133 lines
3.8 KiB
Diff
133 lines
3.8 KiB
Diff
From 5eb28f461a1b368a57994cc3b3f2ba3154c00bb8 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Fri, 9 May 2025 20:23:57 +0000
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Subject: [PATCH] arm64: dts: rockchip: Add GMAC nodes for RK3528
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Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
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Ethernet QoS IP.
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Add device tree nodes for the two Ethernet controllers in RK3528.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Tested-by: Yao Zi <ziyao@disroot.org>
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Link: https://lore.kernel.org/r/20250509202402.260038-2-jonas@kwiboo.se
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3528.dtsi | 105 +++++++++++++++++++++++
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1 file changed, 105 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@@ -677,6 +677,111 @@
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status = "disabled";
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};
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+ gmac0: ethernet@ffbd0000 {
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+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
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+ reg = <0x0 0xffbd0000 0x0 0x10000>;
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+ clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
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+ <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
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+ <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
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+ clock-names = "stmmaceth", "clk_mac_ref",
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+ "mac_clk_rx", "mac_clk_tx",
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+ "pclk_mac", "aclk_mac";
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+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq", "eth_wake_irq";
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+ phy-handle = <&rmii0_phy>;
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+ phy-mode = "rmii";
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+ resets = <&cru SRST_A_MAC_VO>;
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+ reset-names = "stmmaceth";
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+ rockchip,grf = <&vo_grf>;
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+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
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+ snps,mixed-burst;
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+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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+ snps,tso;
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+ status = "disabled";
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+
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+ mdio0: mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <0x1>;
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+ #size-cells = <0x0>;
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+
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+ rmii0_phy: ethernet-phy@2 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0x2>;
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+ clocks = <&cru CLK_MACPHY>;
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+ phy-is-integrated;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&fephym0_led_link>,
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+ <&fephym0_led_spd>;
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+ resets = <&cru SRST_MACPHY>;
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+ };
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+ };
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+
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+ gmac0_stmmac_axi_setup: stmmac-axi-config {
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+ snps,blen = <0 0 0 0 16 8 4>;
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+ snps,rd_osr_lmt = <8>;
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+ snps,wr_osr_lmt = <4>;
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+ };
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+
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+ gmac0_mtl_rx_setup: rx-queues-config {
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+ snps,rx-queues-to-use = <1>;
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+ queue0 {};
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+ };
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+
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+ gmac0_mtl_tx_setup: tx-queues-config {
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+ snps,tx-queues-to-use = <1>;
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+ queue0 {};
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+ };
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+ };
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+
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+ gmac1: ethernet@ffbe0000 {
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+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
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+ reg = <0x0 0xffbe0000 0x0 0x10000>;
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+ clocks = <&cru CLK_GMAC1_SRC_VPU>,
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+ <&cru CLK_GMAC1_RMII_VPU>,
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+ <&cru PCLK_MAC_VPU>,
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+ <&cru ACLK_MAC_VPU>;
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+ clock-names = "stmmaceth",
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+ "clk_mac_ref",
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+ "pclk_mac",
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+ "aclk_mac";
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+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq", "eth_wake_irq";
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+ resets = <&cru SRST_A_MAC>;
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+ reset-names = "stmmaceth";
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+ rockchip,grf = <&vpu_grf>;
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+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
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+ snps,mixed-burst;
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+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
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+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
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+ snps,tso;
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+ status = "disabled";
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+
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+ mdio1: mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <0x1>;
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+ #size-cells = <0x0>;
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+ };
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+
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+ gmac1_stmmac_axi_setup: stmmac-axi-config {
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+ snps,blen = <0 0 0 0 16 8 4>;
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+ snps,rd_osr_lmt = <8>;
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+ snps,wr_osr_lmt = <4>;
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+ };
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+
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+ gmac1_mtl_rx_setup: rx-queues-config {
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+ snps,rx-queues-to-use = <1>;
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+ queue0 {};
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+ };
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+
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+ gmac1_mtl_tx_setup: tx-queues-config {
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+ snps,tx-queues-to-use = <1>;
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+ queue0 {};
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+ };
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+ };
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+
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sdhci: mmc@ffbf0000 {
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compatible = "rockchip,rk3528-dwcmshc",
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"rockchip,rk3588-dwcmshc";
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