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openwrt-25.12
target_linux_rockchip-6.x/patches-6.12/161-02-thermal-rockchip-Add-support-for-RK3528.patch
zhao c4784b5ad0 🍓 Sync 2026-01-16 04:36:33
2026-01-16 04:36:33 +00:00

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From ddd86340a007963e8e893555d64f66b63a174ff7 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 13 Mar 2025 22:51:45 +0000
Subject: [PATCH] thermal: rockchip: Add support for RK3528
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/thermal/rockchip_thermal.c | 117 +++++++++++++++++++++++++++++
1 file changed, 117 insertions(+)
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -206,6 +206,7 @@ struct rockchip_thermal_data {
#define TSADCV2_AUTO_PERIOD_HT 0x6c
#define TSADCV3_AUTO_PERIOD 0x154
#define TSADCV3_AUTO_PERIOD_HT 0x158
+#define TSADCV9_Q_MAX 0x210
#define TSADCV2_AUTO_EN BIT(0)
#define TSADCV2_AUTO_EN_MASK BIT(16)
@@ -216,6 +217,7 @@ struct rockchip_thermal_data {
#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
+#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
@@ -229,6 +231,7 @@ struct rockchip_thermal_data {
#define TSADCV2_DATA_MASK 0xfff
#define TSADCV3_DATA_MASK 0x3ff
#define TSADCV4_DATA_MASK 0x1ff
+#define TSADCV5_DATA_MASK 0x7ff
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
@@ -241,6 +244,9 @@ struct rockchip_thermal_data {
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
+#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
@@ -251,6 +257,8 @@ struct rockchip_thermal_data {
#define PX30_GRF_SOC_CON2 0x0408
+#define RK3528_GRF_TSADC_CON 0x0030
+
#define RK3568_GRF_TSADC_CON 0x0600
#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
@@ -522,6 +530,45 @@ static const struct tsadc_table rk3399_c
{TSADCV3_DATA_MASK, 125000},
};
+static const struct tsadc_table rk3528_code_table[] = {
+ {0, -40000},
+ {1410, -40000},
+ {1419, -35000},
+ {1428, -30000},
+ {1436, -25000},
+ {1445, -20000},
+ {1454, -15000},
+ {1463, -10000},
+ {1471, -5000},
+ {1480, 0},
+ {1489, 5000},
+ {1498, 10000},
+ {1506, 15000},
+ {1515, 20000},
+ {1524, 25000},
+ {1533, 30000},
+ {1541, 35000},
+ {1550, 40000},
+ {1558, 45000},
+ {1567, 50000},
+ {1575, 55000},
+ {1584, 60000},
+ {1593, 65000},
+ {1602, 70000},
+ {1610, 75000},
+ {1619, 80000},
+ {1628, 85000},
+ {1637, 90000},
+ {1646, 95000},
+ {1654, 100000},
+ {1663, 105000},
+ {1672, 110000},
+ {1680, 115000},
+ {1689, 120000},
+ {1697, 125000},
+ {TSADCV5_DATA_MASK, 125000},
+};
+
static const struct tsadc_table rk3568_code_table[] = {
{0, -40000},
{1584, -40000},
@@ -859,6 +906,40 @@ static void rk_tsadcv8_initialize(struct
regs + TSADCV2_AUTO_CON);
}
+static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
+ enum tshut_polarity tshut_polarity)
+{
+ writel_relaxed(TSADCV7_AUTO_PERIOD_TIME,
+ regs + TSADCV3_AUTO_PERIOD);
+ writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME,
+ regs + TSADCV3_AUTO_PERIOD_HT);
+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ writel_relaxed(TSADCV3_Q_MAX_VAL,
+ regs + TSADCV9_Q_MAX);
+ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
+ regs + TSADCV2_AUTO_CON);
+
+ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+ else
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+
+ if (!IS_ERR(grf)) {
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
+ udelay(15);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
+ usleep_range(100, 200);
+ }
+}
+
static void rk_tsadcv2_irq_ack(void __iomem *regs)
{
u32 val;
@@ -1094,6 +1175,15 @@ static int rk_tsadcv2_get_trim_code(cons
return code - base_code;
}
+static int rk_tsadcv3_get_trim_code(const struct chip_tsadc_table *table,
+ int code, int trim_base, int trim_base_frac)
+{
+ int temp = trim_base * 1000 + trim_base_frac * 100;
+ u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
+
+ return (TSADCV3_Q_MAX_VAL - code) - base_code;
+}
+
static const struct rockchip_tsadc_chip px30_tsadc_data = {
/* cpu, gpu */
.chn_offset = 0,
@@ -1292,6 +1382,29 @@ static const struct rockchip_tsadc_chip
},
};
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
+ /* soc */
+ .chn_offset = 0,
+ .chn_num = 1, /* one channel for tsadc */
+ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
+ .tshut_temp = 95000,
+ .initialize = rk_tsadcv11_initialize,
+ .irq_ack = rk_tsadcv4_irq_ack,
+ .control = rk_tsadcv4_control,
+ .get_temp = rk_tsadcv4_get_temp,
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
+ .set_tshut_mode = rk_tsadcv4_tshut_mode,
+ .get_trim_code = rk_tsadcv3_get_trim_code,
+ .trim_slope = 574,
+ .table = {
+ .id = rk3528_code_table,
+ .length = ARRAY_SIZE(rk3528_code_table),
+ .data_mask = TSADCV5_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
/* cpu, gpu */
.chn_offset = 0,
@@ -1396,6 +1509,10 @@ static const struct of_device_id of_rock
.data = (void *)&rk3399_tsadc_data,
},
{
+ .compatible = "rockchip,rk3528-tsadc",
+ .data = (void *)&rk3528_tsadc_data,
+ },
+ {
.compatible = "rockchip,rk3568-tsadc",
.data = (void *)&rk3568_tsadc_data,
},
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