116 lines
3.0 KiB
Diff
116 lines
3.0 KiB
Diff
From 24ddbf99c76a352cc1931ccb5118bca0656034b8 Mon Sep 17 00:00:00 2001
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From: Finley Xiao <finley.xiao@rock-chips.com>
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Date: Tue, 15 Apr 2025 18:32:02 +0800
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Subject: [PATCH] nvmem: rockchip-otp: Add support for RK3568
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This adds the necessary data for handling otp the rk3568.
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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Tested-by: Heiko Stuebner <heiko@sntech.de>
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/nvmem/rockchip-otp.c | 69 ++++++++++++++++++++++++++++++++++++
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1 file changed, 69 insertions(+)
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--- a/drivers/nvmem/rockchip-otp.c
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+++ b/drivers/nvmem/rockchip-otp.c
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@@ -27,6 +27,7 @@
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#define OTPC_USER_CTRL 0x0100
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#define OTPC_USER_ADDR 0x0104
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#define OTPC_USER_ENABLE 0x0108
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+#define OTPC_USER_QP 0x0120
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#define OTPC_USER_Q 0x0124
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#define OTPC_INT_STATUS 0x0304
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#define OTPC_SBPI_CMD0_OFFSET 0x1000
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@@ -184,6 +185,58 @@ read_end:
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return ret;
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}
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+static int rk3568_otp_read(void *context, unsigned int offset, void *val,
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+ size_t count)
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+{
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+ struct rockchip_otp *otp = context;
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+ u16 *buf = val;
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+ u32 otp_qp;
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+ int ret;
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+
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+ ret = rockchip_otp_reset(otp);
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+ if (ret) {
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+ dev_err(otp->dev, "failed to reset otp phy\n");
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+ return ret;
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+ }
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+
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+ ret = rockchip_otp_ecc_enable(otp, true);
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+ if (ret) {
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+ dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
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+ return ret;
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+ }
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+
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+ writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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+ udelay(5);
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+
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+ while (count--) {
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+ writel(offset++ | OTPC_USER_ADDR_MASK,
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+ otp->base + OTPC_USER_ADDR);
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+ writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
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+ otp->base + OTPC_USER_ENABLE);
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+
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+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS,
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+ OTPC_USER_DONE);
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+ if (ret) {
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+ dev_err(otp->dev, "timeout during read setup\n");
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+ goto read_end;
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+ }
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+
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+ otp_qp = readl(otp->base + OTPC_USER_QP);
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+ if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) {
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+ ret = -EIO;
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+ dev_err(otp->dev, "ecc check error during read setup\n");
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+ goto read_end;
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+ }
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+
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+ *buf++ = readl(otp->base + OTPC_USER_Q);
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+ }
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+
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+read_end:
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+ writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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+
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+ return ret;
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+}
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+
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static int rk3588_otp_read(void *context, unsigned int offset,
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void *val, size_t count)
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{
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@@ -280,6 +333,18 @@ static const struct rockchip_data px30_d
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.reg_read = px30_otp_read,
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};
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+static const char * const rk3568_otp_clocks[] = {
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+ "otp", "apb_pclk", "phy", "sbpi",
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+};
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+
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+static const struct rockchip_data rk3568_data = {
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+ .size = 0x80,
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+ .word_size = sizeof(u16),
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+ .clks = rk3568_otp_clocks,
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+ .num_clks = ARRAY_SIZE(rk3568_otp_clocks),
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+ .reg_read = rk3568_otp_read,
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+};
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+
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static const struct rockchip_data rk3576_data = {
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.size = 0x100,
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.read_offset = 0x700,
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@@ -312,6 +377,10 @@ static const struct of_device_id rockchi
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.data = &px30_data,
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},
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{
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+ .compatible = "rockchip,rk3568-otp",
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+ .data = &rk3568_data,
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+ },
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+ {
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.compatible = "rockchip,rk3576-otp",
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.data = &rk3576_data,
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},
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