174 lines
5.0 KiB
Diff
174 lines
5.0 KiB
Diff
From 8ff721f60257d550daf524fc559c0f0d2176b198 Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko@sntech.de>
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Date: Mon, 19 May 2025 00:04:44 +0200
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Subject: [PATCH] arm64: dts: rockchip: move rk3576 pinctrl node outside the
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soc node
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The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
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as dtc points out:
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../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
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Move the pinctrl node outside and adapt the indentation.
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Reported-by: kernel test robot <lkp@intel.com>
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Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/20250518220449.2722673-3-heiko@sntech.de
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 136 +++++++++++------------
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1 file changed, 68 insertions(+), 68 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -429,6 +429,74 @@
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};
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};
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+ pinctrl: pinctrl {
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+ compatible = "rockchip,rk3576-pinctrl";
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+ rockchip,grf = <&ioc_grf>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ gpio0: gpio@27320000 {
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+ compatible = "rockchip,gpio-bank";
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+ reg = <0x0 0x27320000 0x0 0x200>;
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+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
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+ gpio-controller;
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+ gpio-ranges = <&pinctrl 0 0 32>;
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+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #gpio-cells = <2>;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio1: gpio@2ae10000 {
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+ compatible = "rockchip,gpio-bank";
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+ reg = <0x0 0x2ae10000 0x0 0x200>;
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+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
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+ gpio-controller;
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+ gpio-ranges = <&pinctrl 0 32 32>;
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+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #gpio-cells = <2>;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio2: gpio@2ae20000 {
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+ compatible = "rockchip,gpio-bank";
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+ reg = <0x0 0x2ae20000 0x0 0x200>;
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+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
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+ gpio-controller;
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+ gpio-ranges = <&pinctrl 0 64 32>;
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+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #gpio-cells = <2>;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio3: gpio@2ae30000 {
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+ compatible = "rockchip,gpio-bank";
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+ reg = <0x0 0x2ae30000 0x0 0x200>;
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+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
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+ gpio-controller;
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+ gpio-ranges = <&pinctrl 0 96 32>;
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+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #gpio-cells = <2>;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio4: gpio@2ae40000 {
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+ compatible = "rockchip,gpio-bank";
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+ reg = <0x0 0x2ae40000 0x0 0x200>;
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+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
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+ gpio-controller;
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+ gpio-ranges = <&pinctrl 0 128 32>;
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+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #gpio-cells = <2>;
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+ #interrupt-cells = <2>;
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+ };
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+ };
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+
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pmu_a53: pmu-a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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@@ -2349,74 +2417,6 @@
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x4010f000 0x0 0x100>;
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};
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-
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- pinctrl: pinctrl {
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- compatible = "rockchip,rk3576-pinctrl";
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- rockchip,grf = <&ioc_grf>;
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- #address-cells = <2>;
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- #size-cells = <2>;
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- ranges;
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-
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- gpio0: gpio@27320000 {
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- compatible = "rockchip,gpio-bank";
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- reg = <0x0 0x27320000 0x0 0x200>;
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- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
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- gpio-controller;
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- gpio-ranges = <&pinctrl 0 0 32>;
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- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-controller;
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- #gpio-cells = <2>;
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- #interrupt-cells = <2>;
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- };
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-
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- gpio1: gpio@2ae10000 {
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- compatible = "rockchip,gpio-bank";
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- reg = <0x0 0x2ae10000 0x0 0x200>;
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- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
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- gpio-controller;
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- gpio-ranges = <&pinctrl 0 32 32>;
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- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-controller;
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- #gpio-cells = <2>;
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- #interrupt-cells = <2>;
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- };
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-
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- gpio2: gpio@2ae20000 {
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- compatible = "rockchip,gpio-bank";
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- reg = <0x0 0x2ae20000 0x0 0x200>;
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- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
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- gpio-controller;
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- gpio-ranges = <&pinctrl 0 64 32>;
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- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-controller;
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- #gpio-cells = <2>;
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- #interrupt-cells = <2>;
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- };
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-
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- gpio3: gpio@2ae30000 {
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- compatible = "rockchip,gpio-bank";
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- reg = <0x0 0x2ae30000 0x0 0x200>;
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- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
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- gpio-controller;
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- gpio-ranges = <&pinctrl 0 96 32>;
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- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-controller;
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- #gpio-cells = <2>;
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- #interrupt-cells = <2>;
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- };
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-
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- gpio4: gpio@2ae40000 {
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- compatible = "rockchip,gpio-bank";
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- reg = <0x0 0x2ae40000 0x0 0x200>;
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- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
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- gpio-controller;
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- gpio-ranges = <&pinctrl 0 128 32>;
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- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-controller;
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- #gpio-cells = <2>;
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- #interrupt-cells = <2>;
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- };
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- };
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};
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};
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