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rockchip: backport dts changes for Rockchip RK358x

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Backport dts changes up to Linux v6.17 for Rockchip RK358x.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 3adb68ef75)
[rebased upon 24.10 branch, redo patches for kernel 6.6]
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
FUKAUMI Naoki
2025-12-28 18:47:27 +08:00
committed by Tianling Shen
parent 2a6c6e3a54
commit 171e4abe4e
19 changed files with 1339 additions and 0 deletions
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target/linux/rockchip/patches-6.6/030-24-v6.8-dt-bindings-rockchip-vop2-Add-more-endpoint-definition.patch
+28
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@@ -0,0 +1,28 @@
From dc7226acacc6502291446f9e33cf96246ec49a30 Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Mon, 11 Dec 2023 19:59:07 +0800
Subject: [PATCH] dt-bindings: rockchip,vop2: Add more endpoint definition
There are 2 HDMI, 2 DP, 2 eDP on rk3588, so add
corresponding endpoint definition for it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211115907.1785377-1-andyshrk@163.com
---
include/dt-bindings/soc/rockchip,vop2.h | 4 ++++
1 file changed, 4 insertions(+)
--- a/include/dt-bindings/soc/rockchip,vop2.h
+++ b/include/dt-bindings/soc/rockchip,vop2.h
@@ -10,5 +10,9 @@
#define ROCKCHIP_VOP2_EP_LVDS0 5
#define ROCKCHIP_VOP2_EP_MIPI1 6
#define ROCKCHIP_VOP2_EP_LVDS1 7
+#define ROCKCHIP_VOP2_EP_HDMI1 8
+#define ROCKCHIP_VOP2_EP_EDP1 9
+#define ROCKCHIP_VOP2_EP_DP0 10
+#define ROCKCHIP_VOP2_EP_DP1 11
#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
target/linux/rockchip/patches-6.6/050-28-v6.12-arm64-dts-rockchip-rk3588s-fix-sdio-pins-to-pull-up.patch
+39
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@@ -0,0 +1,39 @@
From bd60cae2932cd123d867bf93bdadc4bf545fcdce Mon Sep 17 00:00:00 2001
From: Alex Zhao <zzc@rock-chips.com>
Date: Thu, 29 Aug 2024 15:45:15 -0500
Subject: [PATCH] arm64: dts: rockchip: rk3588s fix sdio pins to pull up
The sdio requires the cmd and data pins to pull up by soc.
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
[adapted to pinctrl filename change]
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20240829204517.398669-2-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
@@ -2449,15 +2449,15 @@
/* sdio_clk_m1 */
<3 RK_PA5 2 &pcfg_pull_none>,
/* sdio_cmd_m1 */
- <3 RK_PA4 2 &pcfg_pull_none>,
+ <3 RK_PA4 2 &pcfg_pull_up>,
/* sdio_d0_m1 */
- <3 RK_PA0 2 &pcfg_pull_none>,
+ <3 RK_PA0 2 &pcfg_pull_up>,
/* sdio_d1_m1 */
- <3 RK_PA1 2 &pcfg_pull_none>,
+ <3 RK_PA1 2 &pcfg_pull_up>,
/* sdio_d2_m1 */
- <3 RK_PA2 2 &pcfg_pull_none>,
+ <3 RK_PA2 2 &pcfg_pull_up>,
/* sdio_d3_m1 */
- <3 RK_PA3 2 &pcfg_pull_none>;
+ <3 RK_PA3 2 &pcfg_pull_up>;
};
};
target/linux/rockchip/patches-6.6/050-29-v6.12-arm64-dts-rockchip-Move-L3-cache-outside-CPUs-in-RK3588-S.patch
+57
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@@ -0,0 +1,57 @@
From df5f6f2f62b9b50cef78f32909485b00fc7cf7f2 Mon Sep 17 00:00:00 2001
From: Dragan Simic <dsimic@manjaro.org>
Date: Thu, 26 Sep 2024 12:29:13 +0200
Subject: [PATCH] arm64: dts: rockchip: Move L3 cache outside CPUs in RK3588(S)
SoC dtsi
Move the "l3_cache" node outside the "cpus" node in the base dtsi file for
Rockchip RK3588(S) SoCs. The A55 and A76 CPU cores in these SoCs belong to
the ARM DynamIQ IP core lineup, which places the L3 cache outside the CPUs
and into the DynamIQ Shared Unit (DSU). [1] Thus, moving the L3 cache DT
node one level higher in the DT improves the way the physical topology of
the RK3588(S) SoCs is represented in the SoC dtsi files.
While there, add a comment that explains it briefly, to save curious readers
from the need to reference the repository log for a clarification.
[1] ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02
Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Helped-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/84264d0713fb51ae2b9b731e28fc14681beea853.1727345965.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 20 +++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -337,15 +337,19 @@
cache-unified;
next-level-cache = <&l3_cache>;
};
+ };
- l3_cache: l3-cache {
- compatible = "cache";
- cache-size = <3145728>;
- cache-line-size = <64>;
- cache-sets = <4096>;
- cache-level = <3>;
- cache-unified;
- };
+ /*
+ * The L3 cache belongs to the DynamIQ Shared Unit (DSU),
+ * so it's represented here, outside the "cpus" node
+ */
+ l3_cache: l3-cache {
+ compatible = "cache";
+ cache-size = <3145728>;
+ cache-line-size = <64>;
+ cache-sets = <4096>;
+ cache-level = <3>;
+ cache-unified;
};
display_subsystem: display-subsystem {
target/linux/rockchip/patches-6.6/050-30-v6.13-arm64-dts-rockchip-Add-HDMI0-node-to-rk3588.patch
+61
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@@ -0,0 +1,61 @@
From d7bb71e69f58c1b3665a9f926bf8d3855111bf8e Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Sat, 19 Oct 2024 13:12:10 +0300
Subject: arm64: dts: rockchip: Add HDMI0 node to rk3588
Add support for the HDMI0 output port found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1258,6 +1258,47 @@
status = "disabled";
};
+ hdmi0: hdmi@fde80000 {
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
+ reg = <0x0 0xfde80000 0x0 0x20000>;
+ clocks = <&cru PCLK_HDMITX0>,
+ <&cru CLK_HDMITX0_EARC>,
+ <&cru CLK_HDMITX0_REF>,
+ <&cru MCLK_I2S5_8CH_TX>,
+ <&cru CLK_HDMIHDP0>,
+ <&cru HCLK_VO1>;
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
+ phys = <&hdptxphy_hdmi0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda>;
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo-grf = <&vo1_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi0_in: port@0 {
+ reg = <0>;
+ };
+
+ hdmi0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
qos_gpu_m0: qos@fdf35000 {
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;
target/linux/rockchip/patches-6.6/050-31-v6.14-arm64-dts-rockchip-Fix-broken-tsadc-pinctrl-names-for.patch
+39
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@@ -0,0 +1,39 @@
From 5c8f9a05336cf5cadbd57ad461621b386aadb762 Mon Sep 17 00:00:00 2001
From: Alexander Shiyan <eagle.alexander923@gmail.com>
Date: Thu, 30 Jan 2025 08:38:49 +0300
Subject: [PATCH] arm64: dts: rockchip: Fix broken tsadc pinctrl names for
rk3588
The tsadc driver does not handle pinctrl "gpio" and "otpout".
Let's use the correct pinctrl names "default" and "sleep".
Additionally, Alexey Charkov's testing [1] has established that
it is necessary for pinctrl state to reference the &tsadc_shut_org
configuration rather than &tsadc_shut for the driver to function correctly.
[1] https://lkml.org/lkml/2025/1/24/966
Fixes: 32641b8ab1a5 ("arm64: dts: rockchip: add rk3588 thermal sensor")
Cc: stable@vger.kernel.org
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Link: https://lore.kernel.org/r/20250130053849.4902-1-eagle.alexander923@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -2555,9 +2555,9 @@
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
- pinctrl-0 = <&tsadc_gpio_func>;
- pinctrl-1 = <&tsadc_shut>;
- pinctrl-names = "gpio", "otpout";
+ pinctrl-0 = <&tsadc_shut_org>;
+ pinctrl-1 = <&tsadc_gpio_func>;
+ pinctrl-names = "default", "sleep";
#thermal-sensor-cells = <1>;
status = "disabled";
};
target/linux/rockchip/patches-6.6/050-32-v6.14-arm64-dts-rockchip-adjust-SMMU-interrupt-type-on-rk3588.patch
+52
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@@ -0,0 +1,52 @@
From 8546cfd08aa4b982acd2357403a1f15495d622ec Mon Sep 17 00:00:00 2001
From: Patrick Wildt <patrick@blueri.se>
Date: Mon, 10 Feb 2025 22:37:29 +0100
Subject: [PATCH] arm64: dts: rockchip: adjust SMMU interrupt type on rk3588
The SMMU architecture requires wired interrupts to be edge triggered,
which does not align with the DT description for the RK3588. This leads
to interrupt storms, as the SMMU continues to hold the pin high and only
pulls it down for a short amount when issuing an IRQ. Update the DT
description to be in line with the spec and perceived reality.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Fixes: cd81d3a0695c ("arm64: dts: rockchip: add rk3588 pcie and php IOMMUs")
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/Z6pxme2Chmf3d3uK@windev.fritz.box
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -549,10 +549,10 @@
mmu600_pcie: iommu@fc900000 {
compatible = "arm,smmu-v3";
reg = <0x0 0xfc900000 0x0 0x200000>;
- interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
#iommu-cells = <1>;
status = "disabled";
@@ -561,10 +561,10 @@
mmu600_php: iommu@fcb00000 {
compatible = "arm,smmu-v3";
reg = <0x0 0xfcb00000 0x0 0x200000>;
- interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>;
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
#iommu-cells = <1>;
status = "disabled";
target/linux/rockchip/patches-6.6/050-33-v6.15-arm64-dts-rockchip-Use-dma-noncoherent-in-base-RK358.patch
+51
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@@ -0,0 +1,51 @@
From 33b561eb66f1e271f2899e103c857d20425076f4 Mon Sep 17 00:00:00 2001
From: Dragan Simic <dsimic@manjaro.org>
Date: Wed, 8 Jan 2025 05:26:45 +0100
Subject: arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi
The preferred way to denote hardware with non-coherent DMA is to use the
"dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS
levels, [1] instead of relying on the compatibles to handle hardware errata,
in this case the Rockchip 3588001 errata. [2]
Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi,
which also goes along with adding initial support for the Rockchip RK3582 SoC
variant, with its separate compatible. [2][3]
[1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
[2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/
[3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/
Cc: Marc Zyngier <maz@kernel.org>
Cc: FUKAUMI Naoki <naoki@radxa.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1909,6 +1909,7 @@
<0x0 0xfe680000 0 0x100000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-controller;
+ dma-noncoherent;
mbi-alias = <0x0 0xfe610000>;
mbi-ranges = <424 56>;
msi-controller;
@@ -1920,6 +1921,7 @@
its0: msi-controller@fe640000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0xfe640000 0x0 0x20000>;
+ dma-noncoherent;
msi-controller;
#msi-cells = <1>;
};
@@ -1927,6 +1929,7 @@
its1: msi-controller@fe660000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0xfe660000 0x0 0x20000>;
+ dma-noncoherent;
msi-controller;
#msi-cells = <1>;
};
target/linux/rockchip/patches-6.6/050-34-v6.15-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch
+28
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@@ -0,0 +1,28 @@
From d0f17738778c12be629ba77ff00c43c3e9eb8428 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 4 Feb 2025 14:40:07 +0200
Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI0 PHY.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -2702,6 +2702,7 @@
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
clock-names = "ref", "apb";
+ #clock-cells = <0>;
#phy-cells = <0>;
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
target/linux/rockchip/patches-6.6/050-35-v6.15-arm64-dts-rockchip-Add-HDMI0-PHY-PLL-clock-source-to.patch
+38
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@@ -0,0 +1,38 @@
From eb4262203d7d85eb7b6f2696816db272e41f5464 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 4 Feb 2025 14:40:08 +0200
Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on
RK3588
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
For now only HDMI0 output is supported, hence add the related PLL clock.
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1150,14 +1150,16 @@
<&cru DCLK_VOP1>,
<&cru DCLK_VOP2>,
<&cru DCLK_VOP3>,
- <&cru PCLK_VOP_ROOT>;
+ <&cru PCLK_VOP_ROOT>,
+ <&hdptxphy_hdmi0>;
clock-names = "aclk",
"hclk",
"dclk_vp0",
"dclk_vp1",
"dclk_vp2",
"dclk_vp3",
- "pclk_vop";
+ "pclk_vop",
+ "pll_hdmiphy0";
iommus = <&vop_mmu>;
power-domains = <&power RK3588_PD_VOP>;
rockchip,grf = <&sys_grf>;
target/linux/rockchip/patches-6.6/050-36-v6.15-arm64-dts-rockchip-Add-PHY-node-for-HDMI1-TX-port-on.patch
+52
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@@ -0,0 +1,52 @@
From ea97212a0f66b7bd71c23c12f781f1770dd6fcff Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Wed, 11 Dec 2024 01:06:15 +0200
Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
In preparation to enable the second HDMI output port found on RK3588
SoC, add the related PHY node. This requires a GRF, hence add the
dependent node as well.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -67,6 +67,11 @@
};
};
+ hdptxphy1_grf: syscon@fd5e4000 {
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+ reg = <0x0 0xfd5e4000 0x0 0x100>;
+ };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -360,6 +365,22 @@
};
};
+ hdptxphy1: phy@fed70000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed70000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
+ clock-names = "ref", "apb";
+ #phy-cells = <0>;
+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
+ <&cru SRST_HDPTX1_LCPLL>;
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+ "lcpll";
+ rockchip,grf = <&hdptxphy1_grf>;
+ status = "disabled";
+ };
+
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;
target/linux/rockchip/patches-6.6/050-37-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch
+44
View File
@@ -0,0 +1,44 @@
From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding@rock-chips.com>
Date: Thu, 6 Feb 2025 11:03:30 +0800
Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
and eDP Link. Therefore, it is better to name it hdptxphy0 other than
hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
[added armsom-sige7, where hdmi-support was added recently and also
the hdptxphy0-as-dclk source I just added]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1151,7 +1151,7 @@
<&cru DCLK_VOP2>,
<&cru DCLK_VOP3>,
<&cru PCLK_VOP_ROOT>,
- <&hdptxphy_hdmi0>;
+ <&hdptxphy0>;
clock-names = "aclk",
"hclk",
"dclk_vp0",
@@ -1276,7 +1276,7 @@
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "avp", "cec", "earc", "main", "hpd";
- phys = <&hdptxphy_hdmi0>;
+ phys = <&hdptxphy0>;
pinctrl-names = "default";
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda>;
@@ -2699,7 +2699,7 @@
#dma-cells = <1>;
};
- hdptxphy_hdmi0: phy@fed60000 {
+ hdptxphy0: phy@fed60000 {
compatible = "rockchip,rk3588-hdptx-phy";
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
target/linux/rockchip/patches-6.6/050-38-v6.15-arm64-dts-rockchip-Add-HDMI1-node-on-RK3588.patch
+63
View File
@@ -0,0 +1,63 @@
From bed6964e779b5853de042da14320edf9f79506fe Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Wed, 11 Dec 2024 01:06:16 +0200
Subject: arm64: dts: rockchip: Add HDMI1 node on RK3588
Add support for the second HDMI TX port found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-3-02cdca22ff68@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -140,6 +140,47 @@
status = "disabled";
};
+ hdmi1: hdmi@fdea0000 {
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
+ reg = <0x0 0xfdea0000 0x0 0x20000>;
+ clocks = <&cru PCLK_HDMITX1>,
+ <&cru CLK_HDMITX1_EARC>,
+ <&cru CLK_HDMITX1_REF>,
+ <&cru MCLK_I2S6_8CH_TX>,
+ <&cru CLK_HDMIHDP1>,
+ <&cru HCLK_VO1>;
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
+ phys = <&hdptxphy1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
+ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo-grf = <&vo1_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi1_in: port@0 {
+ reg = <0>;
+ };
+
+ hdmi1_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
target/linux/rockchip/patches-6.6/050-39-v6.15-arm64-dts-rockchip-Enable-HDMI1-PHY-clk-provider-on-.patch
+27
View File
@@ -0,0 +1,27 @@
From aadaa27956e3430217d9e6b8af5880e39b05b961 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Sun, 23 Feb 2025 11:31:39 +0200
Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI1 PHY.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -411,6 +411,7 @@
reg = <0x0 0xfed70000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
clock-names = "ref", "apb";
+ #clock-cells = <0>;
#phy-cells = <0>;
resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
<&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
target/linux/rockchip/patches-6.6/050-40-v6.15-arm64-dts-rockchip-Add-HDMI1-PHY-PLL-clock-source-to.patch
+48
View File
@@ -0,0 +1,48 @@
From b2e668a60ed866ba960acb5310d1fb6bf81d154f Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Sun, 23 Feb 2025 11:31:40 +0200
Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on
RK3588
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
The HDMI1 PHY PLL clock source cannot be added directly to vop node in
rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
optional feature and its PHY node belongs to a separate (extra) DT file.
Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
clocks & clock-names properties in the extra DT file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -474,3 +474,24 @@
status = "disabled";
};
};
+
+&vop {
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&cru PCLK_VOP_ROOT>,
+ <&hdptxphy0>,
+ <&hdptxphy1>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "pclk_vop",
+ "pll_hdmiphy0",
+ "pll_hdmiphy1";
+};
target/linux/rockchip/patches-6.6/050-41-v6.15-arm64-dts-rockchip-Add-HDMI-audio-outputs-for-rk3588.patch
+91
View File
@@ -0,0 +1,91 @@
From b8c6c136971c0e9750eec89f367529b2854d3a3c Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Mon, 17 Feb 2025 16:47:41 -0500
Subject: arm64: dts: rockchip: Add HDMI audio outputs for rk3588
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node
as CODEC and the i2s5 device as CPU.
Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is
i2s6, but only added in the rk3588-extra.dtsi device tree as the second
TX HDMI port is not available on base versions of the SoC.
The simple-audio-card,mclk-fs value is set to 128 as it is done in
the downstream driver.
The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so
that they can be used as audio codec nodes.
Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger Haikou
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node")
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -382,6 +382,22 @@
};
};
+ hdmi0_sound: hdmi0-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "hdmi0";
+ status = "disabled";
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi0>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s5_8ch>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
@@ -1285,6 +1301,7 @@
reset-names = "ref", "hdp";
rockchip,grf = <&sys_grf>;
rockchip,vo-grf = <&vo1_grf>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -7,6 +7,22 @@
#include "rk3588-extra-pinctrl.dtsi"
/ {
+ hdmi1_sound: hdmi1-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "hdmi1";
+ status = "disabled";
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi1>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s6_8ch>;
+ };
+ };
+
usb_host1_xhci: usb@fc400000 {
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
@@ -165,6 +181,7 @@
reset-names = "ref", "hdp";
rockchip,grf = <&sys_grf>;
rockchip,vo-grf = <&vo1_grf>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {
target/linux/rockchip/patches-6.6/050-42-v6.15-arm64-dts-rockchip-Add-device-tree-support-for-HDMI-.patch
+88
View File
@@ -0,0 +1,88 @@
From 0327238991ba2d1de25e1116b1c064f433e45b8d Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Fri, 7 Mar 2025 12:18:56 +0300
Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller
Add device tree support for Synopsys DesignWare HDMI RX
Controller.
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Link: https://lore.kernel.org/r/20250307091857.646581-2-dmitry.osipenko@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -23,6 +23,30 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * The 4k HDMI capture controller works only with 32bit
+ * phys addresses and doesn't support IOMMU. HDMI RX CMA
+ * must be reserved below 4GB.
+ * The size of 160MB was determined as follows:
+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
+ * To ensure sufficient support for practical use-cases,
+ * we doubled the 66MB value.
+ */
+ hdmi_receiver_cma: hdmi-receiver-cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
+ size = <0x0 (160 * 0x100000)>; /* 160MiB */
+ alignment = <0x0 0x40000>; /* 64K */
+ no-map;
+ status = "disabled";
+ };
+ };
+
usb_host1_xhci: usb@fc400000 {
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
@@ -198,6 +222,37 @@
};
};
+ hdmi_receiver: hdmi_receiver@fdee0000 {
+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
+ reg = <0x0 0xfdee0000 0x0 0x6000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "cec", "hdmi", "dma";
+ clocks = <&cru ACLK_HDMIRX>,
+ <&cru CLK_HDMIRX_AUD>,
+ <&cru CLK_CR_PARA>,
+ <&cru PCLK_HDMIRX>,
+ <&cru CLK_HDMIRX_REF>,
+ <&cru PCLK_S_HDMIRX>,
+ <&cru HCLK_VO1>;
+ clock-names = "aclk",
+ "audio",
+ "cr_para",
+ "pclk",
+ "ref",
+ "hclk_s_hdmirx",
+ "hclk_vo1";
+ memory-region = <&hdmi_receiver_cma>;
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
+ reset-names = "axi", "apb", "ref", "biu";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo1-grf = <&vo1_grf>;
+ status = "disabled";
+ };
+
pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
target/linux/rockchip/patches-6.6/050-43-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch
+46
View File
@@ -0,0 +1,46 @@
From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 20 Feb 2025 19:58:11 +0100
Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
RK3588
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.
This means the system might run into a failure state hanging the
whole system for the following use cases:
* if the GPU driver is being probed late (e.g. build as a
module and firmware is not in initramfs), the regulator
might already have been disabled. In that case the power
domain is enabled before the regulator.
* unbinding the GPU driver will disable the PM domain and
the regulator. When the driver is bound again, the PM
domain will be enabled before the regulator and error
appears.
Avoid this by adding an explicit regulator dependency to the
power domain.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -881,7 +881,7 @@
};
};
/* These power domains are grouped by VD_GPU */
- power-domain@RK3588_PD_GPU {
+ pd_gpu: power-domain@RK3588_PD_GPU {
reg = <RK3588_PD_GPU>;
clocks = <&cru CLK_GPU>,
<&cru CLK_GPU_COREGROUP>,
target/linux/rockchip/patches-6.6/050-44-v6.16-arm64-dts-rockchip-Move-SHMEM-memory-to-reserved-memory-o.patch
+43
View File
@@ -0,0 +1,43 @@
From 8ecd096d018be8a6bd3bd930f3a41a85db66a67d Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Tue, 1 Apr 2025 17:00:09 +0800
Subject: [PATCH] arm64: dts: rockchip: Move SHMEM memory to reserved memory on
rk3588
0x0 to 0xf0000000 are SDRAM memory areas where 0x10f000 is located.
So move the SHMEM memory of arm_scmi to the reserved memory node.
Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250401090009.733771-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -444,16 +444,15 @@
#clock-cells = <0>;
};
- pmu_sram: sram@10f000 {
- compatible = "mmio-sram";
- reg = <0x0 0x0010f000 0x0 0x100>;
- ranges = <0 0x0 0x0010f000 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
- scmi_shmem: sram@0 {
+ scmi_shmem: shmem@10f000 {
compatible = "arm,scmi-shmem";
- reg = <0x0 0x100>;
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ no-map;
};
};
target/linux/rockchip/patches-6.6/051-05-v6.13-arm64-dts-rockchip-Split-up-RK3588-s-PCIe-pinctrls.patch
+444
View File
@@ -0,0 +1,444 @@
From 4294e32111781b3de4d73b944cbd1bc1662a9a7a Mon Sep 17 00:00:00 2001
From: Sam Edwards <cfsworks@gmail.com>
Date: Wed, 11 Sep 2024 19:50:30 -0700
Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
These pinctrls manage the low-speed PCIe signals:
- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
request that external clock-generation circuitry provide a clock.
- PERST#: An input on the RK3588 in EP mode, used to detect a reset
signal from the RC. In RC mode, the hardware does not use this signal:
Linux itself generates it by putting the pin in GPIO mode.
- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
Each of these signals serves a distinct purpose, and more importantly,
PERST# should not be muxed when the RK3588 is in the RC role. Bundling
them together in pinctrl groups prevents proper use: indeed, almost none
of the current board-specific .dts files make any use of them.
(Exception: Rock 5A recently had a patch land that misuses _pins; this
patch corrects that.)
However, on some RK3588 boards, the PCIe 3 controller will indefinitely
stall the boot if CLKREQ# is not muxed (details in the next patch).
This patch unbundles the signals to allow them to be used.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
@@ -1612,23 +1612,43 @@
pcie20x1 {
/omit-if-no-ref/
- pcie20x1m0_pins: pcie20x1m0-pins {
+ pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
rockchip,pins =
/* pcie20x1_2_clkreqn_m0 */
- <3 RK_PC7 4 &pcfg_pull_none>,
+ <3 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m0_perstn: pcie20x1m0-perstn {
+ rockchip,pins =
/* pcie20x1_2_perstn_m0 */
- <3 RK_PD1 4 &pcfg_pull_none>,
+ <3 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m0_waken: pcie20x1m0-waken {
+ rockchip,pins =
/* pcie20x1_2_waken_m0 */
<3 RK_PD0 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie20x1m1_pins: pcie20x1m1-pins {
+ pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
rockchip,pins =
/* pcie20x1_2_clkreqn_m1 */
- <4 RK_PB7 4 &pcfg_pull_none>,
+ <4 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m1_perstn: pcie20x1m1-perstn {
+ rockchip,pins =
/* pcie20x1_2_perstn_m1 */
- <4 RK_PC1 4 &pcfg_pull_none>,
+ <4 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m1_waken: pcie20x1m1-waken {
+ rockchip,pins =
/* pcie20x1_2_waken_m1 */
<4 RK_PC0 4 &pcfg_pull_none>;
};
@@ -1654,52 +1674,127 @@
pcie30x1 {
/omit-if-no-ref/
- pcie30x1m0_pins: pcie30x1m0-pins {
+ pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m0 */
- <0 RK_PC0 12 &pcfg_pull_none>,
+ <0 RK_PC0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m0 */
- <0 RK_PC5 12 &pcfg_pull_none>,
+ <0 RK_PC5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_0_waken: pcie30x1m0-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m0 */
- <0 RK_PC4 12 &pcfg_pull_none>,
+ <0 RK_PC4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m0 */
- <0 RK_PB5 12 &pcfg_pull_none>,
+ <0 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m0 */
- <0 RK_PB7 12 &pcfg_pull_none>,
+ <0 RK_PB7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_waken: pcie30x1m0-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m0 */
<0 RK_PB6 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x1m1_pins: pcie30x1m1-pins {
+ pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m1 */
- <4 RK_PA3 4 &pcfg_pull_none>,
+ <4 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m1 */
- <4 RK_PA5 4 &pcfg_pull_none>,
+ <4 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_0_waken: pcie30x1m1-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m1 */
- <4 RK_PA4 4 &pcfg_pull_none>,
+ <4 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m1 */
- <4 RK_PA0 4 &pcfg_pull_none>,
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m1 */
- <4 RK_PA2 4 &pcfg_pull_none>,
+ <4 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_waken: pcie30x1m1-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m1 */
<4 RK_PA1 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x1m2_pins: pcie30x1m2-pins {
+ pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m2 */
- <1 RK_PB5 4 &pcfg_pull_none>,
+ <1 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m2 */
- <1 RK_PB4 4 &pcfg_pull_none>,
+ <1 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_0_waken: pcie30x1m2-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m2 */
- <1 RK_PB3 4 &pcfg_pull_none>,
+ <1 RK_PB3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m2 */
- <1 RK_PA0 4 &pcfg_pull_none>,
+ <1 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m2 */
- <1 RK_PA7 4 &pcfg_pull_none>,
+ <1 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_waken: pcie30x1m2-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m2 */
<1 RK_PA1 4 &pcfg_pull_none>;
};
@@ -1721,45 +1816,85 @@
pcie30x2 {
/omit-if-no-ref/
- pcie30x2m0_pins: pcie30x2m0-pins {
+ pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m0 */
- <0 RK_PD1 12 &pcfg_pull_none>,
+ <0 RK_PD1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m0_perstn: pcie30x2m0-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m0 */
- <0 RK_PD4 12 &pcfg_pull_none>,
+ <0 RK_PD4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m0_waken: pcie30x2m0-waken {
+ rockchip,pins =
/* pcie30x2_waken_m0 */
<0 RK_PD2 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m1_pins: pcie30x2m1-pins {
+ pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m1 */
- <4 RK_PA6 4 &pcfg_pull_none>,
+ <4 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_perstn: pcie30x2m1-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m1 */
- <4 RK_PB0 4 &pcfg_pull_none>,
+ <4 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_waken: pcie30x2m1-waken {
+ rockchip,pins =
/* pcie30x2_waken_m1 */
<4 RK_PA7 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m2_pins: pcie30x2m2-pins {
+ pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m2 */
- <3 RK_PD2 4 &pcfg_pull_none>,
+ <3 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_perstn: pcie30x2m2-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m2 */
- <3 RK_PD4 4 &pcfg_pull_none>,
+ <3 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_waken: pcie30x2m2-waken {
+ rockchip,pins =
/* pcie30x2_waken_m2 */
<3 RK_PD3 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m3_pins: pcie30x2m3-pins {
+ pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m3 */
- <1 RK_PD7 4 &pcfg_pull_none>,
+ <1 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m3_perstn: pcie30x2m3-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m3 */
- <1 RK_PB7 4 &pcfg_pull_none>,
+ <1 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m3_waken: pcie30x2m3-waken {
+ rockchip,pins =
/* pcie30x2_waken_m3 */
<1 RK_PB6 4 &pcfg_pull_none>;
};
@@ -1774,45 +1909,85 @@
pcie30x4 {
/omit-if-no-ref/
- pcie30x4m0_pins: pcie30x4m0-pins {
+ pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m0 */
- <0 RK_PC6 12 &pcfg_pull_none>,
+ <0 RK_PC6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m0_perstn: pcie30x4m0-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m0 */
- <0 RK_PD0 12 &pcfg_pull_none>,
+ <0 RK_PD0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m0_waken: pcie30x4m0-waken {
+ rockchip,pins =
/* pcie30x4_waken_m0 */
<0 RK_PC7 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m1_pins: pcie30x4m1-pins {
+ pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m1 */
- <4 RK_PB4 4 &pcfg_pull_none>,
+ <4 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m1_perstn: pcie30x4m1-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m1 */
- <4 RK_PB6 4 &pcfg_pull_none>,
+ <4 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m1_waken: pcie30x4m1-waken {
+ rockchip,pins =
/* pcie30x4_waken_m1 */
<4 RK_PB5 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m2_pins: pcie30x4m2-pins {
+ pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m2 */
- <3 RK_PC4 4 &pcfg_pull_none>,
+ <3 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m2_perstn: pcie30x4m2-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m2 */
- <3 RK_PC6 4 &pcfg_pull_none>,
+ <3 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m2_waken: pcie30x4m2-waken {
+ rockchip,pins =
/* pcie30x4_waken_m2 */
<3 RK_PC5 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m3_pins: pcie30x4m3-pins {
+ pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m3 */
- <1 RK_PB0 4 &pcfg_pull_none>,
+ <1 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m3_perstn: pcie30x4m3-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m3 */
- <1 RK_PB2 4 &pcfg_pull_none>,
+ <1 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m3_waken: pcie30x4m3-waken {
+ rockchip,pins =
/* pcie30x4_waken_m3 */
<1 RK_PB1 4 &pcfg_pull_none>;
};
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -309,7 +309,7 @@
};
&pcie2x1l2 {
- pinctrl-0 = <&pcie20x1m0_pins>;
+ pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
pinctrl-names = "default";
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_wf>;
@@ -327,6 +327,10 @@
pow_en: pow-en {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
+
+ pcie2_reset: pcie2-reset {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
power {