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rockchip: refresh upstreamed patches

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2025-11-23 20:14:02 +08:00
parent 1a7dc36c88
commit 2684954fed
3 changed files with 12 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-9tripod-x3568-v4.dts
+1 -1
View File
@@ -172,7 +172,7 @@
vcc3v3_pcie: regulator-vcc3v3-pcie {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie_en_pin>;
regulator-name = "vcc3v3_pcie";
target/linux/rockchip/patches-6.12/107-arm64-dts-rockchip-fix-PCIe-3-3V-regulator-voltage-on.patch → target/linux/rockchip/patches-6.12/013-03-v6.19-arm64-dts-rockchip-fix-PCIe-3-3V-regulator-voltage-on.patch
+7 -9
View File
@@ -1,12 +1,8 @@
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH] arm64: dts: rockchip: fix PCIe 3.3V regulator voltage on
9Tripod X3568 v4
From c8ecda015eb4070ced887eba34cdb60737a9893b Mon Sep 17 00:00:00 2001
From: Coia Prant <coiaprant@gmail.com>
Date: Fri, 14 Nov 2025 17:21:15 +0800
Message-Id: <20251114092114.62664-2-coiaprant@gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Subject: [PATCH] arm64: dts: rockchip: fix PCIe 3.3V regulator voltage on
9Tripod X3568 v4
The regulator type is "regulator-fixed" since its voltage always be
3.3v, min and max should be 3300000 make the regulator has a voltage
@@ -15,13 +11,15 @@ The regulator is supplied by dc_12v, so add the vin-supply.
Link: https://github.com/rockchip-linux/kernel/commit/17e9559f67d26f3c602e38a24feb5194e51ac782
Signed-off-by: Coia Prant <coiaprant@gmail.com>
Link: https://patch.msgid.link/20251114092114.62664-2-coiaprant@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts
@@ -174,16 +174,16 @@
@@ -170,16 +170,16 @@
};
vcc3v3_pcie: regulator-vcc3v3-pcie {
@@ -31,7 +29,7 @@ Signed-off-by: Coia Prant <coiaprant@gmail.com>
- regulator-max-microvolt = <3300000>;
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie_en_pin>;
- gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
target/linux/rockchip/patches-6.12/712-phy-rockchip-naneng-combphy-add-sgmii-mac-sel.patch
+4 -4
View File
@@ -1,6 +1,6 @@
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -178,6 +178,7 @@ struct rockchip_combphy_grfcfg {
@@ -181,6 +181,7 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg pipe_xpcs_phy_ready;
struct combphy_reg pipe_pcie1l0_sel;
struct combphy_reg pipe_pcie1l1_sel;
@@ -8,7 +8,7 @@
struct combphy_reg u3otg0_port_en;
struct combphy_reg u3otg1_port_en;
};
@@ -332,6 +333,7 @@ static struct phy *rockchip_combphy_xlat
@@ -335,6 +336,7 @@ static struct phy *rockchip_combphy_xlat
static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
{
@@ -16,7 +16,7 @@
int i;
priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
@@ -367,6 +369,11 @@ static int rockchip_combphy_parse_dt(str
@@ -370,6 +372,11 @@ static int rockchip_combphy_parse_dt(str
priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
@@ -28,7 +28,7 @@
priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy");
/* fallback to old behaviour */
if (PTR_ERR(priv->phy_rst) == -ENOENT)
@@ -785,6 +792,7 @@ static const struct rockchip_combphy_grf
@@ -792,6 +799,7 @@ static const struct rockchip_combphy_grf
/* pipe-grf */
.pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
.pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },