eternalwrt/eternalwrt-mt798x
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

qualcommbe: ipq9574: describe remaining uniphy resets

Browse Source 
Each uniphy has, besides the XPCS reset, a system reset in the GCC and
a soft reset in the NSSCC. The vendor driver pulses both on every
interface mode change as part of the uniphy bring-up. Describe them,
and name the resets while at it, so the PCS driver can pick them up.

Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/24033
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Kenneth Kasilag
2026-07-06 11:53:43 +02:00
committed by Robert Marko
parent bf6d2e78ba
commit 2d35c376d8
1 changed files with 58 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/qualcommbe/patches-6.18/0356-arm64-dts-qcom-ipq9574-describe-remaining-uniphy-resets.patch
+58
View File
@@ -0,0 +1,58 @@
From: Kenneth Kasilag <kenneth@kasilag.me>
Date: Thu, 02 Jul 2026 00:00:00 +0000
Subject: [PATCH] arm64: dts: qcom: ipq9574: describe remaining uniphy resets
Each uniphy has, besides the XPCS reset, a system reset in the GCC and
a soft reset in the NSSCC. The vendor driver pulses both on every
interface mode change as part of the uniphy bring-up. Describe them,
and name the resets while at it, so the PCS driver can pick them up.
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -1493,7 +1493,12 @@
<&gcc GCC_UNIPHY0_AHB_CLK>;
clock-names = "sys",
"ahb";
- resets = <&gcc GCC_UNIPHY0_XPCS_RESET>;
+ resets = <&gcc GCC_UNIPHY0_XPCS_RESET>,
+ <&gcc GCC_UNIPHY0_SYS_RESET>,
+ <&nsscc UNIPHY0_SOFT_RESET>;
+ reset-names = "xpcs",
+ "sys",
+ "soft";
#clock-cells = <1>;
pcs0_ch0: pcs-mii@0 {
@@ -1538,7 +1543,12 @@
<&gcc GCC_UNIPHY1_AHB_CLK>;
clock-names = "sys",
"ahb";
- resets = <&gcc GCC_UNIPHY1_XPCS_RESET>;
+ resets = <&gcc GCC_UNIPHY1_XPCS_RESET>,
+ <&gcc GCC_UNIPHY1_SYS_RESET>,
+ <&nsscc UNIPHY1_SOFT_RESET>;
+ reset-names = "xpcs",
+ "sys",
+ "soft";
#clock-cells = <1>;
pcs1_ch0: uniphy-ch@0 {
@@ -1559,7 +1569,12 @@
<&gcc GCC_UNIPHY2_AHB_CLK>;
clock-names = "sys",
"ahb";
- resets = <&gcc GCC_UNIPHY2_XPCS_RESET>;
+ resets = <&gcc GCC_UNIPHY2_XPCS_RESET>,
+ <&gcc GCC_UNIPHY2_SYS_RESET>,
+ <&nsscc UNIPHY2_SOFT_RESET>;
+ reset-names = "xpcs",
+ "sys",
+ "soft";
#clock-cells = <1>;
pcs2_ch0: pcs-mii@0 {