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rockchip: fix unstable SGMII on ariaboard photonicat

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This commit is contained in:
Kyosuke Nekoyashiki
2025-05-25 16:23:38 +08:00
committed by Tianling Shen
parent 445f995c78
commit 2ff0f9435f
9 changed files with 149 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
+5
View File
@@ -237,6 +237,7 @@
};
&combphy0 {
rockchip,sgmii-mac-sel = <0>;
status = "okay";
};
@@ -368,7 +369,11 @@
sgmii_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
motorcomm,led-data = <0xe004 0x0000 0x2600 0x0070 0x000a>;
eee-broken-10gt;
eee-broken-10gkx4;
eee-broken-10gkr;
};
};
target/linux/rockchip/patches-6.12/030-18-v6.15-clk-rockchip-rk3568-mark-hclk_vi-as-critical.patch
+31
View File
@@ -0,0 +1,31 @@
From 83dbeca33f7422f4a30c8a91a79d6c0dba4fb6af Mon Sep 17 00:00:00 2001
From: Michael Riesch <michael.riesch@wolfvision.net>
Date: Mon, 10 Feb 2025 09:29:02 +0100
Subject: [PATCH] clk: rockchip: rk3568: mark hclk_vi as critical
The clock 'pclk_vi_niu' has a dependency on 'hclk_vi_niu' according
to the Technical Reference Manual section '2.8.6 NIU Clock gating
reliance'. However, this kind of dependency cannot be addressed
properly at the moment (until the support for linked clocks is
implemented for the RK3568).
As an intermediate solution, mark the hclk_vi as critical on the
Rockchip RK3568.
Suggested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20250210-rk3568-hclk-vi-v1-1-9ade2626f638@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-rk3568.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1602,6 +1602,7 @@ static const char *const rk3568_cru_crit
"pclk_php",
"hclk_usb",
"pclk_usb",
+ "hclk_vi",
"hclk_vo",
};
target/linux/rockchip/patches-6.12/710-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support-for.patch
+1 -1
View File
@@ -37,7 +37,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
static const char * const rk_clocks[] = {
- "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
+ "aclk_mac", "pclk_mac", "pclk_xpcs", "mac_clk_tx", "clk_mac_speed",
+ "aclk_mac", "pclk_mac", "pclk_xpcs", "clk_xpcs_eee", "mac_clk_tx", "clk_mac_speed",
};
static const char * const rk_rmii_clocks[] = {
target/linux/rockchip/patches-6.12/711-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch
+2 -2
View File
@@ -45,13 +45,13 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
- <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
+ <&cru PCLK_XPCS>;
+ <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac",
- "clk_mac_speed", "ptp_ref";
+ "clk_mac_speed", "ptp_ref",
+ "pclk_xpcs";
+ "pclk_xpcs", "clk_xpcs_eee";
resets = <&cru SRST_A_GMAC1>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
target/linux/rockchip/patches-6.12/712-phy-rockchip-naneng-combphy-add-sgmii-mac-sel.patch
+38
View File
@@ -0,0 +1,38 @@
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -122,6 +122,7 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg pipe_xpcs_phy_ready;
struct combphy_reg pipe_pcie1l0_sel;
struct combphy_reg pipe_pcie1l1_sel;
+ struct combphy_reg pipe_sgmii_mac_sel;
};
struct rockchip_combphy_cfg {
@@ -274,6 +275,7 @@ static struct phy *rockchip_combphy_xlat
static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
{
+ int mac_id;
int i;
priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
@@ -309,6 +311,11 @@ static int rockchip_combphy_parse_dt(str
priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
+ if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id)) {
+ rockchip_combphy_param_write(priv->pipe_grf, &priv->cfg->grfcfg->pipe_sgmii_mac_sel,
+ (mac_id > 0) ? true : false);
+ }
+
priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy");
/* fallback to old behaviour */
if (PTR_ERR(priv->phy_rst) == -ENOENT)
@@ -574,6 +581,7 @@ static const struct rockchip_combphy_grf
/* pipe-grf */
.pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
.pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
+ .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 },
};
static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
target/linux/rockchip/patches-6.6/030-18-v6.15-clk-rockchip-rk3568-mark-hclk_vi-as-critical.patch
+31
View File
@@ -0,0 +1,31 @@
From 83dbeca33f7422f4a30c8a91a79d6c0dba4fb6af Mon Sep 17 00:00:00 2001
From: Michael Riesch <michael.riesch@wolfvision.net>
Date: Mon, 10 Feb 2025 09:29:02 +0100
Subject: [PATCH] clk: rockchip: rk3568: mark hclk_vi as critical
The clock 'pclk_vi_niu' has a dependency on 'hclk_vi_niu' according
to the Technical Reference Manual section '2.8.6 NIU Clock gating
reliance'. However, this kind of dependency cannot be addressed
properly at the moment (until the support for linked clocks is
implemented for the RK3568).
As an intermediate solution, mark the hclk_vi as critical on the
Rockchip RK3568.
Suggested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20250210-rk3568-hclk-vi-v1-1-9ade2626f638@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-rk3568.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1593,6 +1593,7 @@ static const char *const rk3568_cru_crit
"hclk_php",
"pclk_php",
"hclk_usb",
+ "hclk_vi",
"hclk_vo",
};
target/linux/rockchip/patches-6.6/710-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support-for.patch
+1 -1
View File
@@ -37,7 +37,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
static const char * const rk_clocks[] = {
- "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
+ "aclk_mac", "pclk_mac", "pclk_xpcs", "mac_clk_tx", "clk_mac_speed",
+ "aclk_mac", "pclk_mac", "pclk_xpcs", "clk_xpcs_eee", "mac_clk_tx", "clk_mac_speed",
};
static const char * const rk_rmii_clocks[] = {
target/linux/rockchip/patches-6.6/711-arm64-dts-rockchip-rk3568-Add-xpcs-support.patch
+2 -2
View File
@@ -45,13 +45,13 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
- <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
+ <&cru PCLK_XPCS>;
+ <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac",
- "clk_mac_speed", "ptp_ref";
+ "clk_mac_speed", "ptp_ref",
+ "pclk_xpcs";
+ "pclk_xpcs", "clk_xpcs_eee";
resets = <&cru SRST_A_GMAC1>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
target/linux/rockchip/patches-6.6/712-phy-rockchip-naneng-combphy-add-sgmii-mac-sel.patch
+38
View File
@@ -0,0 +1,38 @@
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -122,6 +122,7 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg pipe_xpcs_phy_ready;
struct combphy_reg pipe_pcie1l0_sel;
struct combphy_reg pipe_pcie1l1_sel;
+ struct combphy_reg pipe_sgmii_mac_sel;
};
struct rockchip_combphy_cfg {
@@ -274,6 +275,7 @@ static struct phy *rockchip_combphy_xlat
static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
{
+ int mac_id;
int i;
priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
@@ -309,6 +311,11 @@ static int rockchip_combphy_parse_dt(str
priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
+ if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id)) {
+ rockchip_combphy_param_write(priv->pipe_grf, &priv->cfg->grfcfg->pipe_sgmii_mac_sel,
+ (mac_id > 0) ? true : false);
+ }
+
priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy");
/* fallback to old behaviour */
if (PTR_ERR(priv->phy_rst) == -ENOENT)
@@ -574,6 +581,7 @@ static const struct rockchip_combphy_grf
/* pipe-grf */
.pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
.pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
+ .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 },
};
static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {