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realtek: pcs: rtl93xx: make USXGMII config generic

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The USXGMII config setting specific options currently is only
implemented for RTL930x. Looking at the SDK one can see that RTL931x
shares a lot of these configuration options. Additionally, several dumps
from RTK setups have shown that values which aren't set yet by us for
RTL930x but for RTL931x, also apply for RTL930x. Thus, both can be
merged. Start this by making the current function generic for RTL93xx.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22939
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Jonas Jelonek
2026-04-17 12:24:07 +02:00
committed by Robert Marko
parent ed8851d521
commit 440da2900d
1 changed files with 36 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c
+36 -38
View File
@@ -1142,6 +1142,41 @@ static int rtpcs_93xx_sds_set_autoneg(struct rtpcs_serdes *sds, unsigned int neg
}
}
static void rtpcs_93xx_sds_usxgmii_config(struct rtpcs_serdes *sds, u32 opcode, u32 am_period,
u32 all_am_markers, u32 an_table, u32 sync_bit)
{
/* this comes from USXGMII patch sequences of the SDK */
rtpcs_sds_write(sds, 0x06, 0x00, 0x0000);
rtpcs_sds_write(sds, 0x06, 0x0D, 0x0F00);
rtpcs_sds_write(sds, 0x06, 0x1D, 0x0600);
rtpcs_sds_write(sds, 0x07, 0x06, 0x1401); /* CFG_QHSG_TXCFG_MAC_CH0 */
/*
* Controls the USXGMII AN mode. Two states are currently known:
* - 0x03: generic/standard-compliant mode
* - 0xaa: Realtek-proprietary mode (e.g. RTL8224)
*/
rtpcs_sds_write_bits(sds, 0x7, 0x10, 7, 0, opcode); /* CFG_QHSG_AN_OPC */
rtpcs_sds_write_bits(sds, 0x6, 0x12, 15, 0, am_period);
rtpcs_sds_write_bits(sds, 0x6, 0x13, 7, 0, all_am_markers); /* CFG_AM0_M0 */
rtpcs_sds_write_bits(sds, 0x6, 0x13, 15, 8, all_am_markers); /* CFG_AM0_M1 */
rtpcs_sds_write_bits(sds, 0x6, 0x14, 7, 0, all_am_markers); /* CFG_AM0_M2 */
rtpcs_sds_write_bits(sds, 0x6, 0x14, 15, 8, all_am_markers); /* CFG_AM1_M0 */
rtpcs_sds_write_bits(sds, 0x6, 0x15, 7, 0, all_am_markers); /* CFG_AM1_M1 */
rtpcs_sds_write_bits(sds, 0x6, 0x15, 15, 8, all_am_markers); /* CFG_AM1_M2 */
rtpcs_sds_write_bits(sds, 0x6, 0x16, 7, 0, all_am_markers); /* CFG_AM2_M0 */
rtpcs_sds_write_bits(sds, 0x6, 0x16, 15, 8, all_am_markers); /* CFG_AM2_M1 */
rtpcs_sds_write_bits(sds, 0x6, 0x17, 7, 0, all_am_markers); /* CFG_AM2_M2 */
rtpcs_sds_write_bits(sds, 0x6, 0x17, 15, 8, all_am_markers); /* CFG_AM3_M0 */
rtpcs_sds_write_bits(sds, 0x6, 0x18, 7, 0, all_am_markers); /* CFG_AM3_M1 */
rtpcs_sds_write_bits(sds, 0x6, 0x18, 15, 8, all_am_markers); /* CFG_AM3_M2 */
rtpcs_sds_write_bits(sds, 0x6, 0xe, 10, 10, an_table);
rtpcs_sds_write_bits(sds, 0x6, 0x1d, 11, 10, sync_bit);
rtpcs_sds_write_bits(sds, 0x06, 0x03, 15, 15, 0x1); /* FP_TGR3_CFG_EEE_EN */
}
static int rtpcs_93xx_init(struct rtpcs_ctrl *ctrl)
{
u32 model_info = 0;
@@ -2792,43 +2827,6 @@ static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_final_odd[] =
{0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808}
};
static void rtpcs_930x_sds_usxgmii_config(struct rtpcs_serdes *sds,
u32 opcode, u32 am_period,
u32 all_am_markers, u32 an_table,
u32 sync_bit)
{
/* this comes from USXGMII patch sequences of the SDK */
rtpcs_sds_write(sds, 0x06, 0x00, 0x0000);
rtpcs_sds_write(sds, 0x06, 0x0D, 0x0F00);
rtpcs_sds_write(sds, 0x06, 0x1D, 0x0600);
rtpcs_sds_write(sds, 0x07, 0x06, 0x1401); /* CFG_QHSG_TXCFG_MAC_CH0 */
/*
* Controls the USXGMII AN mode. Two states are currently known:
* - 0x03: generic/standard-compliant mode
* - 0xaa: Realtek-proprietary mode (e.g. RTL8224)
*/
rtpcs_sds_write_bits(sds, 0x7, 0x10, 7, 0, opcode); /* CFG_QHSG_AN_OPC */
rtpcs_sds_write_bits(sds, 0x6, 0x12, 15, 0, am_period);
rtpcs_sds_write_bits(sds, 0x6, 0x13, 7, 0, all_am_markers); /* CFG_AM0_M0 */
rtpcs_sds_write_bits(sds, 0x6, 0x13, 15, 8, all_am_markers); /* CFG_AM0_M1 */
rtpcs_sds_write_bits(sds, 0x6, 0x14, 7, 0, all_am_markers); /* CFG_AM0_M2 */
rtpcs_sds_write_bits(sds, 0x6, 0x14, 15, 8, all_am_markers); /* CFG_AM1_M0 */
rtpcs_sds_write_bits(sds, 0x6, 0x15, 7, 0, all_am_markers); /* CFG_AM1_M1 */
rtpcs_sds_write_bits(sds, 0x6, 0x15, 15, 8, all_am_markers); /* CFG_AM1_M2 */
rtpcs_sds_write_bits(sds, 0x6, 0x16, 7, 0, all_am_markers); /* CFG_AM2_M0 */
rtpcs_sds_write_bits(sds, 0x6, 0x16, 15, 8, all_am_markers); /* CFG_AM2_M1 */
rtpcs_sds_write_bits(sds, 0x6, 0x17, 7, 0, all_am_markers); /* CFG_AM2_M2 */
rtpcs_sds_write_bits(sds, 0x6, 0x17, 15, 8, all_am_markers); /* CFG_AM3_M0 */
rtpcs_sds_write_bits(sds, 0x6, 0x18, 7, 0, all_am_markers); /* CFG_AM3_M1 */
rtpcs_sds_write_bits(sds, 0x6, 0x18, 15, 8, all_am_markers); /* CFG_AM3_M2 */
rtpcs_sds_write_bits(sds, 0x6, 0xe, 10, 10, an_table);
rtpcs_sds_write_bits(sds, 0x6, 0x1d, 11, 10, sync_bit);
rtpcs_sds_write_bits(sds, 0x06, 0x03, 15, 15, 0x1); /* FP_TGR3_CFG_EEE_EN */
}
static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode)
{
int (*apply_fn)(struct rtpcs_serdes *, const struct rtpcs_sds_config *, size_t);
@@ -2926,7 +2924,7 @@ static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sd
if (!is_xsgmii)
/* opcode 0x03: standard/generic USXGMII mode */
rtpcs_930x_sds_usxgmii_config(sds, 0x03, 0xa4, 0, 1, 0x1);
rtpcs_93xx_sds_usxgmii_config(sds, 0x03, 0xa4, 0, 1, 0x1);
break;
default: