Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
2026-03-11 11:34:16 +08:00
parent bbddf65c9d 87c2c474f2
commit 49b9a1a2f6
45 changed files with 1515 additions and 180 deletions
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2025 OpenWrt.org
+#
+
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(board_name)
+
+case "$board" in
+gemtek,w1700k-ubi)
+	ubootenv_add_ubi_default
+	;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config
+
+exit 0
@@ -501,7 +501,6 @@ static long rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)

 static const struct file_operations rtc_fops = {
 	.owner		= THIS_MODULE,
-	.llseek		= no_llseek,
 	.read		= rtc_read,
 	.write		= rtc_write,
 	.unlocked_ioctl	= rtc_ioctl,
@@ -5,9 +5,9 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/ustream-ssl.git
-PKG_SOURCE_DATE:=2025-10-03
-PKG_SOURCE_VERSION:=5a81c108d20e24724ed847cc4be033f2a74e6635
-PKG_MIRROR_HASH:=e251189ed315f22ab63dc6f17b03178676e10c21fff0cdd863b294a3c51a1b5b
+PKG_SOURCE_DATE:=2026-03-01
+PKG_SOURCE_VERSION:=99f1c0db5a729f615bc5114b3b52fd8ac8083f34
+PKG_MIRROR_HASH:=631ce829a510895cdf0bcfa48970e963e6c910ccd09718b90d85e455ec35f290
 CMAKE_INSTALL:=1

 PKG_LICENSE:=ISC
@@ -5,7 +5,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=firewall4
-PKG_RELEASE:=1
+PKG_RELEASE:=2

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/firewall4.git
@@ -28,6 +28,7 @@ define Package/firewall4
 	+ucode +ucode-mod-fs +ucode-mod-ubus +ucode-mod-uci
  EXTRA_DEPENDS:=ucode (>=2022.03.22)
  PROVIDES:=uci-firewall
+  DEFAULT_VARIANT:=1
 endef

 define Package/firewall4/description
@@ -177,17 +177,19 @@ function setup_sta(data, config) {
 	config.basic_rate = ratelist(config.basic_rate);
 	config.mcast_rate = ratestr(config.mcast_rate);

-	network_append_string_vars(config, [ 'ssid' ]);
+	network_append_string_vars(config, [ 'ssid',
+		'identity', 'anonymous_identity', 'password',
+		'ca_cert', 'ca_cert2', 'client_cert', 'client_cert2', 'subject_match',
+		'private_key', 'private_key_passwd', 'private_key2', 'private_key2_passwd',
+		 ]);
 	network_append_vars(config, [
 		'rsn_overriding', 'scan_ssid', 'noscan', 'disabled', 'multi_ap_profile', 'multi_ap_backhaul_sta',
 		'ocv', 'beacon_prot', 'key_mgmt', 'sae_pwe', 'psk', 'sae_password', 'pairwise', 'group', 'bssid',
 		'proto', 'mesh_fwding', 'mesh_rssi_threshold', 'frequency', 'fixed_freq',
 		'disable_ht', 'disable_ht40', 'disable_vht', 'vht', 'max_oper_chwidth',
 		'ht40', 'beacon_int', 'ieee80211w', 'basic_rate', 'mcast_rate',
-		'bssid_blacklist', 'bssid_whitelist', 'erp', 'ca_cert', 'identity',
-		'anonymous_identity', 'client_cert', 'private_key', 'private_key_passwd',
-		'subject_match', 'altsubject_match', 'domain_match', 'domain_suffix_match',
-		'ca_cert2', 'client_cert2', 'private_key2', 'private_key2_passwd', 'password',
+		'altsubject_match', 'domain_match', 'domain_suffix_match',
+		'bssid_blacklist', 'bssid_whitelist', 'erp',
 		'dpp_connector', 'dpp_csign', 'dpp_netaccesskey',
 	]);
 }
@@ -1,7 +1,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=apk
-PKG_RELEASE:=1
+PKG_RELEASE:=2

 PKG_SOURCE_URL=https://gitlab.alpinelinux.org/alpine/apk-tools.git
 PKG_SOURCE_PROTO:=git
@@ -0,0 +1,13 @@
+diff --git a/src/genhelp_apk.lua b/src/genhelp_apk.lua
+index a62e84d22ed5..a97264f6ab3c 100644
+--- a/src/genhelp_apk.lua
+++ b/src/genhelp_apk.lua
+@@ -65,7 +65,7 @@ local function render_options(doc, out, options)
+ end
+ 
+ local function render_footer(doc, out)
+-	table.insert(out, ("\nFor more information: man %s %s\n"):format(doc.mansection, doc.manpage))
+	table.insert(out, ("\nFor more information:\n  https://openwrt.org/docs/guide-user/additional-software/apk\n"))
+ end
+ 
+ local function render_optgroups(doc, out, groups)
@@ -0,0 +1,48 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 8 Mar 2026 13:41:16 +0000
+Subject: [PATCH] add: add --force-reinstall option
+
+Allow reinstalling already-installed packages without a version change.
+Only the named packages are reinstalled, not their dependencies.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/src/app_add.c
+++ b/src/app_add.c
+@@ -24,6 +24,7 @@ struct add_ctx {
+ 	OPT(OPT_ADD_initdb,	"initdb") \
+ 	OPT(OPT_ADD_latest,	APK_OPT_SH("l") "latest") \
+ 	OPT(OPT_ADD_no_chown,   "no-chown") \
+	OPT(OPT_ADD_reinstall,	"force-reinstall") \
+ 	OPT(OPT_ADD_upgrade,	APK_OPT_SH("u") "upgrade") \
+ 	OPT(OPT_ADD_usermode,	"usermode") \
+ 	OPT(OPT_ADD_virtual,	APK_OPT_ARG APK_OPT_SH("t") "virtual")
+@@ -41,6 +42,9 @@ static int add_parse_option(void *ctx, s
+ 	case OPT_ADD_latest:
+ 		actx->solver_flags |= APK_SOLVERF_LATEST;
+ 		break;
+	case OPT_ADD_reinstall:
+		actx->solver_flags |= APK_SOLVERF_REINSTALL;
+		break;
+ 	case OPT_ADD_upgrade:
+ 		actx->solver_flags |= APK_SOLVERF_UPGRADE;
+ 		break;
+@@ -177,7 +181,7 @@ static int add_main(void *ctx, struct ap
+ 			apk_deps_add(&world, &dep);
+ 			apk_solver_set_name_flags(dep.name,
+ 						  actx->solver_flags,
+-						  actx->solver_flags);
+						  actx->solver_flags & ~APK_SOLVERF_REINSTALL);
+ 		}
+ 	}
+ 	if (actx->virtpkg) {
+@@ -185,7 +189,7 @@ static int add_main(void *ctx, struct ap
+ 		apk_deps_add(&world, &virtdep);
+ 		apk_solver_set_name_flags(virtdep.name,
+ 					  actx->solver_flags,
+-					  actx->solver_flags);
+					  actx->solver_flags & ~APK_SOLVERF_REINSTALL);
+ 	}
+ 
+ 	r = apk_solver_commit(db, 0, world);
@@ -5,6 +5,7 @@ from pathlib import Path
 from subprocess import run, PIPE
 from sys import argv
 import json
+import re

 if len(argv) != 2:
    print("JSON info files script requires output file as argument")
@@ -31,8 +32,12 @@ def get_initial_output(image_info):

 def add_artifact(artifact, prefix="openwrt-"):
    files = list(output_dir.glob(f"{prefix}{artifact}-*"))
-    if len(files) == 1:
-        output[artifact] = str(files[0].name)
+    if len(files):
+        output[artifact] = {}
+        for file in files:
+            file = str(file.name)
+            arch = re.match(r".*Linux-([^.]*)\.", file).group(1)
+            output[artifact][arch] = file


 for json_file in work_dir.glob("*.json"):
@@ -9,5 +9,7 @@ FEATURES:=dt squashfs nand ramdisk gpio
 KERNEL_PATCHVER:=6.12

 include $(INCLUDE_DIR)/target.mk
+DEFAULT_PACKAGES += \
+	kmod-leds-gpio kmod-gpio-button-hotplug

 $(eval $(call BuildTarget))
@@ -13,6 +13,12 @@ airoha,an7581-evb)
 	ucidef_set_led_usbport "usb1" "USB 1" "green:usb-1" "usb1-port1" "usb2-port1"
 	ucidef_set_led_usbport "usb2" "USB 2" "green:usb-2" "usb3-port1" "usb4-port1"
 	;;
+gemtek,w1700k-ubi)
+	ucidef_set_led_netdev "lan3-yellow" "lan3" "yellow:lan-3" "lan3" "link_10 link_100"
+	ucidef_set_led_netdev "lan3-green" "lan3" "green:lan-3" "lan3" "link_1000 tx rx"
+	ucidef_set_led_netdev "lan4-yellow" "lan4" "yellow:lan-4" "lan4" "link_10 link_100"
+	ucidef_set_led_netdev "lan4-green" "lan4" "green:lan-4" "lan4" "link_1000 tx rx"
+	;;
 esac

 board_config_flush
@@ -14,6 +14,9 @@ an7581_setup_interfaces()
 	airoha,an7581-evb)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "eth1"
 		;;
+	gemtek,w1700k-ubi)
+		ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" "wan"
+		;;
 	*)
 		echo "Unsupported hardware. Network interfaces not initialized"
 		;;
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2025 openwrt.org
+#
+
+START=99
+
+. /lib/functions.sh
+
+find_nct7802()
+{
+	for hwmon in /sys/class/hwmon/hwmon*; do
+		if [ -f "$hwmon/name" ] && [ "$(cat "$hwmon/name" 2>/dev/null)" = "nct7802" ]; then
+			echo "$hwmon"
+			return
+		fi
+	done
+	echo "/sys/class/hwmon/hwmon5" # fallback
+}
+
+boot()
+{
+	case $(board_name) in
+	gemtek,w1700k-ubi)
+		hwmon=$(find_nct7802)
+
+		# Temporarily disable automatic fan control to configure curve
+		echo 1 > $hwmon/pwm1_enable
+
+		# Match trigger points from vendor firmware
+		echo 40000 > $hwmon/pwm1_auto_point1_temp
+		echo 50000 > $hwmon/pwm1_auto_point2_temp
+		echo 60000 > $hwmon/pwm1_auto_point3_temp
+		echo 70000 > $hwmon/pwm1_auto_point4_temp
+		echo 80000 > $hwmon/pwm1_auto_point5_temp
+
+		# Match fan speed from vendor firmware
+		echo 54  > $hwmon/pwm1_auto_point1_pwm
+		echo 69  > $hwmon/pwm1_auto_point2_pwm
+		echo 95  > $hwmon/pwm1_auto_point3_pwm
+		echo 199 > $hwmon/pwm1_auto_point4_pwm
+
+		# Re-enable automatic fan control
+		echo 2 > $hwmon/pwm1_enable
+		;;
+	esac
+}
+
@@ -0,0 +1,19 @@
+REQUIRE_IMAGE_METADATA=1
+RAMFS_COPY_BIN='fitblk fit_check_sign'
+
+platform_do_upgrade() {
+	local board=$(board_name)
+
+	case "$board" in
+		gemtek,w1700k-ubi)
+			fit_do_upgrade "$1"
+			;;
+		*)
+			nand_do_upgrade "$1"
+			;;
+	esac
+}
+
+platform_check_image() {
+	return 0
+}
@@ -3,10 +3,10 @@ SUBTARGET:=an7581
 BOARDNAME:=AN7581 / AN7566 / AN7551
 CPU_TYPE:=cortex-a53
 KERNELNAME:=Image dtbs
-FEATURES+=pwm source-only
+FEATURES+=pwm

 DEFAULT_PACKAGES += \
-	airoha-en7581-npu-firmware
+	airoha-en7581-npu-firmware uboot-envtools

 define Target/Description
 	Build firmware images for Airoha an7581 ARM based boards.
@@ -241,7 +241,7 @@ CONFIG_MUTEX_SPIN_ON_OWNER=y
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEED_SG_DMA_LENGTH=y
 CONFIG_NET_AIROHA=y
-CONFIG_NET_AIROHA_FLOW_STATS=y
+# CONFIG_NET_AIROHA_FLOW_STATS is not set
 CONFIG_NET_AIROHA_NPU=y
 CONFIG_NET_DEVLINK=y
 CONFIG_NET_DSA=y
@@ -204,6 +204,10 @@
 	status = "okay";
 };

+&npu {
+	status = "okay";
+};
+
 &eth {
 	status = "okay";
 };
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "an7581.dtsi"
+
+/ {
+	model = "Gemtek W1700K (OpenWrt U-Boot layout)";
+	compatible = "gemtek,w1700k-ubi", "airoha,an7581", "airoha,en7581";
+
+	aliases {
+		serial0 = &uart1;
+		led-boot = &led_status_red;
+		led-failsafe = &led_status_blue;
+		led-upgrade = &led_status_blue;
+		led-running = &led_status_green;
+	};
+
+	chosen {
+		rootdisk = <&ubi_rootfs>;
+		bootargs = "console=ttyS0,115200 earlycon ubi.block=0,fit root=/dev/fit0 rootwait";
+		stdout-path = "serial0:115200n8";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		key-restart {
+			label = "reset";
+			gpios = <&en7581_pinctrl 0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_green: led-0 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&en7581_pinctrl 17 GPIO_ACTIVE_LOW>;
+		};
+
+		led_status_blue: led-1 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&en7581_pinctrl 19 GPIO_ACTIVE_LOW>;
+		};
+
+		led_status_red: led-2 {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&en7581_pinctrl 29 GPIO_ACTIVE_LOW>;
+		};
+
+		led_status_white: led-3 {
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&en7581_pinctrl 20 GPIO_ACTIVE_LOW>;
+		};
+
+		led-4 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <3>;
+			gpios = <&en7581_pinctrl 9 GPIO_ACTIVE_LOW>;
+		};
+
+		led-5 {
+			color = <LED_COLOR_ID_YELLOW>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <3>;
+			gpios = <&en7581_pinctrl 10 GPIO_ACTIVE_LOW>;
+		};
+
+		led-6 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <4>;
+			gpios = <&en7581_pinctrl 27 GPIO_ACTIVE_LOW>;
+		};
+
+		led-7 {
+			color = <LED_COLOR_ID_YELLOW>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <4>;
+			gpios = <&en7581_pinctrl 28 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&en7581_pinctrl {
+	gpio-ranges = <&en7581_pinctrl 0 13 47>;
+
+	mdio_pins: mdio-pins {
+		mux {
+			function = "mdio";
+			groups = "mdio";
+		};
+
+		conf {
+			pins = "gpio2";
+			output-high;
+		};
+	};
+
+	pcie0_rst_pins: pcie0-rst-pins {
+		conf {
+			pins = "pcie_reset0";
+			drive-open-drain = <1>;
+		};
+	};
+
+	pcie2_rst_pins: pcie2-rst-pins {
+		conf {
+			pins = "pcie_reset2";
+			drive-open-drain = <1>;
+		};
+	};
+
+	/* W1700K does not use the built-in LED controller. Instead, it uses GPIO.
+	 * The driver fails to probe without gswpX_led0_pins defined, so put a dummy
+	 * here.
+	 */
+
+	gswp1_led0_pins: gswp1-led0-pins {
+		mux {
+			function = "phy1_led0";
+			pins = "gpio33";
+		};
+	};
+
+	gswp2_led0_pins: gswp2-led0-pins {
+		mux {
+			function = "phy2_led0";
+			pins = "gpio34";
+		};
+	};
+
+	uart2_pins: uart2-pins {
+		mux {
+			function = "uart";
+			groups = "uart2";
+		};
+	};
+
+	hsuart_pins: hsuart-pins {
+		mux {
+			function = "uart";
+			groups = "hsuart";
+		};
+	};
+};
+
+&snfi {
+	status = "okay";
+};
+
+&spi_nand {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "vendor";
+			reg = <0x00000000 0x00600000>;
+			read-only;
+		};
+
+		partition@600000 {
+			label = "chainloader";
+			reg = <0x00600000 0x00100000>;
+			read-only;
+		};
+
+		partition@700000 {
+			label = "ubi";
+			reg = <0x00700000 0x1f700000>;
+			compatible = "linux,ubi";
+
+			volumes {
+				ubi-volume-ubootenv {
+					volname = "ubootenv";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool";
+					};
+				};
+
+				ubi-volume-ubootenv2 {
+					volname = "ubootenv2";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool";
+					};
+				};
+
+				ubi_rootfs: ubi-volume-fit {
+					volname = "fit";
+				};
+
+				ubi_factory: ubi-volume-factory {
+					volname = "factory";
+				};
+			};
+		};
+
+		/* reserved for bad block table */
+		reserved_bmt@1fe00000 {
+			label = "reserved_bmt";
+			reg = <0x1fe00000 0x00200000>;
+			read-only;
+		};
+	};
+};
+
+&ubi_factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eeprom: eeprom@0 {
+			reg = <0x0 0x1e00>;
+		};
+
+		wan_mac: macaddr@5000 {
+			reg = <0x5000 0x6>;
+		};
+
+		lan_mac: macaddr@6000 {
+			compatible = "mac-base";
+			reg = <0x6000 0x6>;
+			#nvmem-cell-cells = <1>;
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	hwmon@2e {
+		compatible = "nuvoton,nct7802";
+		reg = <0x2e>;
+	};
+};
+
+&pcie0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_rst_pins>;
+	pcie@0,0 {
+		reg = <0x0000 0 0 0 0>;
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		mt7996@0,0 {
+			reg = <0x0000 0 0 0 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			nvmem-cells = <&eeprom>;
+			nvmem-cell-names = "eeprom";
+			airoha,npu = <&npu>;
+			airoha,eth = <&eth>;
+
+			band@0 {
+				/* 2.4 GHz */
+				reg = <0>;
+				nvmem-cells = <&lan_mac 1>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			band@1 {
+				/* 5 GHz */
+				reg = <1>;
+				nvmem-cells = <&lan_mac 2>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			band@2 {
+				/* 6 GHz */
+				reg = <2>;
+				nvmem-cells = <&lan_mac 3>;
+				nvmem-cell-names = "mac-address";
+			};
+		};
+	};
+};
+
+&pcie2 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_rst_pins>;
+};
+
+&npu {
+	firmware-name = "airoha/en7581_MT7996_npu_rv32.bin",
+		"airoha/en7581_MT7996_npu_data.bin";
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+};
+
+&gdm1 {
+	status = "okay";
+
+	nvmem-cells = <&lan_mac 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gdm2 {
+	status = "okay";
+
+	phy-handle = <&phy8>;
+	phy-mode = "usxgmii";
+
+	nvmem-cells = <&wan_mac 0>;
+	nvmem-cell-names = "mac-address";
+	openwrt,netdev-name = "wan";
+};
+
+&gdm4 {
+	status = "okay";
+
+	phy-handle = <&phy5>;
+	phy-mode = "usxgmii";
+
+	nvmem-cells = <&lan_mac 0>;
+	nvmem-cell-names = "mac-address";
+	openwrt,netdev-name = "lan2";
+};
+
+&switch {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>;
+
+	mdio {
+		phy5: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <5>;
+			reset-gpios = <&en7581_pinctrl 46 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <40000>;
+			reset-deassert-us = <150000>;
+			interrupt-parent = <&en7581_pinctrl>;
+			interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+			realtek,pnswap-tx;
+			realtek,pnswap-rx;
+		};
+
+		phy8: ethernet-phy@8 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <8>;
+			reset-gpios = <&en7581_pinctrl 31 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <40000>;
+			reset-deassert-us = <150000>;
+			interrupt-parent = <&en7581_pinctrl>;
+			interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+			realtek,pnswap-tx;
+			realtek,pnswap-rx;
+		};
+	};
+};
+
+&gsw_phy1 {
+	status = "okay";
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gswp1_led0_pins>;
+};
+
+&gsw_port1 {
+	status = "okay";
+	label = "lan3";
+};
+
+&gsw_phy2 {
+	status = "okay";
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gswp2_led0_pins>;
+};
+
+&gsw_port2 {
+	status = "okay";
+	label = "lan4";
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+};
+
+&hsuart3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsuart_pins>;
+};
@@ -69,3 +69,38 @@ define Device/airoha_an7581-evb-emmc
  ARTIFACTS := preloader.bin bl31-uboot.fip
 endef
 TARGET_DEVICES += airoha_an7581-evb-emmc
+
+define Device/gemtek_w1700k-ubi
+  DEVICE_VENDOR := Gemtek
+  DEVICE_MODEL := W1700K
+  DEVICE_VARIANT := UBI
+  DEVICE_ALT0_VENDOR := CenturyLink
+  DEVICE_ALT0_MODEL := W1700K
+  DEVICE_ALT0_VARIANT := UBI
+  DEVICE_ALT1_VENDOR := Lumen
+  DEVICE_ALT1_MODEL := W1700K
+  DEVICE_ALT1_VARIANT := UBI
+  DEVICE_ALT2_VENDOR := Quantum Fiber
+  DEVICE_ALT2_MODEL := W1700K
+  DEVICE_ALT2_VARIANT := UBI
+  DEVICE_DTS := an7581-w1700k-ubi
+  DEVICE_PACKAGES := airoha-en7581-mt7996-npu-firmware \
+		    fitblk kmod-i2c-an7581 kmod-hwmon-nct7802 \
+		    kmod-mt7996-firmware kmod-phy-rtl8261n \
+		    wpad-basic-mbedtls
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  UBOOTENV_IN_UBI := 1
+  KERNEL_IN_UBI := 1
+  KERNEL := kernel-bin | gzip
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 128k
+  KERNEL_INITRAMFS_SUFFIX := -recovery.itb
+  IMAGES := sysupgrade.itb
+  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
+  ARTIFACTS := chainload-uboot.itb
+  ARTIFACT/chainload-uboot.itb := an7581-chainloader gemtek_w1700k
+  SOC := an7581
+endef
+TARGET_DEVICES += gemtek_w1700k-ubi
@@ -0,0 +1,101 @@
+From 99816c896b07f743452e3be42b47f4df364e486f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 10 Mar 2026 16:16:03 +0100
+Subject: [PATCH] pinctrl: airoha: permit GPIO43-46 for PHY LED0
+
+On some board it was found that also the GPIO pin range from 43 to 46 can be
+used for PHY LED0. Add these additional GPIO pins to the function groups.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 48 +++++++++++++++++++++--
+ 1 file changed, 44 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -904,13 +904,21 @@ static const char *const pwm_groups[] =
+ 					  "gpio44", "gpio45",
+ 					  "gpio46", "gpio47" };
+ static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
+-						"gpio35", "gpio42" };
+						"gpio35", "gpio42",
+						"gpio43", "gpio44",
+						"gpio45", "gpio46" };
+ static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
+-						"gpio35", "gpio42" };
+						"gpio35", "gpio42",
+						"gpio43", "gpio44",
+						"gpio45", "gpio46" };
+ static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
+-						"gpio35", "gpio42" };
+						"gpio35", "gpio42",
+						"gpio43", "gpio44",
+						"gpio45", "gpio46" };
+ static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
+-						"gpio35", "gpio42" };
+						"gpio35", "gpio42",
+						"gpio43", "gpio44",
+						"gpio45", "gpio46" };
+ static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
+ 						"gpio45", "gpio46" };
+ static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
+@@ -1548,6 +1556,14 @@ static const struct airoha_pinctrl_func_
+ 				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ 	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio43", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio44", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio45", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio46", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+ };
+ 
+ static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+@@ -1559,6 +1575,14 @@ static const struct airoha_pinctrl_func_
+ 				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ 	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio43", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio44", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio45", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio46", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+ };
+ 
+ static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+@@ -1570,6 +1594,14 @@ static const struct airoha_pinctrl_func_
+ 				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ 	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio43", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio44", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio45", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio46", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+ };
+ 
+ static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+@@ -1581,6 +1613,14 @@ static const struct airoha_pinctrl_func_
+ 				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ 	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio43", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio44", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio45", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio46", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+ };
+ 
+ static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
@@ -0,0 +1,90 @@
+From 9f60f2d9e1920245acbb9b0493d0c073905c3976 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 8 Jan 2026 23:40:26 +0100
+Subject: [PATCH] ARM: dts: BCM5301X: Describe PCIe controllers fully
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Tested successfully on BCM47094 SoC using Linux's pcie-iproc-platform
+driver.
+
+This fixes:
+arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dtb: pcie@12000: 'device_type' is a required property
+        from schema $id: http://devicetree.org/schemas/pci/pci-bus.yaml#
+arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dtb: pcie@12000: 'ranges' is a required property
+        from schema $id: http://devicetree.org/schemas/pci/pci-bus.yaml#
+arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dtb: pcie@13000: 'device_type' is a required property
+        from schema $id: http://devicetree.org/schemas/pci/pci-bus.yaml#
+arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dtb: pcie@13000: 'ranges' is a required property
+        from schema $id: http://devicetree.org/schemas/pci/pci-bus.yaml#
+arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dtb: pcie@14000: 'device_type' is a required property
+        from schema $id: http://devicetree.org/schemas/pci/pci-bus.yaml#
+arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dtb: pcie@14000: 'ranges' is a required property
+        from schema $id: http://devicetree.org/schemas/pci/pci-bus.yaml#
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20260108224026.3550-1-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
+---
+ arch/arm/boot/dts/broadcom/bcm-ns.dtsi | 26 +++++++++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
+@@ -95,7 +95,10 @@
+ 	axi@18000000 {
+ 		compatible = "brcm,bus-axi";
+ 		reg = <0x18000000 0x1000>;
+-		ranges = <0x00000000 0x18000000 0x00100000>;
+		ranges = <0x00000000 0x18000000 0x00100000>,
+			 <0x08000000 0x08000000 0x08000000>,
+			 <0x20000000 0x20000000 0x08000000>,
+			 <0x28000000 0x28000000 0x08000000>;
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+ 
+@@ -182,22 +185,43 @@
+ 		};
+ 
+ 		pcie0: pcie@12000 {
+			compatible = "brcm,iproc-pcie";
+ 			reg = <0x00012000 0x1000>;
+			ranges = <0x82000000 0 0x08000000  0x08000000  0 0x08000000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";
+ 
+			#interrupt-cells = <1>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 		};
+ 
+ 		pcie1: pcie@13000 {
+			compatible = "brcm,iproc-pcie";
+ 			reg = <0x00013000 0x1000>;
+			ranges = <0x82000000 0 0x20000000  0x20000000  0 0x08000000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";
+ 
+			#interrupt-cells = <1>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 		};
+ 
+ 		pcie2: pcie@14000 {
+			compatible = "brcm,iproc-pcie";
+ 			reg = <0x00014000 0x1000>;
+			ranges = <0x82000000 0 0x28000000  0x28000000  0 0x08000000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";
+ 
+			#interrupt-cells = <1>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 		};
@@ -0,0 +1,272 @@
+From 14022b103616ec01417e6c707095d57d61162450 Mon Sep 17 00:00:00 2001
+From: Rosen Penev <rosenp@gmail.com>
+Date: Sun, 1 Mar 2026 16:01:04 -0800
+Subject: [PATCH] ARM: dts: BCM5301X: add root pcie bridges
+
+They are always required and instead of duplicating a definition in each
+dts file, place it in dtsi with labels and work based on that.
+
+Also changed each bridge@ to pcie@ to get extra dtc static analysis.
+
+Fixed bridge numbers as a result.
+
+Signed-off-by: Rosen Penev <rosenp@gmail.com>
+---
+ arch/arm/boot/dts/broadcom/bcm-ns.dtsi        | 30 ++++++++
+ .../dts/broadcom/bcm4709-netgear-r8000.dts    | 73 ++++++++-----------
+ .../dts/broadcom/bcm47094-luxul-xap-1610.dts  | 36 ++-------
+ .../broadcom/bcm47094-luxul-xwr-3150-v1.dts   | 36 ++-------
+ 4 files changed, 76 insertions(+), 99 deletions(-)
+
+--- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
+@@ -196,6 +196,16 @@
+ 			#interrupt-cells = <1>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+
+			pcie_bridge0: pcie@0 {
+				device_type = "pci";
+				reg = <0x0000 0 0 0 0>;
+				bus-range = <0x00 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+ 		};
+ 
+ 		pcie1: pcie@13000 {
+@@ -210,6 +220,16 @@
+ 			#interrupt-cells = <1>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+
+			pcie_bridge1: pcie@0 {
+				device_type = "pci";
+				reg = <0x0000 0 0 0 0>;
+				bus-range = <0x00 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+ 		};
+ 
+ 		pcie2: pcie@14000 {
+@@ -224,6 +244,16 @@
+ 			#interrupt-cells = <1>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+
+			pcie_bridge2: pcie@0 {
+				device_type = "pci";
+				reg = <0x0000 0 0 0 0>;
+				bus-range = <0x00 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+ 		};
+ 
+ 		usb2: usb2@21000 {
+--- a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts
+++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts
+@@ -126,66 +126,53 @@
+ 	};
+ };
+ 
+-&pcie0 {
+-	#address-cells = <3>;
+-	#size-cells = <2>;
+-
+-	bridge@0,0,0 {
+&pcie_bridge0 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+ 		reg = <0x0000 0 0 0 0>;
+-
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-
+-		wifi@0,1,0 {
+-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+-			reg = <0x0000 0 0 0 0>;
+-			ieee80211-freq-limit = <5735000 5835000>;
+-			brcm,ccode-map = "JP-JP-78", "US-Q2-86";
+-		};
+		ieee80211-freq-limit = <5735000 5835000>;
+		brcm,ccode-map = "JP-JP-78", "US-Q2-86";
+ 	};
+ };
+ 
+-&pcie1 {
+-	#address-cells = <3>;
+-	#size-cells = <2>;
+-
+-	bridge@1,0,0 {
+&pcie_bridge1 {
+	pcie@0,0 {
+		device_type = "pci";
+ 		reg = <0x0000 0 0 0 0>;
+		bus-range = <0x01 0xff>;
+ 
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+		ranges;
+ 
+-		bridge@1,1,0 {
+-			reg = <0x0000 0 0 0 0>;
+		pcie@1,0 {
+			device_type = "pci";
+			reg = <0x800 0 0 0 0>;
+ 
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+			ranges;
+ 
+-			bridge@1,0 {
+-				reg = <0x800 0 0 0 0>;
+-
+-				#address-cells = <3>;
+-				#size-cells = <2>;
+-
+-				wifi@0,0 {
+-					compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+-					reg = <0x0000 0 0 0 0>;
+-					brcm,ccode-map = "JP-JP-78", "US-Q2-86";
+-				};
+			wifi@0,0 {
+				compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+				reg = <0x0000 0 0 0 0>;
+				brcm,ccode-map = "JP-JP-78", "US-Q2-86";
+ 			};
+		};
+ 
+-			bridge@1,2,2 {
+-				reg = <0x1000 0 0 0 0>;
+		pcie@2,0 {
+			device_type = "pci";
+			reg = <0x1000 0 0 0 0>;
+ 
+-				#address-cells = <3>;
+-				#size-cells = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+ 
+-				wifi@1,4,0 {
+-					compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+-					reg = <0x0000 0 0 0 0>;
+-					ieee80211-freq-limit = <5170000 5730000>;
+-					brcm,ccode-map = "JP-JP-78", "US-Q2-86";
+-				};
+			wifi@0,0 {
+				compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+				reg = <0x0000 0 0 0 0>;
+				ieee80211-freq-limit = <5170000 5730000>;
+				brcm,ccode-map = "JP-JP-78", "US-Q2-86";
+ 			};
+ 		};
+ 	};
+--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts
+++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts
+@@ -65,39 +65,19 @@
+ };
+ 
+ 
+-&pcie0 {
+-	#address-cells = <3>;
+-	#size-cells = <2>;
+-
+-	bridge@0,0 {
+&pcie_bridge0 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+ 		reg = <0x0000 0 0 0 0>;
+-
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-
+-		wifi@0,0 {
+-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+-			reg = <0x0000 0 0 0 0>;
+-			brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825";
+-		};
+		brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825";
+ 	};
+ };
+ 
+-&pcie1 {
+-	#address-cells = <3>;
+-	#size-cells = <2>;
+-
+-	bridge@0,0 {
+&pcie_bridge1 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+ 		reg = <0x0000 0 0 0 0>;
+-
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-
+-		wifi@0,0 {
+-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+-			reg = <0x0000 0 0 0 0>;
+-			brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825";
+-		};
+		brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825";
+ 	};
+ };
+ 
+--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts
+++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts
+@@ -81,39 +81,19 @@
+ 	nvmem-cell-names = "mac-address";
+ };
+ 
+-&pcie0 {
+-	#address-cells = <3>;
+-	#size-cells = <2>;
+-
+-	bridge@0,0 {
+&pcie_bridge0 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+ 		reg = <0x0000 0 0 0 0>;
+-
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-
+-		wifi@0,0 {
+-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+-			reg = <0x0000 0 0 0 0>;
+-			brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
+-		};
+		brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
+ 	};
+ };
+ 
+-&pcie1 {
+-	#address-cells = <3>;
+-	#size-cells = <2>;
+-
+-	bridge@0,0 {
+&pcie_bridge1 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+ 		reg = <0x0000 0 0 0 0>;
+-
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+-
+-		wifi@0,0 {
+-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+-			reg = <0x0000 0 0 0 0>;
+-			brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
+-		};
+		brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
+ 	};
+ };
+ 
@@ -0,0 +1,32 @@
+From 0b3cd139be565b85f4a3579e376152b9def6256a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jonas=20K=C3=B6ppeler?= <j.koeppeler@tu-berlin.de>
+Date: Thu, 26 Feb 2026 12:40:15 +0100
+Subject: [PATCH] net/sched: sch_cake: avoid sync overhead when unlimited
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Skip inter-instance sync when no rate limit is configured, as it serves
+no purpose and only adds overhead.
+
+Fixes: 1bddd758bac2 ("net/sched: sch_cake: share shaper state across sub-instances of cake_mq")
+Signed-off-by: Jonas Köppeler <j.koeppeler@tu-berlin.de>
+Acked-by: Toke Høiland-Jørgensen <toke@toke.dk>
+Link: https://patch.msgid.link/20260226-cake-mq-skip-sync-bandwidth-unlimited-v1-1-01830bb4db87@tu-berlin.de
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ net/sched/sch_cake.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/net/sched/sch_cake.c
+++ b/net/sched/sch_cake.c
+@@ -2012,7 +2012,8 @@ static struct sk_buff *cake_dequeue(stru
+ 	u64 delay;
+ 	u32 len;
+ 
+-	if (q->config->is_shared && now - q->last_checked_active >= q->config->sync_time) {
+	if (q->config->is_shared && q->rate_ns &&
+	    now - q->last_checked_active >= q->config->sync_time) {
+ 		struct net_device *dev = qdisc_dev(sch);
+ 		struct cake_sched_data *other_priv;
+ 		u64 new_rate = q->config->rate_bps;
@@ -0,0 +1,187 @@
+From 15c2715a52645fd8e6e18b7abc3449292d118c7c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jonas=20K=C3=B6ppeler?= <j.koeppeler@tu-berlin.de>
+Date: Thu, 26 Feb 2026 12:40:16 +0100
+Subject: [PATCH] net/sched: sch_cake: fixup cake_mq rate adjustment for
+ diffserv config
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+cake_mq's rate adjustment during the sync periods did not adjust the
+rates for every tin in a diffserv config. This lead to inconsistencies
+of rates between the tins. Fix this by setting the rates for all tins
+during synchronization.
+
+Fixes: 1bddd758bac2 ("net/sched: sch_cake: share shaper state across sub-instances of cake_mq")
+Signed-off-by: Jonas Köppeler <j.koeppeler@tu-berlin.de>
+Acked-by: Toke Høiland-Jørgensen <toke@toke.dk>
+Link: https://patch.msgid.link/20260226-cake-mq-skip-sync-bandwidth-unlimited-v1-2-01830bb4db87@tu-berlin.de
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ net/sched/sch_cake.c | 50 ++++++++++++++++++++------------------------
+ 1 file changed, 23 insertions(+), 27 deletions(-)
+
+--- a/net/sched/sch_cake.c
+++ b/net/sched/sch_cake.c
+@@ -391,8 +391,8 @@ static const u32 inv_sqrt_cache[REC_INV_
+ 	1239850263, 1191209601, 1147878294, 1108955788
+ };
+ 
+-static void cake_set_rate(struct cake_tin_data *b, u64 rate, u32 mtu,
+-			  u64 target_ns, u64 rtt_est_ns);
+static void cake_configure_rates(struct Qdisc *sch, u64 rate, bool rate_adjust);
+
+ /* http://en.wikipedia.org/wiki/Methods_of_computing_square_roots
+  * new_invsqrt = (invsqrt / 2) * (3 - count * invsqrt^2)
+  *
+@@ -2039,12 +2039,9 @@ static struct sk_buff *cake_dequeue(stru
+ 		if (num_active_qs > 1)
+ 			new_rate = div64_u64(q->config->rate_bps, num_active_qs);
+ 
+-		/* mtu = 0 is used to only update the rate and not mess with cobalt params */
+-		cake_set_rate(b, new_rate, 0, 0, 0);
+		cake_configure_rates(sch, new_rate, true);
+ 		q->last_checked_active = now;
+ 		q->active_queues = num_active_qs;
+-		q->rate_ns = b->tin_rate_ns;
+-		q->rate_shft = b->tin_rate_shft;
+ 	}
+ 
+ begin:
+@@ -2361,12 +2358,10 @@ static void cake_set_rate(struct cake_ti
+ 	b->cparams.p_dec = 1 << 20; /* 1/4096 */
+ }
+ 
+-static int cake_config_besteffort(struct Qdisc *sch)
+static int cake_config_besteffort(struct Qdisc *sch, u64 rate, u32 mtu)
+ {
+ 	struct cake_sched_data *q = qdisc_priv(sch);
+ 	struct cake_tin_data *b = &q->tins[0];
+-	u32 mtu = psched_mtu(qdisc_dev(sch));
+-	u64 rate = q->config->rate_bps;
+ 
+ 	q->tin_cnt = 1;
+ 
+@@ -2380,12 +2375,10 @@ static int cake_config_besteffort(struct
+ 	return 0;
+ }
+ 
+-static int cake_config_precedence(struct Qdisc *sch)
+static int cake_config_precedence(struct Qdisc *sch, u64 rate, u32 mtu)
+ {
+ 	/* convert high-level (user visible) parameters into internal format */
+ 	struct cake_sched_data *q = qdisc_priv(sch);
+-	u32 mtu = psched_mtu(qdisc_dev(sch));
+-	u64 rate = q->config->rate_bps;
+ 	u32 quantum = 256;
+ 	u32 i;
+ 
+@@ -2456,7 +2449,7 @@ static int cake_config_precedence(struct
+  *	Total 12 traffic classes.
+  */
+ 
+-static int cake_config_diffserv8(struct Qdisc *sch)
+static int cake_config_diffserv8(struct Qdisc *sch, u64 rate, u32 mtu)
+ {
+ /*	Pruned list of traffic classes for typical applications:
+  *
+@@ -2473,8 +2466,6 @@ static int cake_config_diffserv8(struct
+  */
+ 
+ 	struct cake_sched_data *q = qdisc_priv(sch);
+-	u32 mtu = psched_mtu(qdisc_dev(sch));
+-	u64 rate = q->config->rate_bps;
+ 	u32 quantum = 256;
+ 	u32 i;
+ 
+@@ -2504,7 +2495,7 @@ static int cake_config_diffserv8(struct
+ 	return 0;
+ }
+ 
+-static int cake_config_diffserv4(struct Qdisc *sch)
+static int cake_config_diffserv4(struct Qdisc *sch, u64 rate, u32 mtu)
+ {
+ /*  Further pruned list of traffic classes for four-class system:
+  *
+@@ -2517,8 +2508,6 @@ static int cake_config_diffserv4(struct
+  */
+ 
+ 	struct cake_sched_data *q = qdisc_priv(sch);
+-	u32 mtu = psched_mtu(qdisc_dev(sch));
+-	u64 rate = q->config->rate_bps;
+ 	u32 quantum = 1024;
+ 
+ 	q->tin_cnt = 4;
+@@ -2546,7 +2535,7 @@ static int cake_config_diffserv4(struct
+ 	return 0;
+ }
+ 
+-static int cake_config_diffserv3(struct Qdisc *sch)
+static int cake_config_diffserv3(struct Qdisc *sch, u64 rate, u32 mtu)
+ {
+ /*  Simplified Diffserv structure with 3 tins.
+  *		Latency Sensitive	(CS7, CS6, EF, VA, TOS4)
+@@ -2554,8 +2543,6 @@ static int cake_config_diffserv3(struct
+  *		Low Priority		(LE, CS1)
+  */
+ 	struct cake_sched_data *q = qdisc_priv(sch);
+-	u32 mtu = psched_mtu(qdisc_dev(sch));
+-	u64 rate = q->config->rate_bps;
+ 	u32 quantum = 1024;
+ 
+ 	q->tin_cnt = 3;
+@@ -2580,32 +2567,33 @@ static int cake_config_diffserv3(struct
+ 	return 0;
+ }
+ 
+-static void cake_reconfigure(struct Qdisc *sch)
+static void cake_configure_rates(struct Qdisc *sch, u64 rate, bool rate_adjust)
+ {
+	u32 mtu = likely(rate_adjust) ? 0 : psched_mtu(qdisc_dev(sch));
+ 	struct cake_sched_data *qd = qdisc_priv(sch);
+ 	struct cake_sched_config *q = qd->config;
+ 	int c, ft;
+ 
+ 	switch (q->tin_mode) {
+ 	case CAKE_DIFFSERV_BESTEFFORT:
+-		ft = cake_config_besteffort(sch);
+		ft = cake_config_besteffort(sch, rate, mtu);
+ 		break;
+ 
+ 	case CAKE_DIFFSERV_PRECEDENCE:
+-		ft = cake_config_precedence(sch);
+		ft = cake_config_precedence(sch, rate, mtu);
+ 		break;
+ 
+ 	case CAKE_DIFFSERV_DIFFSERV8:
+-		ft = cake_config_diffserv8(sch);
+		ft = cake_config_diffserv8(sch, rate, mtu);
+ 		break;
+ 
+ 	case CAKE_DIFFSERV_DIFFSERV4:
+-		ft = cake_config_diffserv4(sch);
+		ft = cake_config_diffserv4(sch, rate, mtu);
+ 		break;
+ 
+ 	case CAKE_DIFFSERV_DIFFSERV3:
+ 	default:
+-		ft = cake_config_diffserv3(sch);
+		ft = cake_config_diffserv3(sch, rate, mtu);
+ 		break;
+ 	}
+ 
+@@ -2616,6 +2604,14 @@ static void cake_reconfigure(struct Qdis
+ 
+ 	qd->rate_ns   = qd->tins[ft].tin_rate_ns;
+ 	qd->rate_shft = qd->tins[ft].tin_rate_shft;
+}
+
+static void cake_reconfigure(struct Qdisc *sch)
+{
+	struct cake_sched_data *qd = qdisc_priv(sch);
+	struct cake_sched_config *q = qd->config;
+
+	cake_configure_rates(sch, qd->config->rate_bps, false);
+ 
+ 	if (q->buffer_config_limit) {
+ 		qd->buffer_limit = q->buffer_config_limit;
@@ -479,6 +479,7 @@ static int bcma_fbs_probe(struct platform_device *pdev)
 	struct bcma_fbs *priv;
 	unsigned long flags;
 	u8 mac[ETH_ALEN];
+	int ret;

 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
@@ -491,7 +492,10 @@ static int bcma_fbs_probe(struct platform_device *pdev)
 	of_property_read_u32(node, "pci-bus", &priv->pci_bus);
 	of_property_read_u32(node, "pci-dev", &priv->pci_dev);

-	of_get_mac_address(node, mac);
+	ret = of_get_mac_address(node, mac);
+	if (ret == -EPROBE_DEFER)
+		return ret;
+
 	if (is_valid_ether_addr(mac)) {
 		dev_info(dev, "mtd mac %pM\n", mac);
 	} else {
@@ -690,6 +690,7 @@ static int ssb_fbs_probe(struct platform_device *pdev)
 	struct ssb_fbs *priv;
 	unsigned long flags;
 	u8 mac[ETH_ALEN];
+	int ret;

 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
@@ -702,7 +703,10 @@ static int ssb_fbs_probe(struct platform_device *pdev)
 	of_property_read_u32(node, "pci-bus", &priv->pci_bus);
 	of_property_read_u32(node, "pci-dev", &priv->pci_dev);

-	of_get_mac_address(node, mac);
+	ret = of_get_mac_address(node, mac);
+	if (ret == -EPROBE_DEFER)
+		return ret;
+
 	if (is_valid_ether_addr(mac)) {
 		dev_info(dev, "mtd mac %pM\n", mac);
 	} else {
@@ -93,11 +93,6 @@ ipq806x_setup_macs()
 		hw_mac_addr=$(mtd_get_mac_ascii hwconfig HW.WAN.MAC.Address)
 		ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 1)"
 		;;
-	linksys,e8350-v1)
-		hw_mac_addr=$(mtd_get_mac_ascii 0:appsblenv ethaddr)
-		ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)"
-		ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 3)"
-		;;
 	ruijie,rg-mtfi-m520)
 		hw_mac_addr=$(mtd_get_mac_ascii PRODUCTINFO ethaddr)
 		ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
@@ -32,10 +32,6 @@ case "$FIRMWARE" in
 	tplink,onhub)
 		base64_extract /sys/firmware/vpd/ro/wifi_base64_calibration0
 		;;
-	meraki,mr52)
-		CI_UBIPART=art
-		caldata_extract_ubi "ART" 0x1000 0x844
-		;;
 	ruijie,rg-mtfi-m520)
 		caldata_extract "ART" 0x1000 0x844
 		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii PRODUCTINFO ethaddr) 2)
@@ -44,13 +40,6 @@ case "$FIRMWARE" in
 	;;
 "ath10k/pre-cal-pci-0000:01:00.0.bin")
 	case $board in
-	asrock,g10)
-		caldata_extract "0:art" 0x1000 0x2f20
-		;;
-	meraki,mr42)
-		CI_UBIPART=art
-		caldata_extract_ubi "ART" 0x1000 0x2f20
-		;;
 	xiaomi,mi-router-hd)
 		caldata_extract "ART" 0x1000 0x2f20
 		;;
@@ -70,17 +59,6 @@ case "$FIRMWARE" in
 	;;
 "ath10k/pre-cal-pci-0001:01:00.0.bin")
 	case $board in
-	asrock,g10)
-		caldata_extract "0:art" 0x5000 0x2f20
-		;;
-	edgecore,ecw5410)
-		caldata_extract "0:art" 0x1000 0x2f20
-		;;
-	meraki,mr42|\
-	meraki,mr52)
-		CI_UBIPART=art
-		caldata_extract_ubi "ART" 0x5000 0x2f20
-		;;
 	xiaomi,mi-router-hd)
 		caldata_extract "ART" 0x5000 0x2f20
 		;;
@@ -92,21 +70,6 @@ case "$FIRMWARE" in
 	tplink,onhub)
 		base64_extract /sys/firmware/vpd/ro/wifi_base64_calibration2
 		;;
-	meraki,mr42)
-		CI_UBIPART=art
-		caldata_extract_ubi "ART" 0x9000 0x844
-		;;
-	esac
-	;;
-"ath10k/pre-cal-pci-0002:01:00.0.bin")
-	case $board in
-	edgecore,ecw5410)
-		caldata_extract "0:art" 0x5000 0x2f20
-		;;
-	meraki,mr52)
-		CI_UBIPART=art
-		caldata_extract_ubi "ART" 0x9000 0x2f20
-		;;
 	esac
 	;;
 *)
@@ -210,6 +210,14 @@
 					label = "0:appsblenv";
 					reg = <0x0130000 0x0040000>;
 					read-only;
+
+					nvmem-layout {
+						compatible = "u-boot,env";
+
+						macaddr_uboot_ethaddr: ethaddr {
+							#nvmem-cell-cells = <1>;
+						};
+					};
 				};

 				art: partition@170000 {
@@ -399,6 +407,9 @@
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";

+	nvmem-cells = <&macaddr_uboot_ethaddr 3>;
+	nvmem-cell-names = "mac-address";
+
 	fixed-link {
 		speed = <1000>;
 		full-duplex;
@@ -411,6 +422,9 @@
 	phy-mode = "sgmii";
 	qcom,id = <2>;

+	nvmem-cells = <&macaddr_uboot_ethaddr 2>;
+	nvmem-cell-names = "mac-address";
+
 	fixed-link {
 		speed = <1000>;
 		full-duplex;
@@ -279,6 +279,25 @@

 		partitions {
 			compatible = "qcom,smem-part";
+
+			partition-0-art {
+				label = "0:art";
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_1000: pre-calibration@1000 {
+						reg = <0x1000 0x2f20>;
+					};
+
+					precal_art_5000: pre-calibration@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
+			};
 		};
 	};
 };
@@ -292,6 +311,8 @@
 		compatible = "qcom,ath10k";
 		reg = <0x00010000 0 0 0 0>;
 		qcom,ath10k-calibration-variant = "ASRock-G10";
+		nvmem-cells = <&precal_art_1000>;
+		nvmem-cell-names = "pre-calibration";
 	};
 };

@@ -304,6 +325,8 @@
 		compatible = "qcom,ath10k";
 		reg = <0x00010000 0 0 0 0>;
 		qcom,ath10k-calibration-variant = "ASRock-G10";
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
 	};
 };

@@ -212,12 +212,15 @@
 				#size-cells = <1>;

 				cfg1@2a0000 {
-					compatible = "u-boot,env-redundant-bool";
 					label = "CFG1";
 					reg = <0x2a0000 0x0010000>;

-					ethaddr: ethaddr {
-						#nvmem-cell-cells = <1>;
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool";
+
+						ethaddr: ethaddr {
+							#nvmem-cell-cells = <1>;
+						};
 					};
 				};

@@ -194,6 +194,22 @@
 			partition@36c0000 {
 				label = "ubi";
 				reg = <0x36c0000 0x46c0000>;
+
+				volumes {
+					ubi-volume-art {
+						volname = "ART";
+
+						art_nvmem: nvmem-layout {
+							compatible = "fixed-layout";
+							#address-cells = <1>;
+							#size-cells = <1>;
+
+							precal_art_5000: pre-calibration@5000 {
+								reg = <0x5000 0x2f20>;
+							};
+						};
+					};
+				};
 			};

 			partition@7d80000 {
@@ -192,6 +192,25 @@

 			partitions {
 				compatible = "qcom,smem-part";
+
+				partition-0-art {
+					label = "0:art";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						precal_art_1000: pre-calibration@1000 {
+							reg = <0x1000 0x2f20>;
+						};
+
+						precal_art_5000: pre-calibration@5000 {
+							reg = <0x5000 0x2f20>;
+						};
+					};
+				};
 			};
 		};
 	};
@@ -234,6 +253,8 @@
 		compatible = "qcom,ath10k";
 		reg = <0x00010000 0 0 0 0>;
 		qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
+		nvmem-cells = <&precal_art_1000>;
+		nvmem-cell-names = "pre-calibration";
 	};
 };

@@ -250,6 +271,8 @@
 		compatible = "qcom,ath10k";
 		reg = <0x00010000 0 0 0 0>;
 		qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
+		nvmem-cells = <&precal_art_5000>;
+		nvmem-cell-names = "pre-calibration";
 	};
 };

@@ -193,19 +193,29 @@
 	};
 };

+&art_nvmem {
+	precal_art_1000: pre-calibration@1000 {
+		reg = <0x1000 0x2f20>;
+	};
+
+	cal_art_9000: calibration@9000 {
+		reg = <0x9000 0x844>;
+	};
+};
+
 &wifi0 {
-	nvmem-cells = <&mac_address 1>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&precal_art_1000>, <&mac_address 1>;
+	nvmem-cell-names = "pre-calibration", "mac-address";
 };

 &wifi1 {
-	nvmem-cells = <&mac_address 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&precal_art_5000>, <&mac_address 2>;
+	nvmem-cell-names = "pre-calibration", "mac-address";
 };

 &wifi2 {
-	nvmem-cells = <&mac_address 3>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&cal_art_9000>, <&mac_address 3>;
+	nvmem-cell-names = "calibration", "mac-address";
 };

 &hs_phy_0 {
@@ -218,19 +218,29 @@
 	};
 };

+&art_nvmem {
+	cal_art_1000: calibration@1000 {
+		reg = <0x1000 0x844>;
+	};
+
+	precal_art_9000: pre-calibration@9000 {
+		reg = <0x9000 0x2f20>;
+	};
+};
+
 &wifi0 {
-	nvmem-cells = <&mac_address 4>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&cal_art_1000>, <&mac_address 4>;
+	nvmem-cell-names = "calibration", "mac-address";
 };

 &wifi1 {
-	nvmem-cells = <&mac_address 3>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&precal_art_5000>, <&mac_address 3>;
+	nvmem-cell-names = "pre-calibration", "mac-address";
 };

 &wifi2 {
-	nvmem-cells = <&mac_address 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&precal_art_9000>, <&mac_address 2>;
+	nvmem-cell-names = "pre-calibration", "mac-address";
 };

 &hs_phy_0 {
@@ -28,6 +28,7 @@

 #define RTL838X_INT_RW_CTRL		(0x0058)
 #define RTL838X_EXT_VERSION		(0x00D0)
+#define RTL838X_PLL_CML_CTRL		(0x0ff8)

 #define RTL931X_LED_GLB_CTRL		(0x0600)
 #define RTL931X_MAC_L2_GLOBAL_CTRL2	(0x1358)
@@ -101,9 +101,21 @@ static int rtlsmp_register(void)

 static void __init apply_early_quirks(void)
 {
-	/* Open up write protected registers. Never mess with this elsewhere */
-	if (soc_info.family == RTL8380_FAMILY_ID)
+	if (soc_info.family == RTL8380_FAMILY_ID) {
+		/*
+		 * Open up write protected registers. SDK opens/closes this whenever needed. For
+		 * simplicity always work with an "open" register set.
+		 */
 		sw_w32(0x3, RTL838X_INT_RW_CTRL);
+		/*
+		 * Disable 4 byte address mode of flash controller. If this bit is not cleared
+		 * the watchdog cannot reset the SoC. The SDK changes this short before restart.
+		 * Until this quirk was implemented all RTL838x devices ran with this disabled
+		 * because of a coding error. As no issues were detected keep the behaviour
+		 * until more details are known.
+		 */
+		sw_w32_mask(BIT(30), 0, RTL838X_PLL_CML_CTRL);
+	}
 }

 static void __init apply_dts_quirks(void)
@@ -1540,19 +1540,13 @@ static int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, v
 */
 static int rtldsa_ethernet_loaded(struct platform_device *pdev)
 {
-	struct device_node *dn = pdev->dev.of_node;
-	struct device_node *ports, *port;
+	struct platform_device *eth_pdev;
+	struct device_node *port_np;
+	struct device_node *eth_np;
 	int ret = -EPROBE_DEFER;

-	ports = of_get_child_by_name(dn, "ethernet-ports");
-	if (!ports)
-		return -ENODEV;
-
-	for_each_child_of_node(ports, port) {
-		struct device_node *eth_np;
-		struct platform_device *eth_pdev;
-
-		eth_np = of_parse_phandle(port, "ethernet", 0);
+	for_each_node_with_property(port_np, "ethernet") {
+		eth_np = of_parse_phandle(port_np, "ethernet", 0);
 		if (!eth_np)
 			continue;

@@ -1564,9 +1558,9 @@ static int rtldsa_ethernet_loaded(struct platform_device *pdev)

 		if (eth_pdev->dev.driver)
 			ret = 0;
-	}

-	of_node_put(ports);
+		put_device(&eth_pdev->dev);
+	}

 	return ret;
 }
@@ -24,12 +24,12 @@
 #include <asm/mach-rtl-otto/mach-rtl-otto.h>
 #include "rtl838x_eth.h"

-#define RTETH_OWN_CPU		1
-#define RTETH_RX_RING_SIZE	128
-#define RTETH_RX_RINGS		2
-#define RTETH_TX_RING_SIZE	16
-#define RTETH_TX_RINGS		2
-#define RTETH_TX_TRIGGER	0x16
+#define RTETH_OWN_CPU			1
+#define RTETH_RX_RING_SIZE		128
+#define RTETH_RX_RINGS			2
+#define RTETH_TX_RING_SIZE		16
+#define RTETH_TX_RINGS			2
+#define RTETH_TX_TRIGGER(ctrl, ring)	((0x16 >> ring) & ctrl->r->tx_trigger_mask)

 #define NOTIFY_EVENTS	10
 #define NOTIFY_BLOCKS	10
@@ -121,47 +121,18 @@ static void rteth_839x_create_tx_header(struct rteth_packet *h, unsigned int des
 		h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8;
 }

-static void rteth_930x_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio)
+static void rteth_93xx_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio)
 {
 	h->cpu_tag[0] = 0x8000;  /* CPU tag marker */
+	h->cpu_tag[1] = FIELD_PREP(RTL93XX_CPU_TAG1_FWD_MASK, RTL93XX_CPU_TAG1_FWD_PHYSICAL) |
+		        FIELD_PREP(RTL93XX_CPU_TAG1_IGNORE_STP_MASK, 1);

-	h->cpu_tag[1] = FIELD_PREP(RTL93XX_CPU_TAG1_FWD_MASK,
-				   RTL93XX_CPU_TAG1_FWD_PHYSICAL);
-	h->cpu_tag[1] |= FIELD_PREP(RTL93XX_CPU_TAG1_IGNORE_STP_MASK, 1);
-	h->cpu_tag[2] = 0;
+	h->cpu_tag[2] = (prio >= 0) ? (BIT(5) | (prio & 0x1f)) << 8 : 0;
 	h->cpu_tag[3] = 0;
-	h->cpu_tag[4] = 0;
-	h->cpu_tag[5] = 0;
-	h->cpu_tag[6] = BIT(dest_port) >> 16;
-	h->cpu_tag[7] = BIT(dest_port) & 0xffff;
-
-	/* Enable (AS_QID) and set priority queue (QID) */
-	if (prio >= 0)
-		h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
-}
-
-static void rteth_931x_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio)
-{
-	h->cpu_tag[0] = 0x8000;  /* CPU tag marker */
-
-	h->cpu_tag[1] = FIELD_PREP(RTL93XX_CPU_TAG1_FWD_MASK,
-				   RTL93XX_CPU_TAG1_FWD_PHYSICAL);
-	h->cpu_tag[1] |= FIELD_PREP(RTL93XX_CPU_TAG1_IGNORE_STP_MASK, 1);
-	h->cpu_tag[2] = 0;
-	h->cpu_tag[3] = 0;
-	h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
-	if (dest_port >= 32) {
-		dest_port -= 32;
-		h->cpu_tag[4] = BIT(dest_port) >> 16;
-		h->cpu_tag[5] = BIT(dest_port) & 0xffff;
-	} else {
-		h->cpu_tag[6] = BIT(dest_port) >> 16;
-		h->cpu_tag[7] = BIT(dest_port) & 0xffff;
-	}
-
-	/* Enable (AS_QID) and set priority queue (QID) */
-	if (prio >= 0)
-		h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
+	h->cpu_tag[4] = BIT_ULL(dest_port) >> 48;
+	h->cpu_tag[5] = BIT_ULL(dest_port) >> 32;
+	h->cpu_tag[6] = BIT_ULL(dest_port) >> 16;
+	h->cpu_tag[7] = BIT_ULL(dest_port) & 0xffff;
 }

 struct rtl838x_rx_q {
@@ -925,7 +896,7 @@ static void rteth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
 static int rteth_start_xmit(struct sk_buff *skb, struct net_device *netdev)
 {
 	struct rteth_ctrl *ctrl = netdev_priv(netdev);
-	int slot, len = skb->len, dest_port = -1;
+	int val, slot, len = skb->len, dest_port = -1;
 	int ring = skb_get_queue_mapping(skb);
 	struct device *dev = &ctrl->pdev->dev;
 	struct rteth_packet *packet;
@@ -990,18 +961,16 @@ static int rteth_start_xmit(struct sk_buff *skb, struct net_device *netdev)

 	spin_lock(&ctrl->tx_lock);

-	/* Before starting TX, prevent a Lexra bus bug on RTL8380 SoCs */
-	if (ctrl->r->family_id == RTL8380_FAMILY_ID) {
-		for (int i = 0; i < 10; i++) {
-			u32 val = sw_r32(ctrl->r->dma_if_ctrl);
-			if ((val & ctrl->r->tx_rx_enable) == ctrl->r->tx_rx_enable)
-				break;
-		}
-	}
+	/*
+	 * Issue send for 1 or 2 triggers. On some SoCs (especially RTL838x) there is a known
+	 * bug, where the hardware sometimes reads empty values from the register. Work around
+	 * that with a poll that checks if TX/RX is enabled in the register.
+	 */
+	if (read_poll_timeout(sw_r32, val, val & ctrl->r->tx_rx_enable,
+			     0, 5000, false, ctrl->r->dma_if_ctrl))
+		dev_warn_once(dev, "DMA interface ctrl register read failed\n");

-	/* issue SoC independent send for 1 or 2 triggers with some bit vodoo */
-	sw_w32_mask(0, (RTETH_TX_TRIGGER >> ring) & ctrl->r->tx_trigger_mask,
-		    ctrl->r->dma_if_ctrl);
+	sw_w32(val | RTETH_TX_TRIGGER(ctrl, ring), ctrl->r->dma_if_ctrl);

 	netdev->stats.tx_packets++;
 	netdev->stats.tx_bytes += len;
@@ -1204,24 +1173,20 @@ static void rteth_mac_link_up(struct phylink_config *config,

 static void rteth_set_mac_hw(struct net_device *dev, u8 *mac)
 {
-	struct rteth_ctrl *ctrl = netdev_priv(dev);
+	u32 mac_lo = (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
+	u32 mac_hi = (mac[0] << 8) | mac[1];
+	struct rteth_ctrl *ctrl;
 	unsigned long flags;

+	ctrl = netdev_priv(dev);
 	spin_lock_irqsave(&ctrl->lock, flags);
-	pr_debug("In %s\n", __func__);
-	sw_w32((mac[0] << 8) | mac[1], ctrl->r->mac);
-	sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], ctrl->r->mac + 4);

-	if (ctrl->r->family_id == RTL8380_FAMILY_ID) {
-		/* 2 more registers, ALE/MAC block */
-		sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
-		sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
-		       (RTL838X_MAC_ALE + 4));
+	for (int i = 0; i < RTETH_MAX_MAC_REGS; i++)
+		if (ctrl->r->mac_reg[i]) {
+			sw_w32(mac_hi, ctrl->r->mac_reg[i]);
+			sw_w32(mac_lo, ctrl->r->mac_reg[i] + 4);
+		}

-		sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
-		sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
-		       RTL838X_MAC2 + 4);
-	}
 	spin_unlock_irqrestore(&ctrl->lock, flags);
 }

@@ -1416,7 +1381,9 @@ static const struct rteth_config rteth_838x_cfg = {
 	.get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
 	.get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
 	.get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
-	.mac = RTL838X_MAC,
+	.mac_reg = { RTETH_838X_MAC_ADDR_CTRL,
+		     RTETH_838X_MAC_ADDR_CTRL_ALE,
+		     RTETH_838X_MAC_ADDR_CTRL_MAC },
 	.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
 	.update_counter = rteth_83xx_update_counter,
 	.create_tx_header = rteth_838x_create_tx_header,
@@ -1463,7 +1430,7 @@ static const struct rteth_config rteth_839x_cfg = {
 	.get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
 	.get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
 	.get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
-	.mac = RTL839X_MAC,
+	.mac_reg = { RTETH_839X_MAC_ADDR_CTRL },
 	.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
 	.update_counter = rteth_83xx_update_counter,
 	.create_tx_header = rteth_839x_create_tx_header,
@@ -1511,10 +1478,10 @@ static const struct rteth_config rteth_930x_cfg = {
 	.get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
 	.get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
 	.get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
-	.mac = RTL930X_MAC_L2_ADDR_CTRL,
+	.mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
 	.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
 	.update_counter = rteth_93xx_update_counter,
-	.create_tx_header = rteth_930x_create_tx_header,
+	.create_tx_header = rteth_93xx_create_tx_header,
 	.decode_tag = rteth_930x_decode_tag,
 	.hw_reset = &rteth_93xx_hw_reset,
 	.init_mac = &rteth_930x_init_mac,
@@ -1559,10 +1526,10 @@ static const struct rteth_config rteth_931x_cfg = {
 	.get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
 	.get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
 	.get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
-	.mac = RTL931X_MAC_L2_ADDR_CTRL,
+	.mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
 	.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
 	.update_counter = rteth_93xx_update_counter,
-	.create_tx_header = rteth_931x_create_tx_header,
+	.create_tx_header = rteth_93xx_create_tx_header,
 	.decode_tag = rteth_931x_decode_tag,
 	.hw_reset = &rteth_93xx_hw_reset,
 	.init_mac = &rteth_931x_init_mac,
@@ -1668,12 +1635,12 @@ static int rtl838x_eth_probe(struct platform_device *pdev)
 	if (is_valid_ether_addr(mac_addr)) {
 		rteth_set_mac_hw(dev, mac_addr);
 	} else {
-		mac_addr[0] = (sw_r32(ctrl->r->mac) >> 8) & 0xff;
-		mac_addr[1] = sw_r32(ctrl->r->mac) & 0xff;
-		mac_addr[2] = (sw_r32(ctrl->r->mac + 4) >> 24) & 0xff;
-		mac_addr[3] = (sw_r32(ctrl->r->mac + 4) >> 16) & 0xff;
-		mac_addr[4] = (sw_r32(ctrl->r->mac + 4) >> 8) & 0xff;
-		mac_addr[5] = sw_r32(ctrl->r->mac + 4) & 0xff;
+		mac_addr[0] = (sw_r32(ctrl->r->mac_reg[0]) >> 8) & 0xff;
+		mac_addr[1] = sw_r32(ctrl->r->mac_reg[0]) & 0xff;
+		mac_addr[2] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 24) & 0xff;
+		mac_addr[3] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 16) & 0xff;
+		mac_addr[4] = (sw_r32(ctrl->r->mac_reg[0] + 4) >> 8) & 0xff;
+		mac_addr[5] = sw_r32(ctrl->r->mac_reg[0] + 4) & 0xff;
 	}
 	dev_addr_set(dev, mac_addr);
 	/* if the address is invalid, use a random value */
@@ -3,11 +3,16 @@
 #ifndef _RTL838X_ETH_H
 #define _RTL838X_ETH_H

+#define RTETH_MAX_MAC_REGS			3
+
 /* Register definition */

 #define RTETH_838X_CPU_PORT			28
 #define RTETH_838X_DMA_IF_INTR_MSK		(0x9f50)
 #define RTETH_838X_DMA_IF_INTR_STS		(0x9f54)
+#define RTETH_838X_MAC_ADDR_CTRL		(0xa9ec)
+#define RTETH_838X_MAC_ADDR_CTRL_ALE		(0x6b04)
+#define RTETH_838X_MAC_ADDR_CTRL_MAC		(0xa320)
 #define RTETH_838X_MAC_FORCE_MODE_CTRL		(0xa104 + RTETH_838X_CPU_PORT * 4)
 #define RTETH_838X_MAC_L2_PORT_CTRL		(0xd560 + RTETH_838X_CPU_PORT * 128)
 #define RTETH_838X_QM_PKT2CPU_INTPRI_MAP	(0x5f10)
@@ -17,6 +22,7 @@
 #define RTETH_839X_CPU_PORT			52
 #define RTETH_839X_DMA_IF_INTR_MSK		(0x7864)
 #define RTETH_839X_DMA_IF_INTR_STS		(0x7868)
+#define RTETH_839X_MAC_ADDR_CTRL		(0x02b4)
 #define RTETH_839X_MAC_FORCE_MODE_CTRL		(0x02bc + RTETH_839X_CPU_PORT * 4)
 #define RTETH_839X_MAC_L2_PORT_CTRL		(0x8004 + RTETH_839X_CPU_PORT * 128)
 #define RTETH_839X_QM_PKT2CPU_INTPRI_MAP	(0x1154)
@@ -27,6 +33,7 @@
 #define RTETH_930X_DMA_IF_INTR_MSK		(0xe010)
 #define RTETH_930X_DMA_IF_INTR_STS		(0xe01c)
 #define RTETH_930X_MAC_FORCE_MODE_CTRL		(0xca1c + RTETH_930X_CPU_PORT * 4)
+#define RTETH_930X_MAC_L2_ADDR_CTRL		(0xc714)
 #define RTETH_930X_MAC_L2_PORT_CTRL		(0x3268 + RTETH_930X_CPU_PORT * 64)
 #define RTETH_930X_QM_RSN2CPUQID_CTRL_0		(0xa344)
 #define RTETH_930X_QM_RSN2CPUQID_CTRL_CNT	11
@@ -35,6 +42,7 @@
 #define RTETH_931X_DMA_IF_INTR_MSK		(0x0910)
 #define RTETH_931X_DMA_IF_INTR_STS		(0x091c)
 #define RTETH_931X_MAC_FORCE_MODE_CTRL		(0x0dcc + RTETH_931X_CPU_PORT * 4)
+#define RTETH_931X_MAC_L2_ADDR_CTRL		(0x135c)
 #define RTETH_931X_MAC_L2_PORT_CTRL		(0x6000 + RTETH_931X_CPU_PORT * 128)
 #define RTETH_931X_QM_RSN2CPUQID_CTRL_0		(0xa9f4)
 #define RTETH_931X_QM_RSN2CPUQID_CTRL_CNT	14
@@ -74,14 +82,6 @@

 #define RTL839X_DMA_IF_INTR_NOTIFY_MASK		GENMASK(22, 20)

-/* MAC address settings */
-#define RTL838X_MAC				(0xa9ec)
-#define RTL839X_MAC				(0x02b4)
-#define RTL838X_MAC_ALE				(0x6b04)
-#define RTL838X_MAC2				(0xa320)
-#define RTL930X_MAC_L2_ADDR_CTRL		(0xC714)
-#define RTL931X_MAC_L2_ADDR_CTRL		(0x135c)
-
 /* Ringbuffer setup */
 #define RTL838X_DMA_RX_BASE			(0x9f00)
 #define RTL839X_DMA_RX_BASE			(0x780c)
@@ -419,7 +419,7 @@ struct rteth_config {
 	u32 (*get_mac_link_spd_sts)(int port);
 	u32 (*get_mac_rx_pause_sts)(int port);
 	u32 (*get_mac_tx_pause_sts)(int port);
-	int mac;
+	u32 mac_reg[RTETH_MAX_MAC_REGS];
 	int l2_tbl_flush_ctrl;
 	void (*create_tx_header)(struct rteth_packet *h, unsigned int dest_port, int prio);
 	bool (*decode_tag)(struct rteth_packet *h, struct dsa_tag *tag);
@@ -18,7 +18,7 @@ SDK_BUILD_DIR:=$(BUILD_DIR)/$(SDK_NAME)

 STAGING_SUBDIR_HOST := staging_dir/host
 STAGING_SUBDIR_TARGET := staging_dir/$(TARGET_DIR_NAME)
-STAGING_SUBDIR_TOOLCHAIN := staging_dir/toolchain-$(ARCH)$(ARCH_SUFFIX)_gcc-$(GCCV)_$(LIBC)$(if $(CONFIG_arm),_eabi)
+STAGING_SUBDIR_TOOLCHAIN := staging_dir/$(TOOLCHAIN_DIR_NAME)

 BUNDLER_PATH := $(subst $(space),:,$(filter-out $(TOPDIR)/%,$(subst :,$(space),$(PATH))))
 BUNDLER_COMMAND := PATH=$(BUNDLER_PATH) $(XARGS) $(SCRIPT_DIR)/bundle-libraries.sh $(SDK_BUILD_DIR)/$(STAGING_SUBDIR_HOST)