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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2026-04-10 10:19:41 +08:00
parent 254508aaad 8101611355
commit 584f938f24
65 changed files with 968 additions and 593 deletions
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include/package.mk
+9
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@@ -61,6 +61,15 @@ ifdef CONFIG_USE_MOLD
endif
endif
# loongarch64 sets CONFIG_PAGE_SIZE_16KB, all other targets set CONFIG_PAGE_SIZE_4KB only.
ifeq ($(ARCH),loongarch64)
TARGET_CFLAGS += -Wl,-z,max-page-size=16384
TARGET_LDFLAGS += -zmax-page-size=16384
else
TARGET_CFLAGS += -Wl,-z,max-page-size=4096
TARGET_LDFLAGS += -zmax-page-size=4096
endif
include $(INCLUDE_DIR)/hardening.mk
include $(INCLUDE_DIR)/prereq.mk
include $(INCLUDE_DIR)/unpack.mk
package/boot/arm-trusted-firmware-mediatek/Makefile
+6 -8
View File
@@ -13,9 +13,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git
PKG_SOURCE_DATE:=2025-07-11
PKG_SOURCE_VERSION:=78a0dfd927bb00ce973a1f8eb4079df0f755887a
PKG_MIRROR_HASH:=72a5f3f00f9e368226bb779dc098aac6195a312b48cc22172987d494ccd135d1
PKG_SOURCE_DATE:=2026-01-23
PKG_SOURCE_VERSION:=e06f258664198a901ff1c7c0c87802a115179451
PKG_MIRROR_HASH:=e094f5c2838f366e9b2d87e85e0c324ac3b955dd02a493adced843031cf6b517
PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
@@ -36,10 +36,10 @@ define Trusted-Firmware-A/Default
BOARD_QFN:=
DRAM_USE_COMB:=
RAM_BOOT_UART_DL:=
USE_SPI2:=
USE_UBI:=
FIP_OFFSET:=
FIP_SIZE:=
SPIM_CTRL:=
endef
define Trusted-Firmware-A/mt7622-nor-1ddr
@@ -464,7 +464,6 @@ define Trusted-Firmware-A/mt7987-spim-nand0
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
SPIM_CTRL:=0
endef
define Trusted-Firmware-A/mt7987-spim-nand0-ubi-comb
@@ -473,7 +472,6 @@ define Trusted-Firmware-A/mt7987-spim-nand0-ubi-comb
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
USE_UBI:=1
SPIM_CTRL:=0
endef
define Trusted-Firmware-A/mt7987-spim-nand2-ubi-comb
@@ -481,8 +479,8 @@ define Trusted-Firmware-A/mt7987-spim-nand2-ubi-comb
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
USE_SPI2:=1
USE_UBI:=1
SPIM_CTRL:=2
endef
define Trusted-Firmware-A/mt7987-ram-comb
@@ -799,7 +797,7 @@ TFA_MAKE_FLAGS += \
$(if $(USE_UBI),UBI=1 $(if $(findstring mt7986,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x200000)) \
$(if $(FIP_OFFSET),OVERRIDE_FIP_BASE=$(FIP_OFFSET)) \
$(if $(FIP_SIZE),OVERRIDE_FIP_SIZE=$(FIP_SIZE)) \
$(if $(SPIM_CTRL),SPIM_CTRL=$(SPIM_CTRL)) \
$(if $(USE_SPI2),SPIM_NAND_PREFER_SPI2=1) \
$(if $(RAM_BOOT_UART_DL),bl2,all)
define Package/trusted-firmware-a-ram/install
package/boot/arm-trusted-firmware-mediatek/patches/0005-mt7987-make-SPI-controller-configurable.patch
+7 -91
View File
@@ -16,67 +16,25 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
5 files changed, 53 insertions(+), 3 deletions(-)
create mode 100644 plat/mediatek/mt7987/Config.in
--- a/plat/mediatek/apsoc_common/Config.in
+++ b/plat/mediatek/apsoc_common/Config.in
@@ -783,6 +783,7 @@ config ENABLE_BL31_RUNTIME_LOG
default 1
depends on _ENABLE_BL31_RUNTIME_LOG
+source "plat/mediatek/mt7987/Config.in"
source "plat/mediatek/mt7988/Config.in"
endmenu # Platform configurations
--- /dev/null
+++ b/plat/mediatek/mt7987/Config.in
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Copyright (c) 2025 Daniel Golle <daniel@makrotopia.org>
+#
+# MT7987 platform-specific configurations
+#
+
+if _PLAT_MT7987
+
+choice
+ prompt "SPI controller"
+ depends on (_BOOT_DEVICE_SPIM_NAND || _BOOT_DEVICE_SPI_NOR)
+ default _SPIM_CTRL_0 if _BOOT_DEVICE_SPIM_NAND
+ default _SPIM_CTRL_2 if _BOOT_DEVICE_SPI_NOR
+
+ config _SPIM_CTRL_0
+ bool "0"
+
+ config _SPIM_CTRL_2
+ bool "2"
+
+endchoice
+
+config SPIM_CTRL
+ int
+ default 0 if _SPIM_CTRL_0
+ default 2 if _SPIM_CTRL_2
+
+endif # _PLAT_MT7987
--- a/plat/mediatek/mt7987/bl2/bl2.mk
+++ b/plat/mediatek/mt7987/bl2/bl2.mk
@@ -91,7 +91,11 @@ endif # END OF BOOT_DEVICE = ram
ifeq ($(BOOT_DEVICE),nor)
$(eval $(call BL2_BOOT_NOR))
BL2_SOURCES += $(MTK_PLAT_SOC)/bl2/bl2_dev_spi_nor.c
+ifeq ($(SPIM_CTRL),0)
+DTS_NAME := mt7987-spi0
+else
+ifeq ($(SPIM_NAND_PREFER_SPI2),1)
DTS_NAME := mt7987-spi2
+else
+DTS_NAME := mt7987-spi0
+endif
endif # END OF BOOTDEVICE = nor
ifeq ($(BOOT_DEVICE),emmc)
@@ -112,10 +116,18 @@ ifeq ($(BOOT_DEVICE),spim-nand)
$(eval $(call BL2_BOOT_SPI_NAND,0,0))
BL2_SOURCES += $(MTK_PLAT_SOC)/bl2/bl2_dev_spi_nand.c
@@ -118,7 +122,11 @@ ifeq ($(SPIM_NAND_NO_RETRY),1)
BL2_CPPFLAGS += -DSPIM_NAND_NO_RETRY
endif # END OF SPIM_NAND_NO_RETRY
NAND_TYPE ?= spim:2k+64
+ifeq ($(SPIM_CTRL),2)
+ifeq ($(SPIM_NAND_PREFER_SPI2),1)
+DTS_NAME := mt7987-spi2
+else
DTS_NAME := mt7987-spi0
@@ -84,45 +42,3 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
$(eval $(call BL2_BOOT_NAND_TYPE_CHECK,$(NAND_TYPE),spim:2k+64 spim:2k+128 spim:4k+256))
endif # END OF BOOTDEVICE = spim-nand
+ifneq ($(SPIM_CTRL),)
+BL2_CPPFLAGS += -DSPIM_CTRL=$(SPIM_CTRL)
+endif
+
ifeq ($(BROM_HEADER_TYPE),)
$(error BOOT_DEVICE has invalid value. Please re-check.)
endif
--- a/plat/mediatek/mt7987/bl2/bl2_dev_spi_nand.c
+++ b/plat/mediatek/mt7987/bl2/bl2_dev_spi_nand.c
@@ -12,10 +12,18 @@
#define MTK_QSPI_SRC_CLK CB_MPLL_D2
+#if SPIM_CTRL == 0
+#define SELECTED_SPIM SPIM0
+#elif SPIM_CTRL == 2
+#define SELECTED_SPIM SPIM2
+#else
+#error "Invalid SPI controller selection"
+#endif
+
uint32_t mtk_plat_get_qspi_src_clk(void)
{
/* config GPIO pinmux to spi mode */
- mtk_spi_gpio_init(SPIM0);
+ mtk_spi_gpio_init(SELECTED_SPIM);
/* select 208M clk */
mtk_spi_source_clock_select(MTK_QSPI_SRC_CLK);
--- a/plat/mediatek/mt7987/platform.mk
+++ b/plat/mediatek/mt7987/platform.mk
@@ -56,8 +56,8 @@ include make_helpers/dep.mk
$(call GEN_DEP_RULES,bl2,emicfg bl2_boot_ram bl2_boot_nand_nmbm bl2_dev_mmc bl2_plat_init bl2_plat_setup mt7987_gpio dtb)
$(call MAKE_DEP,bl2,emicfg,DDR4_4BG_MODE DRAM_DEBUG_LOG DDR3_FREQ_2133 DDR3_FREQ_1866 DDR4_FREQ_3200 DDR4_FREQ_2666)
-$(call MAKE_DEP,bl2,bl2_plat_init,BL2_COMPRESS)
-$(call MAKE_DEP,bl2,bl2_plat_setup,BOOT_DEVICE TRUSTED_BOARD_BOOT BL32_TZRAM_BASE BL32_TZRAM_SIZE BL32_LOAD_OFFSET)
+$(call MAKE_DEP,bl2,bl2_plat_init,BL2_COMPRESS SPIM_CTRL)
+$(call MAKE_DEP,bl2,bl2_plat_setup,BOOT_DEVICE TRUSTED_BOARD_BOOT BL32_TZRAM_BASE BL32_TZRAM_SIZE BL32_LOAD_OFFSET SPIM_CTRL)
$(call MAKE_DEP,bl2,bl2_dev_mmc,BOOT_DEVICE)
$(call MAKE_DEP,bl2,bl2_boot_ram,RAM_BOOT_DEBUGGER_HOOK RAM_BOOT_UART_DL)
$(call MAKE_DEP,bl2,bl2_boot_nand_nmbm,NMBM_MAX_RATIO NMBM_MAX_RESERVED_BLOCKS NMBM_DEFAULT_LOG_LEVEL)
package/boot/arm-trusted-firmware-mediatek/patches/0007-hack-mt7987-bl2-move-FIP-offset-to-0x100000.patch
+2 -2
View File
@@ -16,9 +16,9 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- a/plat/mediatek/mt7987/bl2/bl2_dev_spi_nor.c
+++ b/plat/mediatek/mt7987/bl2/bl2_dev_spi_nor.c
@@ -7,7 +7,7 @@
#include <stdint.h>
@@ -8,7 +8,7 @@
#include <boot_spi.h>
#include <mtk_spi.h>
-#define FIP_BASE 0x250000
+#define FIP_BASE 0x100000
package/boot/uboot-mediatek/patches/470-add-bpi-r4-lite.patch
+14 -1
View File
@@ -1133,7 +1133,7 @@
+};
--- /dev/null
+++ b/arch/arm/dts/mt7987a-bpi-r4-lite-spim-nand-u-boot.dtsi
@@ -0,0 +1,69 @@
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 MediaTek Inc.
@@ -1163,6 +1163,19 @@
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc_pins_default>;
+ max-frequency = <48000000>;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_3p3v>;
+ non-removable;
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_flash_pins>;
package/boot/uboot-tools/Makefile
+1 -1
View File
@@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk
PKG_DISTNAME:=u-boot
PKG_VERSION:=2026.01
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:= \
package/boot/uboot-tools/uboot-envtools/files/ath79
+1
View File
@@ -46,6 +46,7 @@ librerouter,librerouter-v1|\
moxa,awk-1137c|\
netgear,ex7300|\
netgear,ex7300-v2|\
netgear,wndap360|\
netgear,wndr4300-v2|\
netgear,wndr4500-v3|\
netgear,wnr1000-v2|\
package/system/mtd/src/mtd.c
+1 -1
View File
@@ -774,7 +774,7 @@ static void usage(void)
fprintf(stderr, "Usage: mtd [<options> ...] <command> [<arguments> ...] <device>[:<device>...]\n\n"
"The device is in the format of mtdX (eg: mtd4) or its label.\n"
"mtd recognizes these commands:\n"
" dump dump mtd device\n"
" dump dump mtd device\n"
" unlock unlock the device\n"
" refresh refresh mtd partition\n"
" erase erase all data on device\n"
target/linux/airoha/dts/an7581-evb-emmc-eagle.dts
+39
View File
@@ -0,0 +1,39 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;
#include "an7581-evb-emmc.dtsi"
#include "an7581-npu-mt7996.dtsi"
/ {
model = "Airoha AN7581 Evaluation Board (eMMC + Eagle)";
compatible = "airoha,an7581-evb", "airoha,an7581", "airoha,en7581";
aliases {
serial0 = &uart1;
};
chosen {
bootargs = "console=ttyS0,115200 earlycon";
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x00000000>;
};
};
&pcie2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_rst_pins>;
status = "okay";
};
&en7581_pinctrl {
pcie2_rst_pins: pcie2-rst-pins {
conf {
pins = "pcie_reset2";
drive-open-drain = <1>;
};
};
};
target/linux/airoha/dts/an7581-evb-emmc-kite.dts
+24
View File
@@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;
#include "an7581-evb-emmc.dtsi"
#include "an7581-npu-mt7992.dtsi"
/ {
model = "Airoha AN7581 Evaluation Board (eMMC + Kite)";
compatible = "airoha,an7581-evb", "airoha,an7581", "airoha,en7581";
aliases {
serial0 = &uart1;
};
chosen {
bootargs = "console=ttyS0,115200 earlycon";
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x00000000>;
};
};
target/linux/airoha/dts/an7581-evb-emmc.dts → target/linux/airoha/dts/an7581-evb-emmc.dtsi
-38
View File
@@ -1,33 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;
/* Bootloader installs ATF here */
/memreserve/ 0x80000000 0x200000;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include "an7581.dtsi"
/ {
model = "Airoha AN7581 Evaluation Board";
compatible = "airoha,an7581-evb", "airoha,an7581", "airoha,en7581";
aliases {
serial0 = &uart1;
};
chosen {
bootargs = "console=ttyS0,115200 earlycon";
stdout-path = "serial0:115200n8";
linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x00000000>;
};
};
&sound {
audio-routing = "Headphone", "HP_L",
"Headphone", "HP_R",
@@ -70,13 +47,6 @@
};
};
pcie2_rst_pins: pcie2-rst-pins {
conf {
pins = "pcie_reset2";
drive-open-drain = <1>;
};
};
gswp1_led0_pins: gswp1-led0-pins {
mux {
function = "phy1_led0";
@@ -212,12 +182,6 @@
};
};
&pcie2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_rst_pins>;
status = "okay";
};
&mdio {
as21xx_1: ethernet-phy@1d {
compatible = "ethernet-phy-ieee802.3-c45";
@@ -253,8 +217,6 @@
};
&npu {
firmware-name = "airoha/en7581_MT7996_npu_rv32.bin",
"airoha/en7581_MT7996_npu_data.bin";
status = "okay";
};
target/linux/airoha/dts/an7581-evb.dts
+6 -28
View File
@@ -154,36 +154,14 @@
#address-cells = <1>;
#size-cells = <1>;
bootloader@0 {
label = "bootloader";
reg = <0x00000000 0x00080000>;
read-only;
bl2@0 {
label = "bl2";
reg = <0x0 0x20000>;
};
art@200000 {
label = "art";
reg = <0x00200000 0x00400000>;
};
tclinux@600000 {
label = "tclinux";
reg = <0x00600000 0x03200000>;
};
tclinux_slave@3800000 {
label = "tclinux_alt";
reg = <0x03800000 0x03200000>;
};
rootfs_data@6a00000 {
label = "rootfs_data";
reg = <0x06a00000 0x01400000>;
};
reserved_bmt@7e00000 {
label = "reserved_bmt";
reg = <0x07e00000 0x00200000>;
read-only;
ubi@20000 {
label = "ubi";
reg = <0x20000 0x0>;
};
};
};
target/linux/airoha/dts/an7581-npu-mt7992.dtsi
+6
View File
@@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
&npu {
firmware-name = "airoha/en7581_npu_rv32.bin",
"airoha/en7581_npu_data.bin";
};
target/linux/airoha/dts/an7581-npu-mt7996.dtsi
+6
View File
@@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
&npu {
firmware-name = "airoha/en7581_MT7996_npu_rv32.bin",
"airoha/en7581_MT7996_npu_data.bin";
};
target/linux/airoha/dts/an7581-w1700k-ubi.dts
+1 -2
View File
@@ -6,6 +6,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "an7581.dtsi"
#include "an7581-npu-mt7996.dtsi"
/ {
model = "Gemtek W1700K (OpenWrt U-Boot layout)";
@@ -303,8 +304,6 @@
};
&npu {
firmware-name = "airoha/en7581_MT7996_npu_rv32.bin",
"airoha/en7581_MT7996_npu_data.bin";
status = "okay";
};
target/linux/airoha/image/an7581.mk
+18 -5
View File
@@ -59,16 +59,29 @@ define Device/airoha_an7581-evb
endef
TARGET_DEVICES += airoha_an7581-evb
define Device/airoha_an7581-evb-emmc
define Device/airoha_an7581-evb-emmc-eagle
DEVICE_VENDOR := Airoha
DEVICE_MODEL := AN7581 Evaluation Board (EMMC)
DEVICE_DTS := an7581-evb-emmc
DEVICE_PACKAGES := kmod-i2c-an7581
DEVICE_MODEL := AN7581 Evaluation Board (eMMC + Eagle)
DEVICE_DTS := an7581-evb-emmc-eagle
DEVICE_PACKAGES := kmod-i2c-an7581 airoha-en7581-mt7996-npu-firmware \
kmod-mt7996-firmware wpad-basic-mbedtls
ARTIFACT/preloader.bin := an7581-preloader rfb
ARTIFACT/bl31-uboot.fip := an7581-bl31-uboot rfb
ARTIFACTS := preloader.bin bl31-uboot.fip
endef
TARGET_DEVICES += airoha_an7581-evb-emmc
TARGET_DEVICES += airoha_an7581-evb-emmc-eagle
define Device/airoha_an7581-evb-emmc-kite
DEVICE_VENDOR := Airoha
DEVICE_MODEL := AN7581 Evaluation Board (eMMC + Kite)
DEVICE_DTS := an7581-evb-emmc-kite
DEVICE_PACKAGES := kmod-i2c-an7581 airoha-en7581-mt7992-npu-firmware \
kmod-mt7992-firmware wpad-basic-mbedtls
ARTIFACT/preloader.bin := an7581-preloader rfb
ARTIFACT/bl31-uboot.fip := an7581-bl31-uboot rfb
ARTIFACTS := preloader.bin bl31-uboot.fip
endef
TARGET_DEVICES += airoha_an7581-evb-emmc-kite
define Device/gemtek_w1700k-ubi
DEVICE_VENDOR := Gemtek
target/linux/ath79/dts/ar7161_netgear_wndap360.dts
+8 -2
View File
@@ -11,19 +11,25 @@
model = "Netgear WNDAP360";
chosen {
/delete-property/ bootargs;
bootargs = "console=ttyS0,9600";
};
aliases {
led-boot = &led_power_orange;
led-failsafe = &led_power_orange;
led-running = &led_power_orange;
led-running = &led_power_green;
led-upgrade = &led_power_orange;
};
leds {
compatible = "gpio-leds";
led_power_green: power_green {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
};
led_power_orange: power_orange {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_ORANGE>;
target/linux/ath79/generic/base-files/etc/init.d/bootcount
+1 -2
View File
@@ -12,8 +12,7 @@ boot() {
fw_setenv fwr_verify 0
;;
qihoo,c301)
local n=$(fw_printenv activeregion | cut -d = -f 2)
fw_setenv "image${n}trynum" 0
fw_setenv $(printf "image%strynum" $(fw_printenv -n activeregion)) 0
;;
esac
}
target/linux/ath79/image/generic.mk
+5 -5
View File
@@ -2240,12 +2240,12 @@ define Device/netgear_wndap360
DEVICE_MODEL := WNDAP360
DEVICE_PACKAGES := kmod-owl-loader
IMAGE_SIZE := 7744k
BLOCKSIZE := 256k
KERNEL := kernel-bin | append-dtb | gzip | uImage gzip
KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none
LOADER_TYPE := bin
KERNEL := kernel-bin | append-dtb | lzma | loader-kernel | uImage none
KERNEL_INITRAMFS := $$(KERNEL)
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \
check-size | append-metadata
IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \
append-rootfs | pad-rootfs | check-size | append-metadata
endef
TARGET_DEVICES += netgear_wndap360
target/linux/kirkwood/image/Makefile
+2 -4
View File
@@ -97,11 +97,9 @@ define Device/kernel-size-migration-linksys
2. Run folowing commands in console (ssh or serial): \n$\
\t fw_printenv \n$\
\t fw_setenv nandboot \
"$$$$(fw_printenv nandboot | awk -F= '{sub(/^nandboot=/, "");print}' \
| sed 's/0x300000/0x400000/g')"\n$\
"$$$$(fw_printenv -n nandboot | sed 's/0x300000/0x400000/g')"\n$\
\t fw_setenv altnandboot \
"$$$$(fw_printenv altnandboot | awk -F= '{sub(/^altnandboot=/, "");print}' \
| sed 's/0x300000/0x400000/g')"\n$\
"$$$$(fw_printenv -n altnandboot | sed 's/0x300000/0x400000/g')"\n$\
3. Test if envs are ok by 'fw_printenv'. \
It should be the same except last argument of\
'nand read.e' in 'nandboot' and 'altnandboot'.\n$\
target/linux/mediatek/dts/mt7981b-asus-rt-ax57m.dts
+2 -2
View File
@@ -67,7 +67,7 @@
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
};
wlan24 {
function = LED_FUNCTION_WLAN_2GHZ;
@@ -241,7 +241,7 @@
precal_factory_1010: precal@1010 {
reg = <0x1010 0x6f010>;
};
};
};
};
target/linux/mediatek/dts/mt7981b-bazis-ax3000wm.dts
+10 -10
View File
@@ -53,7 +53,7 @@
gpios = <&pio 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
led_warning: led_fault {
function = LED_FUNCTION_FAULT;
color = <LED_COLOR_ID_RED>;
@@ -78,7 +78,7 @@
gpios = <&pio 35 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
led_lan_back {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
@@ -130,7 +130,7 @@
phy5: phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <5>;
leds {
#address-cells = <1>;
#size-cells = <0>;
@@ -203,11 +203,11 @@
eeprom_factory_0: eeprom@0 {
reg = <0x0 0x1000>;
};
mac_lan: macaddr@4 {
reg = <0x4 0x6>;
};
mac_wan: macaddr@a {
reg = <0xa 0x6>;
};
@@ -218,8 +218,8 @@
mac_wlan_5ghz: macaddr@24 {
reg = <0x24 0x6>;
};
};
};
};
@@ -233,12 +233,12 @@
label = "ubi";
reg = <0x580000 0x7a40000>;
compatible = "linux,ubi";
volumes {
ubi_rootdisk: ubi-volume-fit {
volname = "fit";
};
ubi_ubootenv: ubi-volume-ubootenv {
volname = "ubootenv";
};
@@ -279,7 +279,7 @@
nvmem-cell-names = "eeprom";
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&mac_wlan_2ghz>;
target/linux/mediatek/dts/mt7981b-cudy-wbr3000uax-v1.dtsi
+2 -2
View File
@@ -13,7 +13,7 @@
led-upgrade = &led_warning;
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
@@ -28,7 +28,7 @@
color = <LED_COLOR_ID_BLUE>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
led_warning: led_fault {
function = LED_FUNCTION_FAULT;
color = <LED_COLOR_ID_RED>;
target/linux/mediatek/dts/mt7981b-totolink-x6000r.dts
+4 -4
View File
@@ -22,12 +22,12 @@
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
reg = <0 0x40000000 0 0x10000000>;
device_type = "memory";
};
gpio-keys {
compatible = "gpio-keys";
@@ -84,7 +84,7 @@
nvmem-cells = <&macaddr_factory_14>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <2500>;
full-duplex;
@@ -137,7 +137,7 @@
reg = <3>;
label = "lan1";
};
port@6 {
reg = <6>;
label = "cpu";
target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts
+1 -1
View File
@@ -10,6 +10,6 @@
};
&ubi {
/* reduce ubi partition size from .dtsi to fit into 64M Nand */
/* reduce ubi partition size from .dtsi to fit into 64M Nand */
reg = <0x580000 0x4000000>;
};
target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dtsi
+1 -1
View File
@@ -84,7 +84,7 @@
linux,default-trigger = "phy1tpt";
};
};
};
&eth {
target/linux/mediatek/dts/mt7986a-asiarf-ap7986-003.dts
+1 -1
View File
@@ -218,7 +218,7 @@
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
target/linux/mediatek/dts/mt7986b-tplink-archer-ax80-v1-eu.dts
+34 -34
View File
@@ -11,7 +11,7 @@
/ {
compatible = "tplink,archer-ax80-v1-eu", "mediatek,mt7986b";
model = "TP-Link Archer AX80 v1 (EU)";
aliases {
serial0 = &uart0;
led-boot = &led_power;
@@ -19,58 +19,58 @@
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
device_type = "memory";
};
leds {
compatible = "gpio-leds";
led_power: power {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_POWER;
gpios = <&pio 15 GPIO_ACTIVE_LOW>;
default-state = "on";
};
wlan2g {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_WLAN_2GHZ;
gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_WLAN_5GHZ;
gpios = <&pio 12 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
internet_white {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_WAN_ONLINE;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
internet_orange {
color = <LED_COLOR_ID_ORANGE>;
function = LED_FUNCTION_WAN;
gpios = <&pio 19 GPIO_ACTIVE_LOW>;
};
lan {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_LAN;
gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
};
usb {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_DISK;
@@ -78,36 +78,36 @@
trigger-sources = <&ssusb>;
linux,default-trigger = "usbport";
};
wps {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_WPS;
gpios = <&pio 18 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 14 GPIO_ACTIVE_LOW>;
};
wifi {
label = "wlan";
linux,code = <KEY_WLAN>;
gpios = <&pio 20 GPIO_ACTIVE_LOW>;
};
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -116,7 +116,7 @@
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
@@ -137,7 +137,7 @@
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
@@ -147,25 +147,25 @@
full-duplex;
};
};
mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
phy-handle = <&phy6>;
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
reset-delay-us = <1500000>;
reset-post-delay-us = <1000000>;
reset-post-delay-us = <1000000>;
reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
phy6: phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <6>;
};
switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
@@ -174,7 +174,7 @@
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -213,7 +213,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
@@ -222,44 +222,44 @@
spi-rx-bus-width = <4>;
spi-cal-enable;
spi-cal-mode = "read-data";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x0 0x200000>;
read-only;
};
partition@200000 {
label = "u-boot-env";
reg = <0x200000 0x100000>;
};
partition@300000 {
label = "ubi0";
reg = <0x300000 0x3200000>;
};
partition@3500000 {
label = "ubi1";
reg = <0x3500000 0x3200000>;
};
partition@6700000 {
label = "userconfig";
reg = <0x6700000 0x800000>;
};
partition@6f00000 {
label = "tp_data";
reg = <0x6f00000 0x400000>;
read-only;
};
partition@7300000 {
label = "mali_data";
reg = <0x7300000 0x800000>;
@@ -285,7 +285,7 @@
bias-disable; /* bias-disable */
};
};
wf_2g_5g_pins: wf_2g_5g-pins {
mux {
function = "wifi";
target/linux/mediatek/dts/mt7986b-zyxel-wx5600-t0-ubootmod.dts
+9 -9
View File
@@ -155,7 +155,7 @@
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
eeprom_factory: eeprom@0 {
@@ -315,7 +315,7 @@
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
@@ -325,7 +325,7 @@
phy-handle = <&phy5>;
label = "lan2";
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
@@ -335,22 +335,22 @@
phy-handle = <&phy6>;
label = "lan1";
};
mdio: mdio-bus{
#address-cells = <1>;
#size-cells = <0>;
phy5: phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
reset-assert-us = <600>;
reset-deassert-us = <20000>;
reg = <5>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
@@ -358,7 +358,7 @@
};
};
};
phy6: phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <6>;
@@ -366,7 +366,7 @@
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
target/linux/mediatek/image/filogic.mk
+2 -2
View File
@@ -10,7 +10,7 @@ endef
define Build/fit-with-netgear-top-level-rootfs-node
$(call Build/fit-its,$(1))
$(TOPDIR)/scripts/gen_netgear_rootfs_node.sh $(KERNEL_BUILD_DIR)/root.squashfs > $@.rootfs
$(TOPDIR)/scripts/gen_netgear_rootfs_node.sh $(KERNEL_BUILD_DIR)/root.squashfs$(if $(TARGET_PER_DEVICE_ROOTFS),+pkg=$(ROOTFS_ID/$(DEVICE_NAME))) > $@.rootfs
awk '/configurations/ { system("cat $@.rootfs") } 1' $@.its > $@.its.tmp
@mv -f $@.its.tmp $@.its
@rm -f $@.rootfs
@@ -677,7 +677,7 @@ define Device/bananapi_bpi-r4-common
DEVICE_VENDOR := Bananapi
DEVICE_DTS_DIR := $(DTS_DIR)/
DEVICE_DTS_LOADADDR := 0x45f00000
DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd
DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd mt7988a-bananapi-bpi-r4-wifi-be14
DEVICE_DTC_FLAGS := --pad 4096
DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-mux-pca954x kmod-eeprom-at24 kmod-mt7996-firmware kmod-mt7996-233-firmware \
kmod-rtc-pcf8563 kmod-sfp kmod-phy-aquantia kmod-usb3 e2fsprogs f2fsck mkf2fs mt7988-wo-firmware automount
target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patc → target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patch
View File
target/linux/mediatek/patches-6.12/911-dts-mt7988a-bpi-r4-be14-wifi-eeprom.patch
+283
View File
@@ -0,0 +1,283 @@
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-be14.dtso
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device tree overlay for the BananaPi BPI-R4 with BE14 WiFi module.
+ * Some BE14 modules are shipped with zeroed or incorrect EEPROM
+ * calibration data. This overlay provides known-good EEPROM data
+ * (including correct tx_power values for 2G/5G/6G bands) dumped
+ * from a working BE14 module.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+};
+
+&i2c_wifi {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ address-bits = <8>;
+ page-size = <8>;
+ size = <256>;
+ };
+};
+
+&pcie0 {
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ wifi@0,0 {
+ reg = <0x0000 0 0 0 0>;
+
+ mediatek,eeprom-data = <0x90790400 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0xae682613 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0xae882613 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x11131b1a 0x131b0808 0xe00a0a0a 0x00008038
+ 0x8000001a 0x03000000 0x01010000 0x00100001 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x04070489 0x00000080 0x18090489 0x42888300
+ 0x1c090489 0x96000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000007 0x00000000 0x00000000 0xf24b0bc8 0x3ba5fd5f
+ 0x02800000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0xaf89003c 0xaf8900cb 0x8900a889 0x008c0a00 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x004153c7 0x0044539e 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0xa1a3a081 0xa1990091 0x00910091 0x00910000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x0c000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x22222222 0x66447766 0x44776644 0x77664477
+ 0x66447766 0x44444466 0x44444466 0x44444466 0x44444466 0x44444400 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00800080
+ 0x00800a0a 0x00404040 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000002 0x20000000 0x00000220 0x00000000 0x00022000 0x00000000 0x02200000 0x00000002
+ 0x20000000 0x00000220 0x00000000 0x00022000 0x00000000 0x02200000 0x00000002 0x20000000
+ 0x00000220 0x00000000 0x00022000 0x00000000 0x02200000 0x00000002 0x20000000 0x00000220
+ 0x00000000 0x00022000 0x00000000 0x02200000 0x00000002 0x27000000 0x00000227 0x00000000
+ 0x00022700 0x00000000 0x02270000 0x00000002 0x27000000 0x00000227 0x00000000 0x00022700
+ 0x00000000 0x02270000 0x00000002 0x27000000 0x00000227 0x00000000 0x00022700 0x00000000
+ 0x02270000 0x00000002 0x27000000 0x00000227 0x00000000 0x00022700 0x00000000 0x02270000
+ 0x00000002 0x00000000 0x00000200 0x00000000 0x00020000 0x00000000 0x02000000 0x00000002
+ 0x27000000 0x00000227 0x00000000 0x00022700 0x00000000 0x02270000 0x00000002 0x27000000
+ 0x00000227 0x00000000 0x00022700 0x00000000 0x02270000 0x00000002 0x27000000 0x00000227
+ 0x00000000 0x00022700 0x00000000 0x02270000 0x00000002 0x27000000 0x00000227 0x00000000
+ 0x02270000 0x00000000 0x02270000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x02020280 0x7f000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x20252b31 0x363b4146
+ 0x00564c52 0x575d6167 0x6d10161c 0x22282e35 0x3c005042 0x484e545a 0x60660000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00b40000 0x00b40000 0x00000000 0x00000000
+ 0x00000000 0x0000c400 0xb9008800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000040bd 0x40bd40bd 0x40bd40bd
+ 0x40bd40bd 0x40bd40c8 0x40c640c6 0x40c740c7 0x40c840c7 0x40c640c7 0x40c740c7 0x40c640c5
+ 0x40c640c6 0x40c540c4 0x40c440c4 0x40c30000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x02000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x000000d1 0xd1d1dddd 0xdde9e9e9 0xf5f5f501 0x01010909 0x09151515 0xd1d1d1dd 0xdddde9e9
+ 0xe9f5f5f5 0xfdfdfd09 0x09091515 0x15d1d1d1 0xdddddde9 0xe9e9f5f5 0xf5ffffff 0x07070719
+ 0x1919d7d7 0xd7e3e3e3 0xefefeff7 0xf7f70303 0x03171717 0x1f1f1fcf 0xcfcfdbdb 0xdbe7e7e7
+ 0xf3f3f3ff 0xffff1313 0x13171717 0xd7d7d7e3 0xe3e3efef 0xeff7f7f7 0x03030311 0x11111919
+ 0x19cfcfcf 0xdbdbdbe7 0xe7e7f3f3 0xf3ffffff 0x13131317 0x1717d7d7 0xd7e3e3e3 0xefefeff7
+ 0xf7f70303 0x03111111 0x191919cf 0xcfcfdbdb 0xdbe7e7e7 0xf3f3f3ff 0xffff1313 0x13171717
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00350035 0x0035002d 0x00300000 0x00000000
+ 0x00000000 0x00000000 0x00cdcd00 0x00000000 0x00000000 0x00000000 0x0000c400 0xc4009600
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x29272727 0x27250000 0x00000000 0x00000000 0x22242424 0x21212121 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000080 0x80c18080 0x80808080 0x80808080 0x80808080 0x808080c1
+ 0x80c180c1 0xc18080c1 0x80808080 0x80808080 0x80808000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00808080 0x80808080 0x80808080
+ 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080
+ 0x80808080 0x80808080 0x80808080 0x80808080 0x80000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0xc6c6c4c4 0xc30000c1 0xc1c18383 0x83838386 0x86c1c183 0x83838383 0x8686c1c1 0xc1818181
+ 0x82838585 0x86868888 0xc1c1c181 0x81818283 0x85858686 0x8888c1c1 0xc1818181 0x82838585
+ 0x86868888 0xc1c1c181 0x81818283 0x85858686 0x8888c1c1 0xc1818181 0x82838585 0x86868888
+ 0xc1c1c181 0x81818283 0x85858686 0x8888c1c1 0xc1818181 0x82838585 0x86868888 0xc1c5c5c3
+ 0xc100c2c2 0xc2c2c2c1 0x00818383 0xc1c1c1c1 0x00008183 0x83c2c1c1 0xc1c10000 0x818383c1
+ 0xc2c2c2c2 0xc1008183 0x83848487 0x87c2c1c1 0xc1c10000 0x81838384 0x848888c1 0xc1c1c1c1
+ 0x00008183 0x83868689 0x89c1c181 0x81838484 0x84858686 0x88888b8b 0x8281c2c2 0xc2c2c100
+ 0x81838384 0x848787c2 0xc2c2c2c2 0xc1008183 0x83848487 0x87c2c2c2 0xc2c2c100 0x81838384
+ 0x848787c2 0xc2c2c2c2 0xc1008183 0x83848487 0x87c2c2c2 0xc2c2c100 0x81838384 0x848787c2
+ 0xc1c1c1c1 0x00008183 0x83868689 0x89c18181 0x83848484 0x85868688 0x888b8b81 0x81818384
+ 0x84848586 0x8688888b 0x8b81c5c5 0xc3c100c2 0xc2c2c200 0x81828383 0x85858787 0xc2c2c2c2
+ 0xc2008182 0x83838585 0x8787c2c1 0xc1c1c181 0x82838484 0x86868a8a 0xc1c18282 0x84848484
+ 0x84858586 0x868c8c82 0x82c2c2c2 0xc2008182 0x83838585 0x8787c2c2 0xc2c2c200 0x81828383
+ 0x85858787 0xc2c2c2c2 0xc2008182 0x83838585 0x8787c2c2 0xc2c2c200 0x81828383 0x85858787
+ 0xc2c2c2c2 0xc2008182 0x83838585 0x8787c2c1 0xc1c1c181 0x82838484 0x86868a8a 0xc1c18282
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x84848484 0x84858586 0x868c8c82 0x82828284 0x84848484 0x85858686 0x8c8c8282 0x87878888
+ 0x88888888 0x8888888d 0x8d878787 0x87888888 0x88888888 0x88888d8d 0x87878787 0x88888888
+ 0x88888888 0x888d8d87 0x87878788 0x88888888 0x88888888 0x8d8d8787 0x00818181 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x82830000 0x00000000 0xc4c1c4c1 0x80c280c1
+ 0xc180c1c2 0xc3c1c4c1 0xc1c280c3 0xc1c1c1c3 0xc4c4c5c1 0xc2c480c4 0xc3c2c2c2 0x80808080
+ 0x80808080 0x80808080 0x00000000 0x00000000 0x00000000 0x80808080 0x80808080 0x80808080
+ 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080
+ 0x80808080 0x00000000 0x00000000 0x00000000 0x85868685 0x80828481 0x87868584 0x82c1c286
+ 0x87828387 0x85828d8d 0x8d909090 0x85838486 0x82808180 0x868480c1 0x80c1c284 0x86818086
+ 0x81808d8d 0x8d909090 0x83848386 0x81c18080 0x87858280 0xc1c2c483 0x86808086 0x82808d8d
+ 0x8d909090 0x8c8c8c8c 0x8c8c8c8c 0x8f8f8f8f 0x8f8f8d8e 0x8e8e8e91 0x91918d8d 0x8d909090
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x80808080
+ 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080
+ 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080
+ 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080 0x80808080
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80808080 0x80808080 0x80808080 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000a00 0x000c0000 0x0d000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x2f7f7f7f 0x13110f2c 0x007f7f00 0x110a0000 0x2f7f7f7f 0x13110f2c 0x007f7f00 0x110a0000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+};
target/linux/qualcommax/dts/ipq5018-scr50axe.dts
+1 -1
View File
@@ -295,7 +295,7 @@
nand-bus-width = <8>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partitions {
compatible = "qcom,smem-part";
target/linux/qualcommax/dts/ipq6000-link.dtsi
+1 -1
View File
@@ -64,7 +64,7 @@
&tlmm {
gpio-reserved-ranges = <20 1>;
mdio_pins: mdio-pins {
mdc {
pins = "gpio64";
target/linux/qualcommax/dts/ipq8072-mx5300.dts
+1
View File
@@ -19,6 +19,7 @@
led-running = &led_system_blue;
led-failsafe = &led_system_red;
led-upgrade = &led_system_green;
label-mac-device = &dp2;
};
chosen {
target/linux/ramips/dts/mt7621_cudy_ap1300-outdoor-v1.dts
+4 -4
View File
@@ -9,12 +9,12 @@
/ {
compatible = "cudy,ap1300-outdoor-v1", "mediatek,mt7621-soc";
model = "Cudy AP1300 Outdoor v1";
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
led-upgrade = &led_sys;
label-mac-device = &gmac0;
};
@@ -70,9 +70,9 @@
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_5GHZ;
linux,default-trigger = "phy1tpt";
};
};
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
target/linux/ramips/dts/mt7621_cudy_c200p.dts
+1 -1
View File
@@ -28,7 +28,7 @@
hw_margin_ms = <1000>;
always-running;
};
gpio-export {
compatible = "gpio-export";
#size-cells = <0>;
target/linux/ramips/dts/mt7628an_cudy_re1200-outdoor-v1.dts
+1 -1
View File
@@ -71,7 +71,7 @@
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_5GHZ;
linux,default-trigger = "phy1tpt";
};
};
};
};
target/linux/ramips/mt7620/config-6.18
+1
View File
@@ -158,6 +158,7 @@ CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_PAGE_BLOCK_MAX_ORDER=10
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
target/linux/ramips/mt7621/config-6.18
+1
View File
@@ -210,6 +210,7 @@ CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_PADATA=y
CONFIG_PAGE_BLOCK_MAX_ORDER=10
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
target/linux/ramips/mt76x8/config-6.18
+1
View File
@@ -148,6 +148,7 @@ CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_PAGE_BLOCK_MAX_ORDER=10
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
target/linux/ramips/patches-6.18/933-MIPS-SMP-Wait-for-secondary-CPUs-to-stop-in-smp_send.patch
+1 -1
View File
@@ -16,7 +16,7 @@ Signed-off-by: Rany Hany <rany_hany@riseup.net>
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -416,7 +416,17 @@ static void stop_this_cpu(void *dummy)
@@ -427,7 +427,17 @@ static void stop_this_cpu(void *dummy)
void smp_send_stop(void)
{
target/linux/ramips/patches-6.18/934-MIPS-SMP-Properly-stop-secondary-CPUs-for-restart.patch
+2 -2
View File
@@ -25,7 +25,7 @@ Signed-off-by: Rany Hany <rany_hany@riseup.net>
#include <asm/mips-cps.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
@@ -402,6 +403,8 @@ asmlinkage void start_secondary(void)
@@ -413,6 +414,8 @@ asmlinkage void start_secondary(void)
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}
@@ -34,7 +34,7 @@ Signed-off-by: Rany Hany <rany_hany@riseup.net>
static void stop_this_cpu(void *dummy)
{
/*
@@ -411,13 +414,66 @@ static void stop_this_cpu(void *dummy)
@@ -422,13 +425,66 @@ static void stop_this_cpu(void *dummy)
set_cpu_online(smp_processor_id(), false);
calculate_cpu_foreign_map();
local_irq_disable();
target/linux/ramips/rt288x/config-6.18
+1
View File
@@ -141,6 +141,7 @@ CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_PAGE_BLOCK_MAX_ORDER=10
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
target/linux/ramips/rt305x/config-6.18
+1
View File
@@ -141,6 +141,7 @@ CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_PAGE_BLOCK_MAX_ORDER=10
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
target/linux/ramips/rt3883/config-6.18
+1
View File
@@ -139,6 +139,7 @@ CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_PAGE_BLOCK_MAX_ORDER=10
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
target/linux/realtek/dts/rtl9301_linksys_lgs328c.dts
+4 -4
View File
@@ -111,7 +111,7 @@
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, usxgmii)
SWITCH_PORT_SDS(9, 10, 2, usxgmii)
SWITCH_PORT_SDS(10, 11, 2, usxgmii)
@@ -120,7 +120,7 @@
SWITCH_PORT_SDS(13, 14, 2, usxgmii)
SWITCH_PORT_SDS(14, 15, 2, usxgmii)
SWITCH_PORT_SDS(15, 16, 2, usxgmii)
SWITCH_PORT_SDS(16, 17, 3, usxgmii)
SWITCH_PORT_SDS(17, 18, 3, usxgmii)
SWITCH_PORT_SDS(18, 19, 3, usxgmii)
@@ -129,7 +129,7 @@
SWITCH_PORT_SDS(21, 22, 3, usxgmii)
SWITCH_PORT_SDS(22, 23, 3, usxgmii)
SWITCH_PORT_SDS(23, 24, 3, usxgmii)
port@24 {
reg = <24>;
label = "lan25";
@@ -162,7 +162,7 @@
managed = "in-band-status";
sfp = <&sfp3>;
};
port@28 {
reg = <28>;
ethernet = <&ethernet0>;
target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-common.dtsi
+1 -1
View File
@@ -272,7 +272,7 @@
SWITCH_PORT_LED(24, 9, 6, 1, usxgmii)
SWITCH_PORT_LED(25, 10, 7, 1, usxgmii)
SWITCH_PORT_LED(26, 11, 8, 1, usxgmii)
port27: port@27 {
reg = <27>;
label = "lan12";
target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
+1 -1
View File
@@ -128,7 +128,7 @@
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_LED(0, 1, 2, 0, usxgmii)
SWITCH_PORT_LED(1, 2, 2, 0, usxgmii)
SWITCH_PORT_LED(2, 3, 2, 0, usxgmii)
target/linux/realtek/dts/rtl9313_xikestor_sks8300-12x-v1.dts
+2 -2
View File
@@ -54,14 +54,14 @@
/* LED[0]: green | LED[1]: amber */
led_set0 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)
RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G |
RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
};
/*
* Diodes PT7A7514WE is fed by hardware-assisted SYS_LED. There is no
* real driver for this. However, this node causes a quirk being applied
* real driver for this. However, this node causes a quirk being applied
* very early to avoid a reset during early boot.
*/
watchdog1: watchdog {
target/linux/realtek/files-6.12/arch/mips/rtl-otto/prom.c
+1 -1
View File
@@ -327,7 +327,7 @@ static void prepare_highmem(void)
*
* Whenever CPU accesses memory the normal MIPS translation is applied and afterwards
* the bus adds the zone mapping. E.g. a read to 0x81230000 is converted to an cached
* memory access to logical address 0x01230000. It is issued to the OCP bus and the
* memory access to logical address 0x01230000. It is issued to the OCP bus and the
* mapping from zone 1 register is added. That allows for two memory topologies:
*
* Linear memory with a maximum of 320 MB:
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
+3 -3
View File
@@ -820,7 +820,7 @@ static int rtpcs_838x_sds_patch(struct rtpcs_serdes *sds,
default:
break;
}
return 0;
}
@@ -856,7 +856,7 @@ static int rtpcs_838x_setup_serdes(struct rtpcs_serdes *sds,
rtpcs_838x_sds_patch(sds, hw_mode);
rtpcs_838x_sds_reset(sds);
/* release reset */
rtpcs_sds_write(sds, 0, 3, 0x7106);
@@ -1287,7 +1287,7 @@ pll_setup:
/* RTL930X */
/*
/*
* RTL930X needs a special mapping from logic SerDes ID to physical SerDes ID,
* which takes the page into account. This applies to most of read/write calls.
*/
target/linux/realtek/files-6.18/arch/mips/rtl-otto/prom.c
+1 -1
View File
@@ -327,7 +327,7 @@ static void prepare_highmem(void)
*
* Whenever CPU accesses memory the normal MIPS translation is applied and afterwards
* the bus adds the zone mapping. E.g. a read to 0x81230000 is converted to an cached
* memory access to logical address 0x01230000. It is issued to the OCP bus and the
* memory access to logical address 0x01230000. It is issued to the OCP bus and the
* mapping from zone 1 register is added. That allows for two memory topologies:
*
* Linear memory with a maximum of 320 MB:
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c
+13 -59
View File
@@ -211,72 +211,27 @@ u64 rtl839x_get_port_reg_le(int reg)
return v;
}
static int rtldsa_bus_read(struct mii_bus *bus, int addr, int regnum)
{
struct rtl838x_switch_priv *priv = bus->priv;
return mdiobus_read_nested(priv->parent_bus, addr, regnum);
}
static int rtldsa_bus_write(struct mii_bus *bus, int addr, int regnum, u16 val)
{
struct rtl838x_switch_priv *priv = bus->priv;
return mdiobus_write_nested(priv->parent_bus, addr, regnum, val);
}
static int rtldsa_bus_c45_read(struct mii_bus *bus, int addr, int devad, int regnum)
{
struct rtl838x_switch_priv *priv = bus->priv;
return mdiobus_c45_read_nested(priv->parent_bus, addr, devad, regnum);
}
static int rtldsa_bus_c45_write(struct mii_bus *bus, int addr, int devad, int regnum, u16 val)
{
struct rtl838x_switch_priv *priv = bus->priv;
return mdiobus_c45_write_nested(priv->parent_bus, addr, devad, regnum, val);
}
static int rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
{
struct device_node *dn, *phy_node, *pcs_node, *led_node;
struct device *dev = priv->dev;
struct mii_bus *bus;
int ret;
u32 pn;
/* Check if all busses of Realtek mdio controller are registered */
dn = of_find_compatible_node(NULL, NULL, "realtek,otto-mdio");
if (!dn)
if (!of_device_is_available(dn)) {
of_node_put(dn);
return -ENODEV;
}
if (!of_device_is_available(dn))
ret = -ENODEV;
priv->parent_bus = of_mdio_find_bus(dn);
if (!priv->parent_bus)
return -EPROBE_DEFER;
bus = devm_mdiobus_alloc(priv->ds->dev);
if (!bus)
return -ENOMEM;
bus->name = "rtldsa_mdio";
bus->read = rtldsa_bus_read;
bus->write = rtldsa_bus_write;
bus->read_c45 = rtldsa_bus_c45_read;
bus->write_c45 = rtldsa_bus_c45_write;
bus->phy_mask = priv->parent_bus->phy_mask;
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
bus->parent = dev;
priv->ds->user_mii_bus = bus;
priv->ds->user_mii_bus->priv = priv;
ret = mdiobus_register(priv->ds->user_mii_bus);
if (ret)
return ret;
for_each_child_of_node_scoped(dn, bn) {
struct mii_bus *bus = of_mdio_find_bus(bn);
if (!bus) {
of_node_put(dn);
return -EPROBE_DEFER;
}
put_device(&bus->dev);
}
of_node_put(dn);
dn = of_find_compatible_node(NULL, NULL, "realtek,otto-switch");
if (!dn) {
@@ -1610,7 +1565,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
return err;
priv->family_id = soc_info.family;
priv->id = soc_info.id;
sw_w32(0, priv->r->spanning_tree_ctrl);
priv->irq_mask = GENMASK_ULL(priv->r->cpu_port - 1, 0);
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c
+11 -28
View File
@@ -2056,9 +2056,9 @@ static bool rtldsa_mac_is_unsnoop(const unsigned char *addr)
return false;
}
static int rtldsa_port_mdb_add(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_mdb *mdb,
const struct dsa_db db)
static int rtldsa_83xx_port_mdb_add(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_mdb *mdb,
const struct dsa_db db)
{
struct rtl838x_switch_priv *priv = ds->priv;
u64 mac = ether_addr_to_u64(mdb->addr);
@@ -2068,9 +2068,6 @@ static int rtldsa_port_mdb_add(struct dsa_switch *ds, int port,
u64 seed = priv->r->l2_hash_seed(mac, vid);
int mc_group;
if (priv->id >= 0x9300)
return -EOPNOTSUPP;
pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
if (priv->lag_non_primary & BIT_ULL(port)) {
@@ -2138,6 +2135,12 @@ out:
return err;
}
static int rtldsa_93xx_port_mdb_add(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_mdb *mdb,
const struct dsa_db db)
{
return -EOPNOTSUPP;
}
static int rtldsa_port_mdb_del(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_mdb *mdb,
@@ -2498,20 +2501,6 @@ out:
return 0;
}
static int rtldsa_phy_read(struct dsa_switch *ds, int addr, int regnum)
{
struct rtl838x_switch_priv *priv = ds->priv;
return mdiobus_read_nested(priv->parent_bus, addr, regnum);
}
static int rtldsa_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
{
struct rtl838x_switch_priv *priv = ds->priv;
return mdiobus_write_nested(priv->parent_bus, addr, regnum, val);
}
static const struct flow_action_entry *rtldsa_rate_policy_extract(struct flow_cls_offload *cls)
{
struct flow_rule *rule;
@@ -2635,9 +2624,6 @@ const struct dsa_switch_ops rtldsa_83xx_switch_ops = {
.get_tag_protocol = rtldsa_get_tag_protocol,
.setup = rtldsa_83xx_setup,
.phy_read = rtldsa_phy_read,
.phy_write = rtldsa_phy_write,
.phylink_get_caps = rtldsa_83xx_phylink_get_caps,
.get_strings = rtldsa_get_strings,
@@ -2673,7 +2659,7 @@ const struct dsa_switch_ops rtldsa_83xx_switch_ops = {
.port_fdb_del = rtldsa_port_fdb_del,
.port_fdb_dump = rtldsa_port_fdb_dump,
.port_mdb_add = rtldsa_port_mdb_add,
.port_mdb_add = rtldsa_83xx_port_mdb_add,
.port_mdb_del = rtldsa_port_mdb_del,
.port_mirror_add = rtldsa_port_mirror_add,
@@ -2698,9 +2684,6 @@ const struct dsa_switch_ops rtldsa_93xx_switch_ops = {
.get_tag_protocol = rtldsa_get_tag_protocol,
.setup = rtldsa_93xx_setup,
.phy_read = rtldsa_phy_read,
.phy_write = rtldsa_phy_write,
.phylink_get_caps = rtldsa_93xx_phylink_get_caps,
.get_strings = rtldsa_get_strings,
@@ -2736,7 +2719,7 @@ const struct dsa_switch_ops rtldsa_93xx_switch_ops = {
.port_fdb_del = rtldsa_port_fdb_del,
.port_fdb_dump = rtldsa_port_fdb_dump,
.port_mdb_add = rtldsa_port_mdb_add,
.port_mdb_add = rtldsa_93xx_port_mdb_add,
.port_mdb_del = rtldsa_port_mdb_del,
.port_mirror_add = rtldsa_port_mirror_add,
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/qos.c
+23 -24
View File
@@ -133,26 +133,26 @@ static void rtl839x_setup_prio2queue_matrix(int *min_queues)
}
/* Sets the CPU queue depending on the internal priority of a packet */
static void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues)
static void rtl83xx_setup_prio2queue_cpu_matrix(int reg)
{
int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP
: RTL839X_QM_PKT2CPU_INTPRI_MAP;
u32 v = 0;
pr_info("QM_PKT2CPU_INTPRI_MAP: %08x\n", sw_r32(reg));
for (int i = 0; i < MAX_PRIOS; i++)
v |= max_queues[i] << (i * 3);
v |= rtldsa_max_available_queue[i] << (i * 3);
sw_w32(v, reg);
}
static void rtl83xx_setup_default_prio2queue(void)
static void rtl838x_setup_default_prio2queue(void)
{
if (soc_info.family == RTL8380_FAMILY_ID)
rtl838x_setup_prio2queue_matrix(rtldsa_max_available_queue);
else
rtl839x_setup_prio2queue_matrix(rtldsa_max_available_queue);
rtl838x_setup_prio2queue_matrix(rtldsa_max_available_queue);
rtl83xx_setup_prio2queue_cpu_matrix(RTL838X_QM_PKT2CPU_INTPRI_MAP);
}
rtl83xx_setup_prio2queue_cpu_matrix(rtldsa_max_available_queue);
static void rtl839x_setup_default_prio2queue(void)
{
rtl839x_setup_prio2queue_matrix(rtldsa_max_available_queue);
rtl83xx_setup_prio2queue_cpu_matrix(RTL839X_QM_PKT2CPU_INTPRI_MAP);
}
/* Sets the output queue assigned to a port, the port can be the CPU-port */
@@ -162,12 +162,11 @@ void rtl839x_set_egress_queue(int port, int queue)
}
/* Sets the priority assigned of an ingress port, the port can be the CPU-port */
static void rtl83xx_set_ingress_priority(int port, int priority)
static void rtldsa_839x_set_ingress_priority(int port, int priority)
{
if (soc_info.family == RTL8380_FAMILY_ID)
sw_w32(priority << ((port % 10) * 3), RTL838X_PRI_SEL_PORT_PRI(port));
else
sw_w32(priority << ((port % 10) * 3), RTL839X_PRI_SEL_PORT_PRI(port));
int shift = ((port % 10) * 3);
sw_w32_mask(7 << shift, priority << shift, RTL839X_PRI_SEL_PORT_PRI(port));
}
static int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port)
@@ -275,7 +274,7 @@ void rtldsa_838x_qos_init(struct rtl838x_switch_priv *priv)
pr_info("Setting up RTL838X QoS\n");
pr_info("RTL838X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL838X_PRI_SEL_TBL_CTRL(0)));
rtl83xx_setup_default_prio2queue();
rtl838x_setup_default_prio2queue();
/* Enable inner (bit 12) and outer (bit 13) priority remapping from DSCP */
sw_w32_mask(0, BIT(12) | BIT(13), RTL838X_PRI_DSCP_INVLD_CTRL0);
@@ -299,14 +298,14 @@ void rtldsa_838x_qos_init(struct rtl838x_switch_priv *priv)
sw_w32(v, RTL838X_PRI_SEL_IPRI_REMAP);
/* On all ports set scheduler type to WFQ */
for (int i = 0; i <= soc_info.cpu_port; i++)
for (int i = 0; i <= priv->r->cpu_port; i++)
sw_w32(0, RTL838X_SCHED_P_TYPE_CTRL(i));
/* Enable egress scheduler for CPU-Port */
sw_w32_mask(0, BIT(8), RTL838X_SCHED_LB_CTRL(soc_info.cpu_port));
sw_w32_mask(0, BIT(8), RTL838X_SCHED_LB_CTRL(priv->r->cpu_port));
/* Enable egress drop allways on */
sw_w32_mask(0, BIT(11), RTL838X_FC_P_EGR_DROP_CTRL(soc_info.cpu_port));
sw_w32_mask(0, BIT(11), RTL838X_FC_P_EGR_DROP_CTRL(priv->r->cpu_port));
/* Give special trap frames priority 7 (BPDUs) and routing exceptions: */
sw_w32_mask(0, 7 << 3 | 7, RTL838X_QM_PKT2CPU_INTPRI_2);
@@ -320,16 +319,16 @@ void rtldsa_839x_qos_init(struct rtl838x_switch_priv *priv)
pr_info("Setting up RTL839X QoS\n");
pr_info("RTL839X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL839X_PRI_SEL_TBL_CTRL(0)));
rtl83xx_setup_default_prio2queue();
rtl839x_setup_default_prio2queue();
for (int port = 0; port < soc_info.cpu_port; port++)
for (int port = 0; port < priv->r->cpu_port; port++)
sw_w32(7, RTL839X_QM_PORT_QNUM(port));
/* CPU-port gets queue number 7 */
sw_w32(7, RTL839X_QM_PORT_QNUM(soc_info.cpu_port));
sw_w32(7, RTL839X_QM_PORT_QNUM(priv->r->cpu_port));
for (int port = 0; port <= soc_info.cpu_port; port++) {
rtl83xx_set_ingress_priority(port, 0);
for (int port = 0; port <= priv->r->cpu_port; port++) {
rtldsa_839x_set_ingress_priority(port, 0);
rtl839x_set_scheduling_algorithm(priv, port, WEIGHTED_FAIR_QUEUE);
rtl839x_set_scheduling_queue_weights(priv, port, rtldsa_default_queue_weights);
/* Do re-marking based on outer tag */
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.h
-2
View File
@@ -1516,14 +1516,12 @@ struct rtl838x_switch_priv {
/* Switch operation */
struct dsa_switch *ds;
struct device *dev;
u16 id;
u16 family_id;
struct rtldsa_port ports[57];
struct mutex reg_mutex; /* Mutex for individual register manipulations */
struct mutex pie_mutex; /* Mutex for Packet Inspection Engine */
int link_state_irq;
int mirror_group_ports[4];
struct mii_bus *parent_bus;
const struct rtldsa_config *r;
u64 irq_mask;
struct dentry *dbgfs_dir;
target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c
+169 -185
View File
@@ -4,6 +4,7 @@
#include <linux/fwnode_mdio.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -107,8 +108,8 @@
#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL3 (0x0CFC)
#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL4 (0x0D00)
#define for_each_phy(ctrl, addr) \
for_each_set_bit(addr, ctrl->valid_ports, RTMDIO_MAX_PHY)
#define for_each_port(ctrl, pn) \
for_each_set_bit(pn, ctrl->valid_ports, RTMDIO_MAX_PHY)
#define rtmdio_ctrl_from_bus(bus) \
(((struct rtmdio_chan *)(bus)->priv)->ctrl)
@@ -176,7 +177,6 @@
*/
struct rtmdio_port {
struct device_node *dn;
int page;
bool raw;
u8 smi_addr;
@@ -185,6 +185,7 @@ struct rtmdio_port {
struct rtmdio_bus {
bool is_c45;
struct mii_bus *mii_bus;
};
struct rtmdio_ctrl {
@@ -198,6 +199,7 @@ struct rtmdio_ctrl {
struct rtmdio_chan {
struct rtmdio_ctrl *ctrl;
u8 smi_bus;
};
struct rtmdio_config {
@@ -205,12 +207,12 @@ struct rtmdio_config {
int raw_page;
int bus_map_base;
int port_map_base;
int (*read_mmd_phy)(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val);
int (*read_phy)(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val);
int (*reset)(struct mii_bus *bus);
void (*setup_polling)(struct mii_bus *bus);
int (*write_mmd_phy)(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val);
int (*write_phy)(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val);
int (*read_mmd_phy)(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val);
int (*read_phy)(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val);
int (*setup_ctrl)(struct rtmdio_ctrl *ctrl);
void (*setup_polling)(struct rtmdio_ctrl *ctrl);
int (*write_mmd_phy)(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val);
int (*write_phy)(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val);
};
struct rtmdio_phy_info {
@@ -225,15 +227,15 @@ struct rtmdio_phy_info {
static int rtmdio_phy_to_port(struct mii_bus *bus, int phy)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
struct rtmdio_chan *chan = bus->priv;
struct rtmdio_ctrl *ctrl = chan->ctrl;
int pn;
if (phy < 0 || phy >= ctrl->cfg->num_phys)
return -ENOENT;
for_each_port(ctrl, pn)
if (ctrl->port[pn].smi_bus == chan->smi_bus && ctrl->port[pn].smi_addr == phy)
return pn;
if (!test_bit(phy, ctrl->valid_ports))
return -ENOENT;
return phy;
return -ENOENT;
}
static int rtmdio_run_cmd(struct mii_bus *bus, int cmd, int mask, int regnum, int fail)
@@ -259,14 +261,14 @@ static int rtmdio_838x_run_cmd(struct mii_bus *bus, int cmd)
RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1, RTMDIO_838X_CMD_FAIL);
}
static int rtmdio_838x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val)
static int rtmdio_838x_read_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
u32 park_page = 31;
int err;
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, addr << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(pn));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, pn << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1,
reg << 20 | park_page << 15 | page << 3);
err = rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_READ_C22);
@@ -278,12 +280,12 @@ static int rtmdio_838x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg
return err;
}
static int rtmdio_838x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val)
static int rtmdio_838x_write_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
u32 park_page = 31;
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(pn));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, val << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1,
reg << 20 | park_page << 15 | page << 3);
@@ -291,13 +293,13 @@ static int rtmdio_838x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 re
return rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C22);
}
static int rtmdio_838x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val)
static int rtmdio_838x_read_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err;
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, addr << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(pn));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, pn << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3, devnum << 16 | regnum);
err = rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_READ_C45);
if (!err)
@@ -308,11 +310,11 @@ static int rtmdio_838x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u
return err;
}
static int rtmdio_838x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val)
static int rtmdio_838x_write_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(pn));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, val << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3, devnum << 16 | regnum);
@@ -325,13 +327,13 @@ static int rtmdio_839x_run_cmd(struct mii_bus *bus, int cmd)
RTMDIO_839X_PHYREG_ACCESS_CTRL, RTMDIO_839X_CMD_FAIL);
}
static int rtmdio_839x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val)
static int rtmdio_839x_read_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err;
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_CTRL, 0x1ff);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, addr << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, pn << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL,
reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23);
err = rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C22);
@@ -343,26 +345,26 @@ static int rtmdio_839x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg
return err;
}
static int rtmdio_839x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val)
static int rtmdio_839x_write_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_CTRL, 0x1ff);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(addr));
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(addr) >> 32);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(pn));
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(pn) >> 32);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL,
reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23);
return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C22);
}
static int rtmdio_839x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val)
static int rtmdio_839x_read_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err;
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, addr << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, pn << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_MMD_CTRL, (devnum << 16) | (regnum & 0xffff));
err = rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C45);
if (!err)
@@ -373,12 +375,12 @@ static int rtmdio_839x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u
return err;
}
static int rtmdio_839x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val)
static int rtmdio_839x_write_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(addr));
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(addr) >> 32);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(pn));
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(pn) >> 32);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_MMD_CTRL, (devnum << 16) | (regnum & 0xffff));
@@ -391,12 +393,12 @@ static int rtmdio_930x_run_cmd(struct mii_bus *bus, int cmd)
RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1, RTMDIO_930X_CMD_FAIL);
}
static int rtmdio_930x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val)
static int rtmdio_930x_write_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
u32 park_page = 31;
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(pn));
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, val << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1,
reg << 20 | page << 3 | park_page << 15);
@@ -404,13 +406,13 @@ static int rtmdio_930x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 re
return rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C22);
}
static int rtmdio_930x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val)
static int rtmdio_930x_read_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
u32 park_page = 31;
int err;
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, addr << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, pn << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1,
reg << 20 | page << 3 | park_page << 15);
err = rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_READ_C22);
@@ -422,23 +424,23 @@ static int rtmdio_930x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg
return err;
}
static int rtmdio_930x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val)
static int rtmdio_930x_write_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(pn));
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, val << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3, (devnum << 16) | (regnum & 0xffff));
return rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C45);
}
static int rtmdio_930x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val)
static int rtmdio_930x_read_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err;
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, addr << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, pn << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3, (devnum << 16) | (regnum & 0xffff));
err = rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_READ_C45);
if (!err)
@@ -455,10 +457,10 @@ static int rtmdio_931x_run_cmd(struct mii_bus *bus, int cmd)
RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0, RTMDIO_931X_CMD_FAIL);
}
static int rtmdio_931x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val)
static int rtmdio_931x_write_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
u64 mask = BIT_ULL(addr);
u64 mask = BIT_ULL(pn);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2, (u32)mask);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4, (u32)(mask >> 32));
@@ -469,12 +471,12 @@ static int rtmdio_931x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 re
return rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C22);
}
static int rtmdio_931x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val)
static int rtmdio_931x_read_phy(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err;
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, addr << 5);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, pn << 5);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0, reg << 6 | page << 11);
err = rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_READ_C22);
if (!err)
@@ -485,12 +487,12 @@ static int rtmdio_931x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg
return err;
}
static int rtmdio_931x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val)
static int rtmdio_931x_read_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err;
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, addr << 5);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, pn << 5);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_MMD_CTRL, (devnum << 16) | (regnum & 0xffff));
err = rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_READ_C45);
if (!err)
@@ -501,10 +503,10 @@ static int rtmdio_931x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u
return err;
}
static int rtmdio_931x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val)
static int rtmdio_931x_write_mmd_phy(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
u64 mask = BIT_ULL(addr);
u64 mask = BIT_ULL(pn);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2, (u32)mask);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4, (u32)(mask >> 32));
@@ -517,16 +519,16 @@ static int rtmdio_931x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum,
static int rtmdio_read_c45(struct mii_bus *bus, int phy, int devnum, int regnum)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err, val, addr;
int err, val, pn;
addr = rtmdio_phy_to_port(bus, phy);
if (addr < 0)
return addr;
pn = rtmdio_phy_to_port(bus, phy);
if (pn < 0)
return pn;
guard(mutex)(&ctrl->lock);
err = (*ctrl->cfg->read_mmd_phy)(bus, addr, devnum, regnum, &val);
pr_debug("rd_MMD(adr=%d, dev=%d, reg=%d) = %d, err = %d\n",
addr, devnum, regnum, val, err);
err = (*ctrl->cfg->read_mmd_phy)(bus, pn, devnum, regnum, &val);
dev_dbg(&bus->dev, "rd_MMD(phy=0x%02x, dev=0x%04x, reg=0x%04x) = 0x%04x, err = %d\n",
phy, devnum, regnum, val, err);
return err ? err : val;
}
@@ -534,21 +536,21 @@ static int rtmdio_read_c45(struct mii_bus *bus, int phy, int devnum, int regnum)
static int rtmdio_read(struct mii_bus *bus, int phy, int regnum)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err, val, addr;
int err, val, pn;
addr = rtmdio_phy_to_port(bus, phy);
if (addr < 0)
return addr;
pn = rtmdio_phy_to_port(bus, phy);
if (pn < 0)
return pn;
guard(mutex)(&ctrl->lock);
if (regnum == RTMDIO_PAGE_SELECT && ctrl->port[addr].page != ctrl->cfg->raw_page)
return ctrl->port[addr].page;
if (regnum == RTMDIO_PAGE_SELECT && ctrl->port[pn].page != ctrl->cfg->raw_page)
return ctrl->port[pn].page;
ctrl->port[addr].raw = (ctrl->port[addr].page == ctrl->cfg->raw_page);
ctrl->port[pn].raw = (ctrl->port[pn].page == ctrl->cfg->raw_page);
err = (*ctrl->cfg->read_phy)(bus, addr, ctrl->port[addr].page, regnum, &val);
pr_debug("rd_PHY(adr=%d, pag=%d, reg=%d) = %d, err = %d\n",
addr, ctrl->port[addr].page, regnum, val, err);
err = (*ctrl->cfg->read_phy)(bus, pn, ctrl->port[pn].page, regnum, &val);
dev_dbg(&bus->dev, "rd_PHY(phy=0x%02x, pag=0x%04x, reg=0x%04x) = 0x%04x, err = %d\n",
phy, ctrl->port[pn].page, regnum, val, err);
return err ? err : val;
}
@@ -556,16 +558,16 @@ static int rtmdio_read(struct mii_bus *bus, int phy, int regnum)
static int rtmdio_write_c45(struct mii_bus *bus, int phy, int devnum, int regnum, u16 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err, addr;
int err, pn;
addr = rtmdio_phy_to_port(bus, phy);
if (addr < 0)
return addr;
pn = rtmdio_phy_to_port(bus, phy);
if (pn < 0)
return pn;
guard(mutex)(&ctrl->lock);
err = (*ctrl->cfg->write_mmd_phy)(bus, addr, devnum, regnum, val);
pr_debug("wr_MMD(adr=%d, dev=%d, reg=%d, val=%d) err = %d\n",
addr, devnum, regnum, val, err);
err = (*ctrl->cfg->write_mmd_phy)(bus, pn, devnum, regnum, val);
dev_dbg(&bus->dev, "wr_MMD(phy=0x%02x, dev=0x%04x, reg=0x%04x, val=0x%04x), err = %d\n",
phy, devnum, regnum, val, err);
return err;
}
@@ -573,49 +575,50 @@ static int rtmdio_write_c45(struct mii_bus *bus, int phy, int devnum, int regnum
static int rtmdio_write(struct mii_bus *bus, int phy, int regnum, u16 val)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int err, page, addr;
int err, page, pn;
addr = rtmdio_phy_to_port(bus, phy);
if (addr < 0)
return addr;
pn = rtmdio_phy_to_port(bus, phy);
if (pn < 0)
return pn;
guard(mutex)(&ctrl->lock);
page = ctrl->port[addr].page;
page = ctrl->port[pn].page;
if (regnum == RTMDIO_PAGE_SELECT)
ctrl->port[addr].page = val;
ctrl->port[pn].page = val;
if (!ctrl->port[addr].raw &&
if (!ctrl->port[pn].raw &&
(regnum != RTMDIO_PAGE_SELECT || page == ctrl->cfg->raw_page)) {
ctrl->port[addr].raw = (page == ctrl->cfg->raw_page);
ctrl->port[pn].raw = (page == ctrl->cfg->raw_page);
err = (*ctrl->cfg->write_phy)(bus, addr, page, regnum, val);
pr_debug("wr_PHY(adr=%d, pag=%d, reg=%d, val=%d) err = %d\n",
addr, page, regnum, val, err);
err = (*ctrl->cfg->write_phy)(bus, pn, page, regnum, val);
dev_dbg(&bus->dev,
"wr_PHY(phy=0x%02x, pag=0x%04x, reg=0x%04x, val=0x%04x), err = %d\n",
phy, page, regnum, val, err);
return err;
}
ctrl->port[addr].raw = false;
ctrl->port[pn].raw = false;
return 0;
}
static void rtmdio_setup_smi_topology(struct rtmdio_ctrl *ctrl)
{
u32 reg, mask, val, addr;
u32 reg, mask, val, pn;
for_each_phy(ctrl, addr) {
for_each_port(ctrl, pn) {
if (ctrl->cfg->bus_map_base) {
reg = (addr / 16) * 4;
mask = 0x3 << ((addr % 16) * 2);
val = ctrl->port[addr].smi_bus << ((addr % 16) * 2);
reg = (pn / 16) * 4;
mask = 0x3 << ((pn % 16) * 2);
val = ctrl->port[pn].smi_bus << ((pn % 16) * 2);
regmap_update_bits(ctrl->map, ctrl->cfg->bus_map_base + reg, mask, val);
}
if (ctrl->cfg->port_map_base) {
reg = (addr / 6) * 4;
mask = 0x1f << ((addr % 6) * 5);
val = ctrl->port[addr].smi_addr << ((addr % 6) * 5);
reg = (pn / 6) * 4;
mask = 0x1f << ((pn % 6) * 5);
val = ctrl->port[pn].smi_addr << ((pn % 6) * 5);
regmap_update_bits(ctrl->map, ctrl->cfg->port_map_base + reg, mask, val);
}
}
@@ -638,11 +641,12 @@ static u32 rtmdio_get_phy_id(struct phy_device *phydev)
return phydev->phy_id;
}
static int rtmdio_get_phy_info(struct mii_bus *bus, int addr, struct rtmdio_phy_info *phyinfo)
static int rtmdio_get_phy_info(struct rtmdio_ctrl *ctrl, int pn, struct rtmdio_phy_info *phyinfo)
{
struct phy_device *phydev = mdiobus_get_phy(bus, addr);
u32 phyid = rtmdio_get_phy_id(phydev);
struct mii_bus *bus = ctrl->bus[ctrl->port[pn].smi_bus].mii_bus;
int addr = ctrl->port[pn].smi_addr;
int ret = 0;
u32 phyid;
/*
* Depending on the attached PHY the polling mechanism must be fine tuned. Basically
@@ -650,6 +654,7 @@ static int rtmdio_get_phy_info(struct mii_bus *bus, int addr, struct rtmdio_phy_
* features.
*/
memset(phyinfo, 0, sizeof(*phyinfo));
phyid = rtmdio_get_phy_id(mdiobus_get_phy(bus, addr));
switch(phyid) {
case RTMDIO_PHY_AQR113C_A:
@@ -681,7 +686,7 @@ static int rtmdio_get_phy_info(struct mii_bus *bus, int addr, struct rtmdio_phy_
phyinfo->has_res_reg = true;
break;
default:
pr_warn("skip polling setup for unknown PHY %08x on address %d\n", phyid, addr);
pr_warn("skip polling setup for unknown PHY %08x on port %d\n", phyid, pn);
ret = -EINVAL;
break;
}
@@ -689,10 +694,8 @@ static int rtmdio_get_phy_info(struct mii_bus *bus, int addr, struct rtmdio_phy_
return ret;
}
static int rtmdio_838x_reset(struct mii_bus *bus)
static int rtmdio_838x_setup_ctrl(struct rtmdio_ctrl *ctrl)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
/*
* PHY_PATCH_DONE enables phy control via SoC. This is required for phy access,
* including patching. Must always be set before the phys are probed.
@@ -703,9 +706,8 @@ static int rtmdio_838x_reset(struct mii_bus *bus)
return 0;
}
static void rtmdio_838x_setup_polling(struct mii_bus *bus)
static void rtmdio_838x_setup_polling(struct rtmdio_ctrl *ctrl)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
int combo_phy;
/* Disable MAC polling for PHY config. It will be activated later in the DSA driver */
@@ -721,10 +723,8 @@ static void rtmdio_838x_setup_polling(struct mii_bus *bus)
regmap_update_bits(ctrl->map, RTMDIO_838X_SMI_GLB_CTRL, BIT(7), combo_phy);
}
static int rtmdio_839x_reset(struct mii_bus *bus)
static int rtmdio_839x_setup_ctrl(struct rtmdio_ctrl *ctrl)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
return 0;
pr_debug("%s called\n", __func__);
@@ -739,47 +739,45 @@ static int rtmdio_839x_reset(struct mii_bus *bus)
return 0;
}
static int rtmdio_930x_reset(struct mii_bus *bus)
static int rtmdio_930x_setup_ctrl(struct rtmdio_ctrl *ctrl)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
unsigned int mask, val;
/* Define C22/C45 bus feature set */
for (int addr = 0; addr < RTMDIO_MAX_SMI_BUS; addr++) {
mask = BIT(16 + addr);
val = ctrl->bus[addr].is_c45 ? mask : 0;
for (int smi_bus = 0; smi_bus < RTMDIO_MAX_SMI_BUS; smi_bus++) {
mask = BIT(16 + smi_bus);
val = ctrl->bus[smi_bus].is_c45 ? mask : 0;
regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL, mask, val);
}
return 0;
}
static void rtmdio_930x_setup_polling(struct mii_bus *bus)
static void rtmdio_930x_setup_polling(struct rtmdio_ctrl *ctrl)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
struct rtmdio_phy_info phyinfo;
unsigned int mask, val, addr;
unsigned int mask, val, pn;
/* set everthing to "SerDes driven" */
regmap_write(ctrl->map, RTMDIO_930X_SMI_MAC_TYPE_CTRL, 0);
/* Define PHY specific polling parameters */
for_each_phy(ctrl, addr) {
if (rtmdio_get_phy_info(bus, addr, &phyinfo))
for_each_port(ctrl, pn) {
if (rtmdio_get_phy_info(ctrl, pn, &phyinfo))
continue;
/* set to "PHY driven" */
mask = addr > 23 ? 0x7 << ((addr - 24) * 3 + 12): 0x3 << ((addr / 4) * 2);
mask = pn > 23 ? 0x7 << ((pn - 24) * 3 + 12): 0x3 << ((pn / 4) * 2);
val = phyinfo.mac_type << (ffs(mask) - 1);
regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_MAC_TYPE_CTRL, mask, val);
/* polling via standard or resolution register */
mask = BIT(20 + ctrl->port[addr].smi_bus);
mask = BIT(20 + ctrl->port[pn].smi_bus);
val = phyinfo.has_res_reg ? mask : 0;
regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL, mask, val);
/* proprietary Realtek 1G/2.5 lite polling */
mask = BIT(addr);
mask = BIT(pn);
val = phyinfo.has_giga_lite ? mask : 0;
regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_PRVTE_POLLING_CTRL, mask, val);
@@ -792,9 +790,8 @@ static void rtmdio_930x_setup_polling(struct mii_bus *bus)
}
}
static int rtmdio_931x_reset(struct mii_bus *bus)
static int rtmdio_931x_setup_ctrl(struct rtmdio_ctrl *ctrl)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
u32 c45_mask = 0;
/* Disable polling for configuration purposes */
@@ -803,20 +800,19 @@ static int rtmdio_931x_reset(struct mii_bus *bus)
msleep(100);
/* Define C22/C45 bus feature set */
for (int i = 0; i < RTMDIO_MAX_SMI_BUS; i++) {
if (ctrl->bus[i].is_c45)
c45_mask |= 0x2 << (i * 2); /* Std. C45, non-standard is 0x3 */
for (int smi_bus = 0; smi_bus < RTMDIO_MAX_SMI_BUS; smi_bus++) {
if (ctrl->bus[smi_bus].is_c45)
c45_mask |= 0x2 << (smi_bus * 2); /* Std. C45, non-standard is 0x3 */
}
regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL1, GENMASK(7, 0), c45_mask);
return 0;
}
static void rtmdio_931x_setup_polling(struct mii_bus *bus)
static void rtmdio_931x_setup_polling(struct rtmdio_ctrl *ctrl)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
struct rtmdio_phy_info phyinfo;
u32 addr;
u32 pn;
/* set everything to "SerDes driven" */
for (int reg = 0; reg < 4; reg++)
@@ -824,17 +820,17 @@ static void rtmdio_931x_setup_polling(struct mii_bus *bus)
RTMDIO_931X_SMI_PHY_ABLTY_SDS * 0x55555555U);
/* Define PHY specific polling parameters */
for_each_phy(ctrl, addr) {
u8 smi = ctrl->port[addr].smi_bus;
for_each_port(ctrl, pn) {
u8 smi = ctrl->port[pn].smi_bus;
unsigned int mask, val;
if (rtmdio_get_phy_info(bus, addr, &phyinfo))
if (rtmdio_get_phy_info(ctrl, pn, &phyinfo))
continue;
/* set to "PHY driven" */
mask = GENMASK(1, 0) << ((addr % 16) * 2);
mask = GENMASK(1, 0) << ((pn % 16) * 2);
val = RTMDIO_931X_SMY_PHY_ABLTY_MDIO << (ffs(mask) - 1);
regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + (addr / 16) * 4,
regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + (pn / 16) * 4,
mask, val);
mask = val = 0;
@@ -864,17 +860,10 @@ static void rtmdio_931x_setup_polling(struct mii_bus *bus)
}
}
static int rtmdio_reset(struct mii_bus *bus)
{
struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
return ctrl->cfg->reset(bus);
}
static int rtmdio_map_ports(struct device *dev)
{
struct rtmdio_ctrl *ctrl = dev_get_drvdata(dev);
int smi_bus, smi_addr, addr;
int smi_bus, smi_addr, pn;
struct device_node *switch_node __free(device_node) =
of_get_child_by_name(dev->of_node->parent, "ethernet-switch");
@@ -889,7 +878,7 @@ static int rtmdio_map_ports(struct device *dev)
of_fwnode_handle(switch_node));
for_each_child_of_node_scoped(ports, port) {
if (of_property_read_u32(port, "reg", &addr))
if (of_property_read_u32(port, "reg", &pn))
continue;
struct device_node *phy __free(device_node) =
@@ -897,11 +886,11 @@ static int rtmdio_map_ports(struct device *dev)
if (!phy)
continue;
if (addr >= ctrl->cfg->num_phys)
if (pn >= ctrl->cfg->num_phys)
return dev_err_probe(dev, -EINVAL, "%pfwP illegal port number\n",
of_fwnode_handle(port));
if (test_bit(addr, ctrl->valid_ports))
if (test_bit(pn, ctrl->valid_ports))
return dev_err_probe(dev, -EINVAL, "%pfwP duplicated port number\n",
of_fwnode_handle(port));
@@ -925,59 +914,46 @@ static int rtmdio_map_ports(struct device *dev)
if (of_device_is_compatible(phy, "ethernet-phy-ieee802.3-c45"))
ctrl->bus[smi_bus].is_c45 = true;
ctrl->port[addr].smi_bus = smi_bus;
ctrl->port[addr].smi_addr = smi_addr;
ctrl->port[addr].dn = of_node_get(phy);
__set_bit(addr, ctrl->valid_ports);
ctrl->port[pn].smi_bus = smi_bus;
ctrl->port[pn].smi_addr = smi_addr;
__set_bit(pn, ctrl->valid_ports);
}
return 0;
}
static int rtmdio_probe_one(struct device *dev, struct rtmdio_ctrl *ctrl)
static int rtmdio_probe_one(struct device *dev, struct rtmdio_ctrl *ctrl,
struct fwnode_handle *node)
{
struct rtmdio_chan *chan;
struct mii_bus *bus;
int ret, addr;
int smi_bus, ret;
ret = fwnode_property_read_u32(node, "reg", &smi_bus);
if (ret)
return ret;
bus = devm_mdiobus_alloc_size(dev, sizeof(*chan));
if (!bus)
return -ENOMEM;
ctrl->bus[smi_bus].mii_bus = bus;
chan = bus->priv;
chan->ctrl = ctrl;
chan->smi_bus = smi_bus;
bus->name = "Realtek MDIO bus";
bus->reset = rtmdio_reset;
bus->read = rtmdio_read;
bus->write = rtmdio_write;
bus->read_c45 = rtmdio_read_c45;
bus->write_c45 = rtmdio_write_c45;
bus->parent = dev;
bus->phy_mask = ~0;
snprintf(bus->id, MII_BUS_ID_SIZE, "realtek-mdio");
device_set_node(&bus->dev, of_fwnode_handle(dev->of_node));
snprintf(bus->id, MII_BUS_ID_SIZE, "realtek-mdio-%d", smi_bus);
ret = devm_mdiobus_register(dev, bus);
ret = devm_of_mdiobus_register(dev, bus, to_of_node(node));
if (ret)
return dev_err_probe(dev, ret, "cannot register MDIO bus\n");
for_each_phy(ctrl, addr) {
if (!ret)
ret = fwnode_mdiobus_register_phy(bus,
of_fwnode_handle(ctrl->port[addr].dn), addr);
of_node_put(ctrl->port[addr].dn);
}
if (ret)
return ret;
/*
* TODO: This polling setup needs to be relocated into rtmdio_probe(). It is a generic
* function and not bus specific. But this will require more rework of the data
* structures. For now it is easier to hand over the single bus that was just created.
*/
if (ctrl->cfg->setup_polling)
ctrl->cfg->setup_polling(bus);
return dev_err_probe(dev, ret, "cannot register MDIO %d bus\n", smi_bus);
return 0;
}
@@ -986,7 +962,7 @@ static int rtmdio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rtmdio_ctrl *ctrl;
int ret, addr;
int ret;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
@@ -1003,14 +979,22 @@ static int rtmdio_probe(struct platform_device *pdev)
return PTR_ERR(ctrl->map);
ret = rtmdio_map_ports(dev);
if (ret) {
for_each_phy(ctrl, addr)
of_node_put(ctrl->port[addr].dn);
if (ret)
return ret;
}
rtmdio_setup_smi_topology(ctrl);
return rtmdio_probe_one(dev, ctrl);
rtmdio_setup_smi_topology(ctrl);
ctrl->cfg->setup_ctrl(ctrl);
device_for_each_child_node_scoped(dev, child) {
ret = rtmdio_probe_one(dev, ctrl, child);
if (ret)
return ret;
}
if (ctrl->cfg->setup_polling)
ctrl->cfg->setup_polling(ctrl);
return 0;
}
static const struct rtmdio_config rtmdio_838x_cfg = {
@@ -1019,7 +1003,7 @@ static const struct rtmdio_config rtmdio_838x_cfg = {
.port_map_base = RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL,
.read_mmd_phy = rtmdio_838x_read_mmd_phy,
.read_phy = rtmdio_838x_read_phy,
.reset = rtmdio_838x_reset,
.setup_ctrl = rtmdio_838x_setup_ctrl,
.setup_polling = rtmdio_838x_setup_polling,
.write_mmd_phy = rtmdio_838x_write_mmd_phy,
.write_phy = rtmdio_838x_write_phy,
@@ -1030,7 +1014,7 @@ static const struct rtmdio_config rtmdio_839x_cfg = {
.raw_page = 8191,
.read_mmd_phy = rtmdio_839x_read_mmd_phy,
.read_phy = rtmdio_839x_read_phy,
.reset = rtmdio_839x_reset,
.setup_ctrl = rtmdio_839x_setup_ctrl,
.write_mmd_phy = rtmdio_839x_write_mmd_phy,
.write_phy = rtmdio_839x_write_phy,
};
@@ -1042,7 +1026,7 @@ static const struct rtmdio_config rtmdio_930x_cfg = {
.port_map_base = RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL,
.read_mmd_phy = rtmdio_930x_read_mmd_phy,
.read_phy = rtmdio_930x_read_phy,
.reset = rtmdio_930x_reset,
.setup_ctrl = rtmdio_930x_setup_ctrl,
.setup_polling = rtmdio_930x_setup_polling,
.write_mmd_phy = rtmdio_930x_write_mmd_phy,
.write_phy = rtmdio_930x_write_phy,
@@ -1055,7 +1039,7 @@ static const struct rtmdio_config rtmdio_931x_cfg = {
.port_map_base = RTMDIO_931X_SMI_PORT_ADDR_CTRL,
.read_mmd_phy = rtmdio_931x_read_mmd_phy,
.read_phy = rtmdio_931x_read_phy,
.reset = rtmdio_931x_reset,
.setup_ctrl = rtmdio_931x_setup_ctrl,
.setup_polling = rtmdio_931x_setup_polling,
.write_mmd_phy = rtmdio_931x_write_mmd_phy,
.write_phy = rtmdio_931x_write_phy,
target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c
+5 -8
View File
@@ -815,7 +815,7 @@ static int rtpcs_838x_sds_patch(struct rtpcs_serdes *sds,
default:
break;
}
return 0;
}
@@ -851,7 +851,7 @@ static int rtpcs_838x_setup_serdes(struct rtpcs_serdes *sds,
rtpcs_838x_sds_patch(sds, hw_mode);
rtpcs_838x_sds_reset(sds);
/* release reset */
rtpcs_sds_write(sds, 0, 3, 0x7106);
@@ -1282,7 +1282,7 @@ pll_setup:
/* RTL930X */
/*
/*
* RTL930X needs a special mapping from logic SerDes ID to physical SerDes ID,
* which takes the page into account. This applies to most of read/write calls.
*/
@@ -2814,10 +2814,6 @@ static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sd
apply_fn = is_xsgmii ? rtpcs_sds_apply_config_xsg : rtpcs_sds_apply_config;
/* USXGMII-QX broken, rely on bootloader setup */
if (hw_mode == RTPCS_SDS_MODE_USXGMII_10GQXGMII)
return 0;
if (hw_mode == RTPCS_SDS_MODE_QSGMII) {
if (sds->id >= 2)
return -ENOTSUPP;
@@ -2893,6 +2889,7 @@ static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sd
case RTPCS_SDS_MODE_XSGMII:
case RTPCS_SDS_MODE_USXGMII_10GSXGMII:
case RTPCS_SDS_MODE_USXGMII_10GQXGMII:
ret = apply_fn(sds, rtpcs_930x_sds_cfg_ana_10g,
ARRAY_SIZE(rtpcs_930x_sds_cfg_ana_10g));
if (ret < 0)
@@ -2903,7 +2900,7 @@ static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sd
if (ret < 0)
return ret;
if (hw_mode == RTPCS_SDS_MODE_USXGMII_10GSXGMII)
if (!is_xsgmii)
/* opcode 0x03: standard/generic USXGMII mode */
rtpcs_930x_sds_usxgmii_config(sds, true, 0x03, 0xa4, 0, 1, 0x1);
break;
target/linux/realtek/image/rt-loader/src/board.c
+1 -1
View File
@@ -98,7 +98,7 @@ found:
else
chip_version = ((cinfo >> 16) & 0x1f) - 1;
snprintf(buffer, len, "RTL%04X%c rev %c (%04x)", model_id,
snprintf(buffer, len, "RTL%04X%c rev %c (%04x)", model_id,
model_version ? model_version + 64 : 0, chip_version + 65, chip_id);
}
target/linux/realtek/patches-6.18/743-net-realtek-serdes-configuration.patch
+203
View File
@@ -0,0 +1,203 @@
--- a/drivers/net/phy/realtek/realtek_main.c
+++ b/drivers/net/phy/realtek/realtek_main.c
@@ -171,6 +171,41 @@
#define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4)
+#define RTL8224_VND1_SERDES_CMD 0x3f8
+#define RTL8224_VND1_SERDES_READ 0x3fc
+#define RTL8224_VND1_SERDES_WRITE 0x400
+#define RTL8224_SDS_CMD_READ BIT(15)
+#define RTL8224_SDS_CMD_WRITE (BIT(15) | BIT(14))
+
+#define RTL8224_VND1_SERDES_MODE 0x7b20
+#define RTL8224_VND1_SERDES_MODE_MASK GENMASK(4, 0)
+#define RTL8224_VND1_SERDES_MODE_OFF 0x1f
+#define RTL8224_VND1_SERDES_MODE_USXGMII 0x0d
+#define RTL8224_VND1_SERDES_SUBMODE_MASK GENMASK(14, 10)
+#define RTL8224_VND1_SERDES_SUBMODE_10G_QXGMII (0x2 << 10)
+
+#define RTL8224_SDS_AM_PAGE 0x6
+#define RTL8224_SDS_AM_PERIOD_REG 0x12
+
+#define RTL8224_SDS_AM_CFG0_REG 0x13
+#define RTL8224_SDS_AM_CFG1_REG 0x14
+#define RTL8224_SDS_AM_CFG2_REG 0x15
+#define RTL8224_SDS_AM_CFG3_REG 0x16
+#define RTL8224_SDS_AM_CFG4_REG 0x17
+#define RTL8224_SDS_AM_CFG5_REG 0x18
+
+#define RTL8224_SDS_NWAY_PAGE 0x7
+#define RTL8224_SDS_NWAY_OPCODE_REG 0x10
+#define RTL8224_SDS_NWAY_OPCODE_MASK GENMASK(7, 0)
+#define RTL8224_SDS_NWAY_AN_REG 0x11
+#define RTL8224_SDS_NWAY_AN_EN_MASK GENMASK(3, 0)
+
+#define RTL8224_SDS_REG0_TX_PAGE 0x2e
+#define RTL8224_SDS_REG0_TX_POST1_REG 0x6
+#define RTL8224_SDS_REG0_TX_REG 0x7
+#define RTL8224_SDS_REG0_TX_Z0_REG 0xb
+
+
#define RTL8221B_PHYCR1 0xa430
#define RTL8221B_PHYCR1_ALDPS_EN BIT(2)
#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12)
@@ -2034,6 +2069,147 @@ exit:
return ret;
}
+static int rtl8224_sds_read(struct phy_device *phydev, int page, u32 reg)
+{
+ int ret;
+ u32 val;
+ u32 cmd = RTL8224_SDS_CMD_READ | (reg << 7) | (page << 1);
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_CMD, cmd);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
+ RTL8224_VND1_SERDES_CMD, val,
+ !(val & BIT(15)), 500, 500000000,
+ false);
+ if (ret < 0)
+ return ret;
+
+ return phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_READ);
+}
+
+static int rtl8224_sds_write(struct phy_device *phydev, int page, int reg, u32 data)
+{
+ int ret;
+ u32 tmp;
+ u32 cmd = RTL8224_SDS_CMD_WRITE | (reg << 7) | (page << 1);
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_WRITE,
+ data);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_CMD, cmd);
+ if (ret < 0)
+ return ret;
+
+ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
+ RTL8224_VND1_SERDES_CMD, tmp,
+ !(tmp & BIT(15)), 500, 500000000,
+ false);
+}
+
+static int rtl8224_sds_modify(struct phy_device *phydev, int page, int reg, u32 mask, u32 data)
+{
+ int ret;
+ u32 val;
+
+ ret = rtl8224_sds_read(phydev, page, reg);
+ if (ret < 0)
+ return ret;
+
+ val = (u32)ret;
+ val = (val & ~mask) | (data & mask);
+
+ ret = rtl8224_sds_write(phydev, page, reg, val);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rtl8224_serdes_config(struct phy_device *phydev)
+{
+ if ((phydev->mdio.addr & 3) != 0)
+ return 0;
+
+ /* Turn SerDes OFF */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_MODE,
+ RTL8224_VND1_SERDES_MODE_MASK,
+ RTL8224_VND1_SERDES_MODE_OFF);
+
+ /* Use generic/standard-compliant AN mode */
+ rtl8224_sds_modify(phydev, RTL8224_SDS_NWAY_PAGE,
+ RTL8224_SDS_NWAY_OPCODE_REG,
+ RTL8224_SDS_NWAY_OPCODE_MASK, 0x0003);
+
+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
+ RTL8224_SDS_AM_PERIOD_REG, 0x00a4);
+
+ /* Set all AM markers to 0 */
+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
+ RTL8224_SDS_AM_CFG0_REG, 0);
+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
+ RTL8224_SDS_AM_CFG1_REG, 0);
+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
+ RTL8224_SDS_AM_CFG2_REG, 0);
+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
+ RTL8224_SDS_AM_CFG3_REG, 0);
+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
+ RTL8224_SDS_AM_CFG4_REG, 0);
+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
+ RTL8224_SDS_AM_CFG5_REG, 0);
+
+ /* Enable USXGMII autoneg on all 4 channels */
+ rtl8224_sds_modify(phydev, RTL8224_SDS_NWAY_PAGE,
+ RTL8224_SDS_NWAY_AN_REG,
+ RTL8224_SDS_NWAY_AN_EN_MASK, 0xf);
+
+ rtl8224_sds_modify(phydev, 0x06, 0x03, BIT(15), BIT(15));
+ rtl8224_sds_modify(phydev, 0x06, 0x1d, BIT(9), BIT(9));
+ rtl8224_sds_modify(phydev, 0x06, 0x1f, BIT(13), BIT(13));
+ rtl8224_sds_write(phydev, 0x21, 0x10, 0x4480);
+ rtl8224_sds_write(phydev, 0x21, 0x13, 0x0400);
+ rtl8224_sds_write(phydev, 0x21, 0x18, 0x6d02);
+ rtl8224_sds_write(phydev, 0x21, 0x1b, 0x424e);
+ rtl8224_sds_write(phydev, 0x21, 0x1d, 0x0002);
+ rtl8224_sds_write(phydev, 0x36, 0x1c, 0x1390);
+ rtl8224_sds_write(phydev, 0x2e, 0x04, 0x0080);
+
+ rtl8224_sds_write(phydev, RTL8224_SDS_REG0_TX_PAGE,
+ RTL8224_SDS_REG0_TX_POST1_REG, 0x0408);
+
+ rtl8224_sds_write(phydev, RTL8224_SDS_REG0_TX_PAGE,
+ RTL8224_SDS_REG0_TX_REG, 0x020d);
+
+ rtl8224_sds_write(phydev, 0x2e, 0x09, 0x0601);
+
+ rtl8224_sds_write(phydev, RTL8224_SDS_REG0_TX_PAGE,
+ RTL8224_SDS_REG0_TX_Z0_REG, 0x222c);
+
+ rtl8224_sds_write(phydev, 0x2e, 0x0c, 0xa217);
+ rtl8224_sds_write(phydev, 0x2e, 0x0d, 0xfe40);
+ rtl8224_sds_write(phydev, 0x2e, 0x15, 0xf5f1);
+ rtl8224_sds_write(phydev, 0x2e, 0x16, 0x0443);
+ rtl8224_sds_write(phydev, 0x2e, 0x1d, 0xabb0);
+
+ /* Turn SerDes ON in 10G_QXGMII mode */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_MODE,
+ RTL8224_VND1_SERDES_SUBMODE_MASK,
+ RTL8224_VND1_SERDES_SUBMODE_10G_QXGMII);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_MODE,
+ RTL8224_VND1_SERDES_MODE_MASK,
+ RTL8224_VND1_SERDES_MODE_USXGMII);
+
+ rtl8224_sds_modify(phydev, 0x20, 0x00, GENMASK(5, 4), 0x30);
+ rtl8224_sds_modify(phydev, 0x20, 0x00, GENMASK(5, 4), 0x10);
+ rtl8224_sds_modify(phydev, 0x20, 0x00, GENMASK(5, 4), 0x30);
+ rtl8224_sds_modify(phydev, 0x20, 0x00, GENMASK(5, 4), 0x00);
+
+ return 0;
+}
+
static int rtl8224_mdi_config_order(struct phy_device *phydev)
{
struct device_node *np = phydev->mdio.dev.of_node;
@@ -2088,6 +2264,10 @@ static int rtl8224_config_init(struct ph
{
int ret;
+ ret = rtl8224_serdes_config(phydev);
+ if (ret)
+ return ret;
+
ret = rtl8224_mdi_config_order(phydev);
if (ret)
return ret;
tools/cmake/Makefile
+2 -2
View File
@@ -7,7 +7,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=cmake
PKG_VERSION:=4.2.3
PKG_VERSION:=4.3.1
PKG_VERSION_MAJOR:=$(word 1,$(subst ., ,$(PKG_VERSION))).$(word 2,$(subst ., ,$(PKG_VERSION)))
PKG_RELEASE:=1
PKG_CPE_ID:=cpe:/a:kitware:cmake
@@ -15,7 +15,7 @@ PKG_CPE_ID:=cpe:/a:kitware:cmake
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/Kitware/CMake/releases/download/v$(PKG_VERSION)/ \
https://cmake.org/files/v$(PKG_VERSION_MAJOR)/
PKG_HASH:=7efaccde8c5a6b2968bad6ce0fe60e19b6e10701a12fce948c2bf79bac8a11e9
PKG_HASH:=0798f4be7a1a406a419ac32db90c2956936fecbf50db3057d7af47d69a2d7edb
HOST_BUILD_PARALLEL:=1
HOST_CONFIGURE_PARALLEL:=1
tools/cmake/patches/130-bootstrap_parallel_make_flag.patch
+1 -1
View File
@@ -1,6 +1,6 @@
--- a/bootstrap
+++ b/bootstrap
@@ -1521,7 +1521,10 @@ int main(){ printf("1%c", (char)0x0a); r
@@ -1522,7 +1522,10 @@ int main(){ printf("1%c", (char)0x0a); r
' > "test.c"
cmake_original_make_flags="${cmake_make_flags}"
if test "x${cmake_parallel_make}" != "x"; then
tools/cmake/patches/150-zstd-libarchive.patch
+1 -1
View File
@@ -1,6 +1,6 @@
--- a/Utilities/cmlibarchive/CMakeLists.txt
+++ b/Utilities/cmlibarchive/CMakeLists.txt
@@ -669,7 +669,7 @@ IF(ENABLE_ZSTD)
@@ -680,7 +680,7 @@ IF(ENABLE_ZSTD)
SET(ZSTD_FIND_QUIETLY TRUE)
ENDIF (ZSTD_INCLUDE_DIR)
tools/cmake/patches/160-disable_xcode_generator.patch
+2 -2
View File
@@ -1,6 +1,6 @@
--- a/Source/CMakeLists.txt
+++ b/Source/CMakeLists.txt
@@ -903,7 +903,7 @@ if(CMake_USE_XCOFF_PARSER)
@@ -923,7 +923,7 @@ if(CMake_USE_XCOFF_PARSER)
endif()
# Xcode only works on Apple
@@ -11,7 +11,7 @@
PRIVATE
--- a/Source/cmake.cxx
+++ b/Source/cmake.cxx
@@ -142,7 +142,7 @@
@@ -144,7 +144,7 @@
# endif
#endif