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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2026-05-27 16:23:52 +08:00
parent 67f4c6958c d22ceb8d24
commit 6efdfa7a1f
428 changed files with 1205 additions and 70271 deletions
Download Patch File Download Diff File Expand all files Collapse all files
package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq50xx
+1
View File
@@ -11,6 +11,7 @@ case "$board" in
cmcc,mr3000d-ci|\
cmcc,pz-l8|\
elecom,wrc-x3000gs2|\
elecom,wrc-x3000gst2|\
iodata,wn-dax3000gr|\
zyxel,scr50axe)
ubootenv_add_mtd "0:appsblenv" "0x0" "0x40000" "0x20000"
target/linux/airoha/patches-6.12/916-net-airoha-Implement-LRO-TCP-support.patch
+58 -66
View File
@@ -21,20 +21,21 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
#include <uapi/linux/ppp_defs.h>
#include "airoha_regs.h"
@@ -439,6 +440,47 @@ static void airoha_fe_crsn_qsel_init(str
@@ -439,6 +440,48 @@ static void airoha_fe_crsn_qsel_init(str
CDM_CRSN_QSEL_Q1));
}
+static void airoha_fe_lro_init_rx_queue(struct airoha_eth *eth, int qdma_id,
+ int lro_queue_index, int qid,
+ int nbuf, int buf_size)
+ int buf_size)
+{
+ int id = qdma_id + 1;
+
+ airoha_fe_rmw(eth, REG_CDM_LRO_LIMIT(id),
+ CDM_LRO_AGG_NUM_MASK | CDM_LRO_AGG_SIZE_MASK,
+ FIELD_PREP(CDM_LRO_AGG_NUM_MASK, nbuf) |
+ FIELD_PREP(CDM_LRO_AGG_SIZE_MASK, buf_size));
+ FIELD_PREP(CDM_LRO_AGG_SIZE_MASK, buf_size) |
+ FIELD_PREP(CDM_LRO_AGG_NUM_MASK,
+ AIROHA_RXQ_LRO_MAX_AGG_COUNT));
+ airoha_fe_rmw(eth, REG_CDM_LRO_AGE_TIME(id),
+ CDM_LRO_AGE_TIME_MASK | CDM_LRO_AGG_TIME_MASK,
+ FIELD_PREP(CDM_LRO_AGE_TIME_MASK,
@@ -51,11 +52,11 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+{
+ int i, id = qdma_id + 1;
+
+ airoha_fe_clear(eth, REG_CDM_LRO_EN(id), LRO_RXQ_EN_MASK);
+ airoha_fe_clear(eth, REG_CDM_LRO_LIMIT(id),
+ CDM_LRO_AGG_NUM_MASK | CDM_LRO_AGG_SIZE_MASK);
+ airoha_fe_clear(eth, REG_CDM_LRO_AGE_TIME(id),
+ CDM_LRO_AGE_TIME_MASK | CDM_LRO_AGG_TIME_MASK);
+ airoha_fe_clear(eth, REG_CDM_LRO_EN(id), LRO_RXQ_EN_MASK);
+ for (i = 0; i < AIROHA_MAX_NUM_LRO_QUEUES; i++)
+ airoha_fe_clear(eth, REG_CDM_LRO_RXQ(id, i), LRO_RXQ_MASK(i));
+}
@@ -69,49 +70,57 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static int airoha_fe_init(struct airoha_eth *eth)
{
airoha_fe_maccr_init(eth);
@@ -603,9 +645,78 @@ static int airoha_qdma_get_gdm_port(stru
@@ -603,6 +646,85 @@ static int airoha_qdma_get_gdm_port(stru
return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port;
}
+static int airoha_qdma_lro_rx_process(struct airoha_queue *q,
+ struct airoha_qdma_desc *desc)
+{
+ u32 desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
+ u32 msg1 = le32_to_cpu(READ_ONCE(desc->msg1));
+ u32 msg2 = le32_to_cpu(READ_ONCE(desc->msg2));
+ u32 msg3 = le32_to_cpu(READ_ONCE(desc->msg3));
+ bool ipv4 = FIELD_GET(QDMA_ETH_RXMSG_IP4_MASK, msg1);
+ bool ipv6 = FIELD_GET(QDMA_ETH_RXMSG_IP6_MASK, msg1);
+ struct sk_buff *skb = q->skb;
+ u32 th_off, tcp_ack_seq;
+ u32 len, th_off, tcp_ack_seq;
+ u16 tcp_win, l2_len;
+ struct tcphdr *th;
+ bool ipv4, ipv6;
+
+ if (FIELD_GET(QDMA_ETH_RXMSG_AGG_COUNT_MASK, msg2) <= 1)
+ return 0;
+
+ ipv4 = FIELD_GET(QDMA_ETH_RXMSG_IP4_MASK, msg1);
+ ipv6 = FIELD_GET(QDMA_ETH_RXMSG_IP6_MASK, msg1);
+ if (!ipv4 && !ipv6)
+ return -EOPNOTSUPP;
+
+ l2_len = FIELD_GET(QDMA_ETH_RXMSG_L2_LEN_MASK, msg2);
+ len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
+ if (ipv4) {
+ u16 agg_len = FIELD_GET(QDMA_ETH_RXMSG_AGG_LEN_MASK, msg3);
+ struct iphdr *iph = (struct iphdr *)(skb->data + l2_len);
+ struct iphdr *iph;
+
+ if (!pskb_may_pull(skb, l2_len + sizeof(*iph)))
+ return -EINVAL;
+
+ iph = (struct iphdr *)(skb->data + l2_len);
+ if (iph->protocol != IPPROTO_TCP)
+ return -EOPNOTSUPP;
+
+ iph->tot_len = cpu_to_be16(agg_len);
+ iph->tot_len = cpu_to_be16(len - l2_len);
+ iph->check = 0;
+ iph->check = ip_fast_csum((void *)iph, iph->ihl);
+ th_off = l2_len + (iph->ihl << 2);
+ } else {
+ struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + l2_len);
+ u32 len, desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
+ struct ipv6hdr *ip6h;
+
+ if (!pskb_may_pull(skb, l2_len + sizeof(*ip6h)))
+ return -EINVAL;
+
+ ip6h = (struct ipv6hdr *)(skb->data + l2_len);
+ if (ip6h->nexthdr != NEXTHDR_TCP)
+ return -EOPNOTSUPP;
+
+ len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
+ ip6h->payload_len = cpu_to_be16(len - l2_len - sizeof(*ip6h));
+ th_off = l2_len + sizeof(*ip6h);
+ }
@@ -119,6 +128,9 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+ tcp_win = FIELD_GET(QDMA_ETH_RXMSG_TCP_WIN_MASK, msg3);
+ tcp_ack_seq = le32_to_cpu(READ_ONCE(desc->data));
+
+ if (!pskb_may_pull(skb, th_off + sizeof(*th)))
+ return -EINVAL;
+
+ th = (struct tcphdr *)(skb->data + th_off);
+ th->ack_seq = cpu_to_be32(tcp_ack_seq);
+ th->window = cpu_to_be16(tcp_win);
@@ -144,82 +156,57 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
{
enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool);
+ bool lro_q = airoha_qdma_is_lro_queue(q);
struct airoha_qdma *qdma = q->qdma;
struct airoha_eth *eth = qdma->eth;
int qid = q - &qdma->q_rx[0];
@@ -652,9 +763,14 @@ static int airoha_qdma_rx_process(struct
@@ -650,11 +772,15 @@ static int airoha_qdma_rx_process(struct
skb_reserve(q->skb, AIROHA_RX_HEADROOM);
__skb_put(q->skb, len);
skb_mark_for_recycle(q->skb);
- skb_mark_for_recycle(q->skb);
q->skb->dev = port->dev;
- q->skb->protocol = eth_type_trans(q->skb, port->dev);
q->skb->ip_summed = CHECKSUM_UNNECESSARY;
skb_record_rx_queue(q->skb, qid);
+
+ if (lro_q && (port->dev->features & NETIF_F_LRO) &&
+ airoha_qdma_lro_rx_process(q, desc) < 0)
+ if (airoha_qdma_lro_rx_process(q, desc) < 0)
+ goto free_frag;
+
+ q->skb->protocol = eth_type_trans(q->skb, port->dev);
+ skb_mark_for_recycle(q->skb);
} else { /* scattered frame */
struct skb_shared_info *shinfo = skb_shinfo(q->skb);
int nr_frags = shinfo->nr_frags;
@@ -743,23 +859,19 @@ static int airoha_qdma_rx_napi_poll(stru
@@ -743,12 +869,13 @@ static int airoha_qdma_rx_napi_poll(stru
static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
struct airoha_qdma *qdma, int ndesc)
{
- const struct page_pool_params pp_params = {
+ int pp_order = airoha_qdma_is_lro_queue(q) ? AIROHA_LRO_PAGE_ORDER : 0;
const struct page_pool_params pp_params = {
- .order = 0,
- .pool_size = 256,
+ struct page_pool_params pp_params = {
+ .order = pp_order,
.pool_size = 256,
.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
.dma_dir = DMA_FROM_DEVICE,
- .max_len = PAGE_SIZE,
+ .max_len = PAGE_SIZE << pp_order,
.nid = NUMA_NO_NODE,
.dev = qdma->eth->dev,
.napi = &q->napi,
};
+ int pp_order, qid = q - &qdma->q_rx[0], thr;
struct airoha_eth *eth = qdma->eth;
- int qid = q - &qdma->q_rx[0], thr;
@@ -757,7 +884,8 @@ static int airoha_qdma_init_rx_queue(str
int qid = q - &qdma->q_rx[0], thr;
dma_addr_t dma_addr;
+ bool lro_q;
- q->buf_size = PAGE_SIZE / 2;
+ q->buf_size = airoha_qdma_is_lro_queue(q) ? pp_params.max_len
+ : pp_params.max_len / 2;
q->qdma = qdma;
-
q->entry = devm_kzalloc(eth->dev, ndesc * sizeof(*q->entry),
GFP_KERNEL);
if (!q->entry)
@@ -770,6 +882,12 @@ static int airoha_qdma_init_rx_queue(str
if (!q->desc)
return -ENOMEM;
+ lro_q = airoha_qdma_is_lro_queue(q);
+ pp_order = lro_q ? AIROHA_LRO_PAGE_ORDER : 0;
+ pp_params.order = pp_order;
+ pp_params.pool_size = 256 >> pp_order;
+ pp_params.max_len = PAGE_SIZE << pp_order;
+
q->page_pool = page_pool_create(&pp_params);
if (IS_ERR(q->page_pool)) {
int err = PTR_ERR(q->page_pool);
@@ -778,6 +896,7 @@ static int airoha_qdma_init_rx_queue(str
return err;
}
+ q->buf_size = pp_params.max_len / (2 * (1 + lro_q));
q->ndesc = ndesc;
netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll);
@@ -2034,6 +2153,64 @@ int airoha_get_fe_port(struct airoha_gdm
@@ -2034,6 +2162,67 @@ int airoha_get_fe_port(struct airoha_gdm
}
}
+static int airoha_dev_set_features(struct net_device *dev,
+ netdev_features_t features)
+{
+
+ netdev_features_t diff = dev->features ^ features;
+ struct airoha_gdm_port *port = netdev_priv(dev);
+ struct airoha_qdma *qdma = port->qdma;
@@ -230,6 +217,9 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+ if (!(diff & NETIF_F_LRO))
+ return 0;
+
+ if (netif_running(dev))
+ return -EBUSY;
+
+ /* reset LRO configuration */
+ if (features & NETIF_F_LRO) {
+ int lro_queue_index = 0;
@@ -239,6 +229,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+
+ for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
+ struct airoha_queue *q = &qdma->q_rx[i];
+ u32 size;
+
+ if (!q->ndesc)
+ continue;
@@ -246,10 +237,10 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+ if (!airoha_qdma_is_lro_queue(q))
+ continue;
+
+ size = SKB_WITH_OVERHEAD(AIROHA_RX_LEN(q->buf_size));
+ size = min_t(u32, size, CDM_LRO_AGG_SIZE_MASK);
+ airoha_fe_lro_init_rx_queue(eth, qdma_id,
+ lro_queue_index, i,
+ q->page_pool->p.pool_size,
+ q->buf_size);
+ lro_queue_index, i, size);
+ lro_queue_index++;
+ }
+ } else {
@@ -277,7 +268,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
struct net_device *dev)
{
@@ -2933,6 +3110,7 @@ static const struct net_device_ops airoh
@@ -2933,6 +3122,7 @@ static const struct net_device_ops airoh
.ndo_stop = airoha_dev_stop,
.ndo_change_mtu = airoha_dev_change_mtu,
.ndo_select_queue = airoha_dev_select_queue,
@@ -285,7 +276,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.ndo_start_xmit = airoha_dev_xmit,
.ndo_get_stats64 = airoha_dev_get_stats64,
.ndo_set_mac_address = airoha_dev_set_macaddr,
@@ -3150,12 +3328,9 @@ static int airoha_alloc_gdm_port(struct
@@ -3150,12 +3340,9 @@ static int airoha_alloc_gdm_port(struct
dev->ethtool_ops = &airoha_ethtool_ops;
dev->max_mtu = AIROHA_MAX_MTU;
dev->watchdog_timeo = 5 * HZ;
@@ -303,13 +294,14 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -43,6 +43,17 @@
@@ -43,6 +43,18 @@
(_n) == 15 ? 128 : \
(_n) == 0 ? 1024 : 16)
+#define AIROHA_LRO_PAGE_ORDER 2
+#define AIROHA_MAX_NUM_LRO_QUEUES 8
+#define AIROHA_RXQ_LRO_EN_MASK 0xff000
+#define AIROHA_RXQ_LRO_EN_MASK 0xff000000
+#define AIROHA_RXQ_LRO_MAX_AGG_COUNT 64
+#define AIROHA_RXQ_LRO_MAX_AGG_TIME 100
+#define AIROHA_RXQ_LRO_MAX_AGE_TIME 2000 /* 1ms */
+
@@ -321,7 +313,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
#define PSE_RSV_PAGES 128
#define PSE_QUEUE_RSV_PAGES 64
@@ -666,6 +677,18 @@ static inline bool airoha_is_7583(struct
@@ -666,6 +678,18 @@ static inline bool airoha_is_7583(struct
return eth->soc->version == 0x7583;
}
target/linux/airoha/patches-6.12/920-01-net-airoha-Introduce-airoha_gdm_dev-struct.patch
+52 -46
View File
@@ -25,7 +25,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -727,6 +727,7 @@ static int airoha_qdma_rx_process(struct
@@ -738,6 +738,7 @@ static int airoha_qdma_rx_process(struct
struct airoha_qdma_desc *desc = &q->desc[q->tail];
u32 hash, reason, msg1, desc_ctrl;
struct airoha_gdm_port *port;
@@ -33,7 +33,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
int data_len, len, p;
struct page *page;
@@ -753,6 +754,10 @@ static int airoha_qdma_rx_process(struct
@@ -764,6 +765,10 @@ static int airoha_qdma_rx_process(struct
goto free_frag;
port = eth->ports[p];
@@ -44,26 +44,24 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (!q->skb) { /* first buffer */
q->skb = napi_build_skb(e->buf - AIROHA_RX_HEADROOM,
q->buf_size);
@@ -762,15 +767,15 @@ static int airoha_qdma_rx_process(struct
@@ -772,14 +777,14 @@ static int airoha_qdma_rx_process(struct
skb_reserve(q->skb, AIROHA_RX_HEADROOM);
__skb_put(q->skb, len);
skb_mark_for_recycle(q->skb);
- q->skb->dev = port->dev;
+ q->skb->dev = netdev;
q->skb->ip_summed = CHECKSUM_UNNECESSARY;
skb_record_rx_queue(q->skb, qid);
- if (lro_q && (port->dev->features & NETIF_F_LRO) &&
+ if (lro_q && (netdev->features & NETIF_F_LRO) &&
airoha_qdma_lro_rx_process(q, desc) < 0)
if (airoha_qdma_lro_rx_process(q, desc) < 0)
goto free_frag;
- q->skb->protocol = eth_type_trans(q->skb, port->dev);
+ q->skb->protocol = eth_type_trans(q->skb, netdev);
skb_mark_for_recycle(q->skb);
} else { /* scattered frame */
struct skb_shared_info *shinfo = skb_shinfo(q->skb);
int nr_frags = shinfo->nr_frags;
@@ -786,7 +791,7 @@ static int airoha_qdma_rx_process(struct
@@ -796,7 +801,7 @@ static int airoha_qdma_rx_process(struct
if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl))
continue;
@@ -72,7 +70,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
/* PPE module requires untagged packets to work
* properly and it provides DSA port index via the
* DMA descriptor. Report DSA tag to the DSA stack
@@ -983,6 +988,7 @@ static void airoha_qdma_wake_netdev_txqs
@@ -992,6 +997,7 @@ static void airoha_qdma_wake_netdev_txqs
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
@@ -80,7 +78,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
int j;
if (!port)
@@ -991,11 +997,12 @@ static void airoha_qdma_wake_netdev_txqs
@@ -1000,11 +1006,12 @@ static void airoha_qdma_wake_netdev_txqs
if (port->qdma != qdma)
continue;
@@ -95,7 +93,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
}
q->txq_stopped = false;
@@ -1839,33 +1846,34 @@ static void airoha_update_hw_stats(struc
@@ -1848,33 +1855,34 @@ static void airoha_update_hw_stats(struc
spin_unlock(&port->stats.lock);
}
@@ -138,7 +136,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
GDM_STAG_EN_MASK);
else
@@ -1893,16 +1901,17 @@ static int airoha_dev_open(struct net_de
@@ -1902,16 +1910,17 @@ static int airoha_dev_open(struct net_de
return 0;
}
@@ -161,7 +159,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id),
FE_PSE_PORT_DROP);
@@ -1922,24 +1931,25 @@ static int airoha_dev_stop(struct net_de
@@ -1931,24 +1940,25 @@ static int airoha_dev_stop(struct net_de
#if defined(CONFIG_PCS_AIROHA)
if (airhoa_is_phy_external(port)) {
@@ -193,7 +191,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
return 0;
}
@@ -2005,16 +2015,17 @@ static int airoha_set_gdm2_loopback(stru
@@ -2014,16 +2024,17 @@ static int airoha_set_gdm2_loopback(stru
return 0;
}
@@ -216,7 +214,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
switch (port->id) {
case AIROHA_GDM3_IDX:
@@ -2039,10 +2050,11 @@ static int airoha_dev_init(struct net_de
@@ -2048,10 +2059,11 @@ static int airoha_dev_init(struct net_de
return 0;
}
@@ -230,7 +228,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
unsigned int start;
airoha_update_hw_stats(port);
@@ -2061,36 +2073,39 @@ static void airoha_dev_get_stats64(struc
@@ -2070,36 +2082,39 @@ static void airoha_dev_get_stats64(struc
} while (u64_stats_fetch_retry(&port->stats.syncp, start));
}
@@ -277,7 +275,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev)
@@ -2153,12 +2168,13 @@ int airoha_get_fe_port(struct airoha_gdm
@@ -2162,11 +2177,12 @@ int airoha_get_fe_port(struct airoha_gdm
}
}
@@ -285,7 +283,6 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+static int airoha_dev_set_features(struct net_device *netdev,
netdev_features_t features)
{
- netdev_features_t diff = dev->features ^ features;
- struct airoha_gdm_port *port = netdev_priv(dev);
+ netdev_features_t diff = netdev->features ^ features;
@@ -294,7 +291,16 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_qdma *qdma = port->qdma;
struct airoha_eth *eth = qdma->eth;
int qdma_id = qdma - &eth->qdma[0];
@@ -2192,6 +2208,7 @@ static int airoha_dev_set_features(struc
@@ -2175,7 +2191,7 @@ static int airoha_dev_set_features(struc
if (!(diff & NETIF_F_LRO))
return 0;
- if (netif_running(dev))
+ if (netif_running(netdev))
return -EBUSY;
/* reset LRO configuration */
@@ -2204,6 +2220,7 @@ static int airoha_dev_set_features(struc
} else {
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *p = eth->ports[i];
@@ -302,7 +308,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (!p)
continue;
@@ -2199,10 +2216,11 @@ static int airoha_dev_set_features(struc
@@ -2211,10 +2228,11 @@ static int airoha_dev_set_features(struc
if (p->qdma != qdma)
continue;
@@ -316,7 +322,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
return 0;
}
airoha_fe_lro_disable(eth, qdma_id);
@@ -2212,9 +2230,10 @@ static int airoha_dev_set_features(struc
@@ -2224,9 +2242,10 @@ static int airoha_dev_set_features(struc
}
static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
@@ -329,7 +335,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_qdma *qdma = port->qdma;
u32 nr_frags, tag, msg0, msg1, len;
struct airoha_queue_entry *e;
@@ -2227,7 +2246,7 @@ static netdev_tx_t airoha_dev_xmit(struc
@@ -2239,7 +2258,7 @@ static netdev_tx_t airoha_dev_xmit(struc
u8 fport;
qid = airoha_qdma_get_txq(qdma, skb_get_queue_mapping(skb));
@@ -338,7 +344,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK,
qid / AIROHA_NUM_QOS_QUEUES) |
@@ -2263,7 +2282,7 @@ static netdev_tx_t airoha_dev_xmit(struc
@@ -2275,7 +2294,7 @@ static netdev_tx_t airoha_dev_xmit(struc
spin_lock_bh(&q->lock);
@@ -347,7 +353,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
nr_frags = 1 + skb_shinfo(skb)->nr_frags;
if (q->queued + nr_frags >= q->ndesc) {
@@ -2287,9 +2306,9 @@ static netdev_tx_t airoha_dev_xmit(struc
@@ -2299,9 +2318,9 @@ static netdev_tx_t airoha_dev_xmit(struc
dma_addr_t addr;
u32 val;
@@ -359,7 +365,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
goto error_unmap;
list_move_tail(&e->list, &tx_list);
@@ -2338,7 +2357,7 @@ static netdev_tx_t airoha_dev_xmit(struc
@@ -2350,7 +2369,7 @@ static netdev_tx_t airoha_dev_xmit(struc
error_unmap:
list_for_each_entry(e, &tx_list, list) {
@@ -368,7 +374,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
DMA_TO_DEVICE);
e->dma_addr = 0;
}
@@ -2347,25 +2366,27 @@ error_unmap:
@@ -2359,25 +2378,27 @@ error_unmap:
spin_unlock_bh(&q->lock);
error:
dev_kfree_skb_any(skb);
@@ -401,7 +407,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
unsigned int start;
airoha_update_hw_stats(port);
@@ -2393,11 +2414,12 @@ static const struct ethtool_rmon_hist_ra
@@ -2405,11 +2426,12 @@ static const struct ethtool_rmon_hist_ra
};
static void
@@ -416,7 +422,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_hw_stats *hw_stats = &port->stats;
unsigned int start;
@@ -2422,11 +2444,12 @@ airoha_ethtool_get_rmon_stats(struct net
@@ -2434,11 +2456,12 @@ airoha_ethtool_get_rmon_stats(struct net
} while (u64_stats_fetch_retry(&port->stats.syncp, start));
}
@@ -431,7 +437,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
int i;
for (i = 0; i < AIROHA_NUM_TX_RING; i++)
@@ -2511,10 +2534,12 @@ static int airoha_qdma_set_tx_ets_sched(
@@ -2523,10 +2546,12 @@ static int airoha_qdma_set_tx_ets_sched(
ARRAY_SIZE(w));
}
@@ -446,7 +452,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u64 cpu_tx_packets = airoha_qdma_rr(port->qdma,
REG_CNTR_VAL(channel << 1));
u64 fwd_tx_packets = airoha_qdma_rr(port->qdma,
@@ -2776,11 +2801,12 @@ static int airoha_qdma_set_trtcm_token_b
@@ -2788,11 +2813,12 @@ static int airoha_qdma_set_trtcm_token_b
mode, val);
}
@@ -461,7 +467,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
int i, err;
for (i = 0; i <= TRTCM_PEAK_MODE; i++) {
@@ -2800,20 +2826,22 @@ static int airoha_qdma_set_tx_rate_limit
@@ -2812,20 +2838,22 @@ static int airoha_qdma_set_tx_rate_limit
return 0;
}
@@ -488,7 +494,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (err) {
NL_SET_ERR_MSG_MOD(opt->extack,
"failed configuring htb offload");
@@ -2823,9 +2851,10 @@ static int airoha_tc_htb_alloc_leaf_queu
@@ -2835,9 +2863,10 @@ static int airoha_tc_htb_alloc_leaf_queu
if (opt->command == TC_HTB_NODE_MODIFY)
return 0;
@@ -501,7 +507,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
NL_SET_ERR_MSG_MOD(opt->extack,
"failed setting real_num_tx_queues");
return err;
@@ -2915,11 +2944,12 @@ static int airoha_tc_matchall_act_valida
@@ -2927,11 +2956,12 @@ static int airoha_tc_matchall_act_valida
return 0;
}
@@ -516,7 +522,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u32 rate = 0, bucket_size = 0;
switch (f->command) {
@@ -2954,18 +2984,19 @@ static int airoha_dev_tc_matchall(struct
@@ -2966,18 +2996,19 @@ static int airoha_dev_tc_matchall(struct
static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type,
void *type_data, void *cb_priv)
{
@@ -540,7 +546,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
default:
return -EOPNOTSUPP;
}
@@ -3012,47 +3043,51 @@ static int airoha_dev_setup_tc_block(str
@@ -3024,47 +3055,51 @@ static int airoha_dev_setup_tc_block(str
}
}
@@ -604,7 +610,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (!test_bit(channel, port->qos_sq_bmap)) {
NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
@@ -3088,8 +3123,8 @@ static int airoha_tc_setup_qdisc_htb(str
@@ -3100,8 +3135,8 @@ static int airoha_tc_setup_qdisc_htb(str
return 0;
}
@@ -615,7 +621,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
{
switch (type) {
case TC_SETUP_QDISC_ETS:
@@ -3161,13 +3196,18 @@ static void airoha_metadata_dst_free(str
@@ -3173,13 +3208,18 @@ static void airoha_metadata_dst_free(str
}
}
@@ -637,7 +643,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
return true;
}
@@ -3179,8 +3219,9 @@ static void airoha_mac_link_up(struct ph
@@ -3191,8 +3231,9 @@ static void airoha_mac_link_up(struct ph
unsigned int mode, phy_interface_t interface,
int speed, int duplex, bool tx_pause, bool rx_pause)
{
@@ -649,7 +655,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_qdma *qdma = port->qdma;
struct airoha_eth *eth = qdma->eth;
u32 frag_size_tx, frag_size_rx;
@@ -3236,65 +3277,122 @@ static int airoha_fill_available_pcs(str
@@ -3248,65 +3289,122 @@ static int airoha_fill_available_pcs(str
&num_available_pcs);
}
@@ -794,7 +800,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
int err, p;
u32 id;
@@ -3316,58 +3414,22 @@ static int airoha_alloc_gdm_port(struct
@@ -3328,58 +3426,22 @@ static int airoha_alloc_gdm_port(struct
return -EINVAL;
}
@@ -859,7 +865,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
static int airoha_register_gdm_devices(struct airoha_eth *eth)
@@ -3381,7 +3443,7 @@ static int airoha_register_gdm_devices(s
@@ -3393,7 +3455,7 @@ static int airoha_register_gdm_devices(s
if (!port)
continue;
@@ -868,7 +874,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (err)
return err;
}
@@ -3490,16 +3552,18 @@ error_napi_stop:
@@ -3502,16 +3564,18 @@ error_napi_stop:
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
@@ -890,7 +896,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
airoha_metadata_dst_free(port);
}
@@ -3521,15 +3585,19 @@ static void airoha_remove(struct platfor
@@ -3533,15 +3597,19 @@ static void airoha_remove(struct platfor
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
@@ -914,7 +920,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_hw_cleanup(eth);
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -546,17 +546,22 @@ struct airoha_qdma {
@@ -547,17 +547,22 @@ struct airoha_qdma {
struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
};
@@ -942,7 +948,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_hw_stats stats;
@@ -690,8 +695,8 @@ static inline bool airoha_qdma_is_lro_qu
@@ -691,8 +696,8 @@ static inline bool airoha_qdma_is_lro_qu
}
int airoha_get_fe_port(struct airoha_gdm_port *port);
target/linux/airoha/patches-6.12/920-02-net-airoha-Move-airoha_qdma-pointer-in-airoha_gdm_de.patch
+33 -33
View File
@@ -60,7 +60,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u32 vip_port;
vip_port = eth->soc->ops.get_vip_port(port, port->nbq);
@@ -994,10 +995,13 @@ static void airoha_qdma_wake_netdev_txqs
@@ -1003,10 +1004,13 @@ static void airoha_qdma_wake_netdev_txqs
if (!port)
continue;
@@ -76,7 +76,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
for (j = 0; j < dev->dev->num_tx_queues; j++) {
if (airoha_qdma_get_txq(qdma, j) != qid)
continue;
@@ -1702,9 +1706,10 @@ static void airoha_qdma_stop_napi(struct
@@ -1711,9 +1715,10 @@ static void airoha_qdma_stop_napi(struct
}
}
@@ -89,7 +89,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u32 val, i = 0;
spin_lock(&port->stats.lock);
@@ -1851,7 +1856,7 @@ static int airoha_dev_open(struct net_de
@@ -1860,7 +1865,7 @@ static int airoha_dev_open(struct net_de
int err, len = ETH_HLEN + netdev->mtu + ETH_FCS_LEN;
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
@@ -98,7 +98,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u32 pse_port = FE_PSE_PORT_PPE1;
#if defined(CONFIG_PCS_AIROHA)
@@ -1868,7 +1873,7 @@ static int airoha_dev_open(struct net_de
@@ -1877,7 +1882,7 @@ static int airoha_dev_open(struct net_de
#endif
netif_tx_start_all_queues(netdev);
@@ -107,7 +107,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (err)
return err;
@@ -1905,11 +1910,11 @@ static int airoha_dev_stop(struct net_de
@@ -1914,11 +1919,11 @@ static int airoha_dev_stop(struct net_de
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
@@ -121,7 +121,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
for (i = 0; i < netdev->num_tx_queues; i++)
netdev_tx_reset_subqueue(netdev, i);
@@ -1942,21 +1947,21 @@ static int airoha_dev_stop(struct net_de
@@ -1951,21 +1956,21 @@ static int airoha_dev_stop(struct net_de
static int airoha_dev_set_macaddr(struct net_device *netdev, void *p)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -147,7 +147,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u32 val, pse_port, chan;
int i, src_port;
@@ -2003,7 +2008,7 @@ static int airoha_set_gdm2_loopback(stru
@@ -2012,7 +2017,7 @@ static int airoha_set_gdm2_loopback(stru
__field_prep(SP_CPORT_MASK(val), FE_PSE_PORT_CDM2));
for (i = 0; i < eth->soc->num_ppe; i++)
@@ -156,7 +156,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (port->id == AIROHA_GDM4_IDX && airoha_is_7581(eth)) {
u32 mask = FC_ID_OF_SRC_PORT_MASK(port->nbq);
@@ -2023,9 +2028,9 @@ static int airoha_dev_init(struct net_de
@@ -2032,9 +2037,9 @@ static int airoha_dev_init(struct net_de
int i;
/* QDMA0 is used for lan ports while QDMA1 is used for WAN ports */
@@ -169,7 +169,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
switch (port->id) {
case AIROHA_GDM3_IDX:
@@ -2034,7 +2039,7 @@ static int airoha_dev_init(struct net_de
@@ -2043,7 +2048,7 @@ static int airoha_dev_init(struct net_de
if (!eth->ports[1]) {
int err;
@@ -178,7 +178,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (err)
return err;
}
@@ -2044,8 +2049,7 @@ static int airoha_dev_init(struct net_de
@@ -2053,8 +2058,7 @@ static int airoha_dev_init(struct net_de
}
for (i = 0; i < eth->soc->num_ppe; i++)
@@ -188,7 +188,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
return 0;
}
@@ -2057,7 +2061,7 @@ static void airoha_dev_get_stats64(struc
@@ -2066,7 +2070,7 @@ static void airoha_dev_get_stats64(struc
struct airoha_gdm_port *port = dev->port;
unsigned int start;
@@ -197,7 +197,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
do {
start = u64_stats_fetch_begin(&port->stats.syncp);
storage->rx_packets = port->stats.rx_ok_pkts;
@@ -2077,8 +2081,8 @@ static int airoha_dev_change_mtu(struct
@@ -2086,8 +2090,8 @@ static int airoha_dev_change_mtu(struct
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
@@ -207,7 +207,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id),
GDM_LONG_LEN_MASK,
@@ -2152,10 +2156,10 @@ static u32 airoha_get_dsa_tag(struct sk_
@@ -2161,10 +2165,10 @@ static u32 airoha_get_dsa_tag(struct sk_
#endif
}
@@ -221,8 +221,8 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
switch (eth->soc->version) {
case 0x7583:
@@ -2174,8 +2178,7 @@ static int airoha_dev_set_features(struc
@@ -2182,8 +2186,7 @@ static int airoha_dev_set_features(struc
{
netdev_features_t diff = netdev->features ^ features;
struct airoha_gdm_dev *dev = netdev_priv(netdev);
- struct airoha_gdm_port *port = dev->port;
@@ -231,7 +231,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_eth *eth = qdma->eth;
int qdma_id = qdma - &eth->qdma[0];
int i;
@@ -2213,10 +2216,10 @@ static int airoha_dev_set_features(struc
@@ -2225,10 +2228,10 @@ static int airoha_dev_set_features(struc
if (!p)
continue;
@@ -244,7 +244,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (d->dev == netdev)
continue;
@@ -2233,8 +2236,7 @@ static netdev_tx_t airoha_dev_xmit(struc
@@ -2245,8 +2248,7 @@ static netdev_tx_t airoha_dev_xmit(struc
struct net_device *netdev)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -254,7 +254,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u32 nr_frags, tag, msg0, msg1, len;
struct airoha_queue_entry *e;
struct netdev_queue *txq;
@@ -2272,7 +2274,7 @@ static netdev_tx_t airoha_dev_xmit(struc
@@ -2284,7 +2286,7 @@ static netdev_tx_t airoha_dev_xmit(struc
}
}
@@ -263,7 +263,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) |
FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f);
@@ -2375,8 +2377,7 @@ static void airoha_ethtool_get_drvinfo(s
@@ -2387,8 +2389,7 @@ static void airoha_ethtool_get_drvinfo(s
struct ethtool_drvinfo *info)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -273,7 +273,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver));
strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info));
@@ -2389,7 +2390,7 @@ static void airoha_ethtool_get_mac_stats
@@ -2401,7 +2402,7 @@ static void airoha_ethtool_get_mac_stats
struct airoha_gdm_port *port = dev->port;
unsigned int start;
@@ -282,7 +282,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
do {
start = u64_stats_fetch_begin(&port->stats.syncp);
stats->FramesTransmittedOK = port->stats.tx_ok_pkts;
@@ -2429,7 +2430,7 @@ airoha_ethtool_get_rmon_stats(struct net
@@ -2441,7 +2442,7 @@ airoha_ethtool_get_rmon_stats(struct net
ARRAY_SIZE(hw_stats->rx_len) + 1);
*ranges = airoha_ethtool_rmon_ranges;
@@ -291,7 +291,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
do {
int i;
@@ -2449,18 +2450,17 @@ static int airoha_qdma_set_chan_tx_sched
@@ -2461,18 +2462,17 @@ static int airoha_qdma_set_chan_tx_sched
const u16 *weights, u8 n_weights)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -312,7 +312,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
TWRR_RW_CMD_MASK |
FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) |
FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) |
@@ -2468,13 +2468,12 @@ static int airoha_qdma_set_chan_tx_sched
@@ -2480,13 +2480,12 @@ static int airoha_qdma_set_chan_tx_sched
err = read_poll_timeout(airoha_qdma_rr, status,
status & TWRR_RW_CMD_DONE,
USEC_PER_MSEC, 10 * USEC_PER_MSEC,
@@ -328,7 +328,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
CHAN_QOS_MODE_MASK(channel),
__field_prep(CHAN_QOS_MODE_MASK(channel), mode));
@@ -2540,9 +2539,9 @@ static int airoha_qdma_get_tx_ets_stats(
@@ -2552,9 +2551,9 @@ static int airoha_qdma_get_tx_ets_stats(
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
@@ -340,7 +340,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
REG_CNTR_VAL((channel << 1) + 1));
u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) +
(fwd_tx_packets - port->fwd_tx_packets);
@@ -2806,17 +2805,16 @@ static int airoha_qdma_set_tx_rate_limit
@@ -2818,17 +2817,16 @@ static int airoha_qdma_set_tx_rate_limit
u32 bucket_size)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -360,7 +360,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
REG_EGRESS_TRTCM_CFG,
i, rate, bucket_size);
if (err)
@@ -2866,11 +2864,11 @@ static int airoha_tc_htb_alloc_leaf_queu
@@ -2878,11 +2876,11 @@ static int airoha_tc_htb_alloc_leaf_queu
return 0;
}
@@ -374,7 +374,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
int i;
for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
@@ -2949,7 +2947,6 @@ static int airoha_dev_tc_matchall(struct
@@ -2961,7 +2959,6 @@ static int airoha_dev_tc_matchall(struct
{
enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT;
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -382,7 +382,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u32 rate = 0, bucket_size = 0;
switch (f->command) {
@@ -2974,7 +2971,7 @@ static int airoha_dev_tc_matchall(struct
@@ -2986,7 +2983,7 @@ static int airoha_dev_tc_matchall(struct
fallthrough;
}
case TC_CLSMATCHALL_DESTROY:
@@ -391,7 +391,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
unit_type);
default:
return -EOPNOTSUPP;
@@ -2986,8 +2983,7 @@ static int airoha_dev_setup_tc_block_cb(
@@ -2998,8 +2995,7 @@ static int airoha_dev_setup_tc_block_cb(
{
struct net_device *netdev = cb_priv;
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -401,7 +401,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (!tc_can_offload(netdev))
return -EOPNOTSUPP;
@@ -3222,7 +3218,7 @@ static void airoha_mac_link_up(struct ph
@@ -3234,7 +3230,7 @@ static void airoha_mac_link_up(struct ph
struct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev,
phylink_config);
struct airoha_gdm_port *port = dev->port;
@@ -412,7 +412,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -548,6 +548,7 @@ struct airoha_qdma {
@@ -549,6 +549,7 @@ struct airoha_qdma {
struct airoha_gdm_dev {
struct airoha_gdm_port *port;
@@ -420,7 +420,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct net_device *dev;
struct airoha_eth *eth;
@@ -558,7 +559,6 @@ struct airoha_gdm_dev {
@@ -559,7 +560,6 @@ struct airoha_gdm_dev {
};
struct airoha_gdm_port {
@@ -428,7 +428,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_gdm_dev *dev;
int id;
int nbq;
@@ -694,19 +694,18 @@ static inline bool airoha_qdma_is_lro_qu
@@ -695,19 +695,18 @@ static inline bool airoha_qdma_is_lro_qu
return !!(AIROHA_RXQ_LRO_EN_MASK & BIT(qid));
}
target/linux/airoha/patches-6.12/920-03-net-airoha-Rely-on-airoha_gdm_dev-pointer-in-airoha_.patch
+2 -2
View File
@@ -37,7 +37,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
val = (addr[0] << 16) | (addr[1] << 8) | addr[2];
airoha_fe_wr(eth, reg, val);
@@ -2028,7 +2026,7 @@ static int airoha_dev_init(struct net_de
@@ -2037,7 +2035,7 @@ static int airoha_dev_init(struct net_de
int i;
/* QDMA0 is used for lan ports while QDMA1 is used for WAN ports */
@@ -48,7 +48,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -663,8 +663,10 @@ static inline u16 airoha_qdma_get_txq(st
@@ -664,8 +664,10 @@ static inline u16 airoha_qdma_get_txq(st
return qid % ARRAY_SIZE(qdma->q_tx);
}
target/linux/airoha/patches-6.12/920-04-net-airoha-Move-qos_sq_bmap-in-airoha_gdm_dev-struct.patch
+10 -10
View File
@@ -22,7 +22,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2822,30 +2822,40 @@ static int airoha_qdma_set_tx_rate_limit
@@ -2834,30 +2834,40 @@ static int airoha_qdma_set_tx_rate_limit
return 0;
}
@@ -75,7 +75,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
err = netif_set_real_num_tx_queues(netdev, num_tx_queues + 1);
if (err) {
@@ -2853,13 +2863,17 @@ static int airoha_tc_htb_alloc_leaf_queu
@@ -2865,13 +2875,17 @@ static int airoha_tc_htb_alloc_leaf_queu
opt->quantum);
NL_SET_ERR_MSG_MOD(opt->extack,
"failed setting real_num_tx_queues");
@@ -95,7 +95,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
static int airoha_qdma_set_rx_meter(struct airoha_gdm_dev *dev,
@@ -3040,11 +3054,13 @@ static int airoha_dev_setup_tc_block(str
@@ -3052,11 +3066,13 @@ static int airoha_dev_setup_tc_block(str
static void airoha_tc_remove_htb_queue(struct net_device *netdev, int queue)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -111,7 +111,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
static int airoha_tc_htb_delete_leaf_queue(struct net_device *netdev,
@@ -3052,9 +3068,8 @@ static int airoha_tc_htb_delete_leaf_que
@@ -3064,9 +3080,8 @@ static int airoha_tc_htb_delete_leaf_que
{
u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -122,7 +122,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
return -EINVAL;
}
@@ -3067,10 +3082,9 @@ static int airoha_tc_htb_delete_leaf_que
@@ -3079,10 +3094,9 @@ static int airoha_tc_htb_delete_leaf_que
static int airoha_tc_htb_destroy(struct net_device *netdev)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -134,7 +134,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_tc_remove_htb_queue(netdev, q);
return 0;
@@ -3081,9 +3095,8 @@ static int airoha_tc_get_htb_get_leaf_qu
@@ -3093,9 +3107,8 @@ static int airoha_tc_get_htb_get_leaf_qu
{
u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -145,7 +145,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
return -EINVAL;
}
@@ -3102,6 +3115,7 @@ static int airoha_tc_setup_qdisc_htb(str
@@ -3114,6 +3127,7 @@ static int airoha_tc_setup_qdisc_htb(str
case TC_HTB_DESTROY:
return airoha_tc_htb_destroy(dev);
case TC_HTB_NODE_MODIFY:
@@ -155,7 +155,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
case TC_HTB_LEAF_DEL:
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -544,6 +544,8 @@ struct airoha_qdma {
@@ -545,6 +545,8 @@ struct airoha_qdma {
struct airoha_queue q_tx[AIROHA_NUM_TX_RING];
struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
@@ -164,7 +164,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
};
struct airoha_gdm_dev {
@@ -556,6 +558,8 @@ struct airoha_gdm_dev {
@@ -557,6 +559,8 @@ struct airoha_gdm_dev {
struct phylink *phylink;
struct phylink_config phylink_config;
#endif
@@ -173,7 +173,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
};
struct airoha_gdm_port {
@@ -565,8 +569,6 @@ struct airoha_gdm_port {
@@ -566,8 +570,6 @@ struct airoha_gdm_port {
struct airoha_hw_stats stats;
target/linux/airoha/patches-6.12/920-05-net-airoha-Move-cpu-fwd-_tx_packets-in-airoha_gdm_de.patch
+3 -3
View File
@@ -21,7 +21,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2535,19 +2535,17 @@ static int airoha_qdma_get_tx_ets_stats(
@@ -2547,19 +2547,17 @@ static int airoha_qdma_get_tx_ets_stats(
struct tc_ets_qopt_offload *opt)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -50,7 +50,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -560,6 +560,9 @@ struct airoha_gdm_dev {
@@ -561,6 +561,9 @@ struct airoha_gdm_dev {
#endif
DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
@@ -60,7 +60,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
};
struct airoha_gdm_port {
@@ -569,10 +572,6 @@ struct airoha_gdm_port {
@@ -570,10 +573,6 @@ struct airoha_gdm_port {
struct airoha_hw_stats stats;
target/linux/airoha/patches-6.12/920-06-net-airoha-Support-multiple-net_devices-for-a-single.patch
+32 -34
View File
@@ -65,7 +65,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (enable) {
airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);
airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);
@@ -618,30 +618,26 @@ static int airoha_qdma_fill_rx_queue(str
@@ -619,30 +619,26 @@ static int airoha_qdma_fill_rx_queue(str
return nframes;
}
@@ -113,7 +113,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
static int airoha_qdma_lro_rx_process(struct airoha_queue *q,
@@ -725,9 +721,8 @@ static int airoha_qdma_rx_process(struct
@@ -736,9 +732,8 @@ static int airoha_qdma_rx_process(struct
struct airoha_queue_entry *e = &q->entry[q->tail];
struct airoha_qdma_desc *desc = &q->desc[q->tail];
u32 hash, reason, msg1, desc_ctrl;
@@ -125,7 +125,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct page *page;
desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
@@ -748,15 +743,10 @@ static int airoha_qdma_rx_process(struct
@@ -759,15 +754,10 @@ static int airoha_qdma_rx_process(struct
if (!len || data_len < len)
goto free_frag;
@@ -143,26 +143,24 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (!q->skb) { /* first buffer */
q->skb = napi_build_skb(e->buf - AIROHA_RX_HEADROOM,
q->buf_size);
@@ -766,15 +756,15 @@ static int airoha_qdma_rx_process(struct
@@ -776,14 +766,14 @@ static int airoha_qdma_rx_process(struct
skb_reserve(q->skb, AIROHA_RX_HEADROOM);
__skb_put(q->skb, len);
skb_mark_for_recycle(q->skb);
- q->skb->dev = netdev;
+ q->skb->dev = dev->dev;
q->skb->ip_summed = CHECKSUM_UNNECESSARY;
skb_record_rx_queue(q->skb, qid);
- if (lro_q && (netdev->features & NETIF_F_LRO) &&
+ if (lro_q && (dev->dev->features & NETIF_F_LRO) &&
airoha_qdma_lro_rx_process(q, desc) < 0)
if (airoha_qdma_lro_rx_process(q, desc) < 0)
goto free_frag;
- q->skb->protocol = eth_type_trans(q->skb, netdev);
+ q->skb->protocol = eth_type_trans(q->skb, dev->dev);
skb_mark_for_recycle(q->skb);
} else { /* scattered frame */
struct skb_shared_info *shinfo = skb_shinfo(q->skb);
int nr_frags = shinfo->nr_frags;
@@ -790,7 +780,9 @@ static int airoha_qdma_rx_process(struct
@@ -800,7 +790,9 @@ static int airoha_qdma_rx_process(struct
if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl))
continue;
@@ -173,7 +171,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
/* PPE module requires untagged packets to work
* properly and it provides DSA port index via the
* DMA descriptor. Report DSA tag to the DSA stack
@@ -987,24 +979,27 @@ static void airoha_qdma_wake_netdev_txqs
@@ -996,24 +988,27 @@ static void airoha_qdma_wake_netdev_txqs
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
@@ -211,7 +209,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
}
q->txq_stopped = false;
@@ -1893,11 +1888,9 @@ static int airoha_dev_open(struct net_de
@@ -1902,11 +1897,9 @@ static int airoha_dev_open(struct net_de
GLOBAL_CFG_RX_DMA_EN_MASK);
atomic_inc(&qdma->users);
@@ -225,7 +223,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id),
pse_port);
@@ -1992,7 +1985,7 @@ static int airoha_set_gdm2_loopback(stru
@@ -2001,7 +1994,7 @@ static int airoha_set_gdm2_loopback(stru
airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX));
airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX));
@@ -234,7 +232,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (src_port < 0)
return src_port;
@@ -2009,7 +2002,7 @@ static int airoha_set_gdm2_loopback(stru
@@ -2018,7 +2011,7 @@ static int airoha_set_gdm2_loopback(stru
airoha_ppe_set_cpu_port(dev, i, AIROHA_GDM2_IDX);
if (port->id == AIROHA_GDM4_IDX && airoha_is_7581(eth)) {
@@ -243,7 +241,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, mask,
__field_prep(mask, AIROHA_GDM2_IDX));
@@ -2023,7 +2016,7 @@ static int airoha_dev_init(struct net_de
@@ -2032,7 +2025,7 @@ static int airoha_dev_init(struct net_de
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
struct airoha_eth *eth = dev->eth;
@@ -252,7 +250,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
/* QDMA0 is used for lan ports while QDMA1 is used for WAN ports */
dev->qdma = &eth->qdma[!airoha_is_lan_gdm_dev(dev)];
@@ -2046,8 +2039,8 @@ static int airoha_dev_init(struct net_de
@@ -2055,8 +2048,8 @@ static int airoha_dev_init(struct net_de
break;
}
@@ -263,7 +261,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
return 0;
}
@@ -2209,20 +2202,26 @@ static int airoha_dev_set_features(struc
@@ -2221,20 +2214,26 @@ static int airoha_dev_set_features(struc
} else {
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *p = eth->ports[i];
@@ -298,7 +296,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
airoha_fe_lro_disable(eth, qdma_id);
}
@@ -2273,7 +2272,8 @@ static netdev_tx_t airoha_dev_xmit(struc
@@ -2285,7 +2284,8 @@ static netdev_tx_t airoha_dev_xmit(struc
}
fport = airoha_get_fe_port(dev);
@@ -308,7 +306,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f);
q = &qdma->q_tx[qid];
@@ -3209,12 +3209,15 @@ bool airoha_is_valid_gdm_dev(struct airo
@@ -3221,12 +3221,15 @@ bool airoha_is_valid_gdm_dev(struct airo
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
@@ -326,7 +324,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
return false;
@@ -3338,10 +3341,11 @@ static int airoha_setup_phylink(struct n
@@ -3350,10 +3353,11 @@ static int airoha_setup_phylink(struct n
static int airoha_alloc_gdm_device(struct airoha_eth *eth,
struct airoha_gdm_port *port,
@@ -340,7 +338,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
int err;
netdev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*dev),
@@ -3359,7 +3363,6 @@ static int airoha_alloc_gdm_device(struc
@@ -3371,7 +3375,6 @@ static int airoha_alloc_gdm_device(struc
netdev->hw_features = AIROHA_HW_FEATURES | NETIF_F_LRO;
netdev->features |= AIROHA_HW_FEATURES;
netdev->vlan_features = AIROHA_HW_FEATURES;
@@ -348,7 +346,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
SET_NETDEV_DEV(netdev, eth->dev);
/* reserve hw queues for HTB offloading */
@@ -3377,11 +3380,25 @@ static int airoha_alloc_gdm_device(struc
@@ -3389,11 +3392,25 @@ static int airoha_alloc_gdm_device(struc
netdev->dev_addr);
}
@@ -375,7 +373,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
#if defined(CONFIG_PCS_AIROHA)
if (airhoa_is_phy_external(port)) {
@@ -3399,7 +3416,8 @@ static int airoha_alloc_gdm_port(struct
@@ -3411,7 +3428,8 @@ static int airoha_alloc_gdm_port(struct
{
const __be32 *id_ptr = of_get_property(np, "reg", NULL);
struct airoha_gdm_port *port;
@@ -385,7 +383,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
u32 id;
if (!id_ptr) {
@@ -3427,15 +3445,51 @@ static int airoha_alloc_gdm_port(struct
@@ -3439,15 +3457,51 @@ static int airoha_alloc_gdm_port(struct
u64_stats_init(&port->stats.syncp);
spin_lock_init(&port->stats.lock);
port->id = id;
@@ -440,7 +438,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
static int airoha_register_gdm_devices(struct airoha_eth *eth)
@@ -3444,14 +3498,22 @@ static int airoha_register_gdm_devices(s
@@ -3456,14 +3510,22 @@ static int airoha_register_gdm_devices(s
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
@@ -467,7 +465,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
set_bit(DEV_STATE_REGISTERED, &eth->state);
@@ -3558,18 +3620,27 @@ error_napi_stop:
@@ -3570,18 +3632,27 @@ error_napi_stop:
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
@@ -501,7 +499,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
airoha_metadata_dst_free(port);
}
@@ -3591,19 +3662,26 @@ static void airoha_remove(struct platfor
@@ -3603,19 +3674,26 @@ static void airoha_remove(struct platfor
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
@@ -533,7 +531,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_metadata_dst_free(port);
}
airoha_hw_cleanup(eth);
@@ -3665,6 +3743,39 @@ static u32 airoha_en7581_get_vip_port(st
@@ -3677,6 +3755,39 @@ static u32 airoha_en7581_get_vip_port(st
return 0;
}
@@ -573,7 +571,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static const char * const an7583_xsi_rsts_names[] = {
"hsi0-mac",
"hsi1-mac",
@@ -3713,6 +3824,36 @@ static u32 airoha_an7583_get_vip_port(st
@@ -3725,6 +3836,36 @@ static u32 airoha_an7583_get_vip_port(st
return 0;
}
@@ -610,7 +608,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static const struct airoha_eth_soc_data en7581_soc_data = {
.version = 0x7581,
.xsi_rsts_names = en7581_xsi_rsts_names,
@@ -3721,6 +3862,7 @@ static const struct airoha_eth_soc_data
@@ -3733,6 +3874,7 @@ static const struct airoha_eth_soc_data
.ops = {
.get_sport = airoha_en7581_get_sport,
.get_vip_port = airoha_en7581_get_vip_port,
@@ -618,7 +616,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
},
};
@@ -3732,6 +3874,7 @@ static const struct airoha_eth_soc_data
@@ -3744,6 +3886,7 @@ static const struct airoha_eth_soc_data
.ops = {
.get_sport = airoha_an7583_get_sport,
.get_vip_port = airoha_an7583_get_vip_port,
@@ -636,7 +634,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
#define AIROHA_MAX_NUM_QDMA 2
#define AIROHA_MAX_NUM_IRQ_BANKS 4
#define AIROHA_MAX_DSA_PORTS 7
@@ -551,8 +552,8 @@ struct airoha_qdma {
@@ -552,8 +553,8 @@ struct airoha_qdma {
struct airoha_gdm_dev {
struct airoha_gdm_port *port;
struct airoha_qdma *qdma;
@@ -646,7 +644,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
#if defined(CONFIG_PCS_AIROHA)
struct phylink *phylink;
@@ -563,12 +564,13 @@ struct airoha_gdm_dev {
@@ -564,12 +565,13 @@ struct airoha_gdm_dev {
/* qos stats counters */
u64 cpu_tx_packets;
u64 fwd_tx_packets;
@@ -662,7 +660,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_hw_stats stats;
@@ -604,6 +606,8 @@ struct airoha_eth_soc_data {
@@ -605,6 +607,8 @@ struct airoha_eth_soc_data {
struct {
int (*get_sport)(struct airoha_gdm_port *port, int nbq);
u32 (*get_vip_port)(struct airoha_gdm_port *port, int nbq);
target/linux/airoha/patches-6.12/920-07-net-airoha-Do-not-stop-GDM-port-if-it-is-shared.patch
+6 -6
View File
@@ -23,7 +23,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1849,8 +1849,8 @@ static int airoha_dev_open(struct net_de
@@ -1858,8 +1858,8 @@ static int airoha_dev_open(struct net_de
int err, len = ETH_HLEN + netdev->mtu + ETH_FCS_LEN;
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
@@ -33,7 +33,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
#if defined(CONFIG_PCS_AIROHA)
if (airhoa_is_phy_external(port)) {
@@ -1878,10 +1878,20 @@ static int airoha_dev_open(struct net_de
@@ -1887,10 +1887,20 @@ static int airoha_dev_open(struct net_de
airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
GDM_STAG_EN_MASK);
@@ -58,7 +58,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
GLOBAL_CFG_TX_DMA_EN_MASK |
@@ -1897,6 +1907,30 @@ static int airoha_dev_open(struct net_de
@@ -1906,6 +1916,30 @@ static int airoha_dev_open(struct net_de
return 0;
}
@@ -89,7 +89,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static int airoha_dev_stop(struct net_device *netdev)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -1909,8 +1943,12 @@ static int airoha_dev_stop(struct net_de
@@ -1918,8 +1952,12 @@ static int airoha_dev_stop(struct net_de
for (i = 0; i < netdev->num_tx_queues; i++)
netdev_tx_reset_subqueue(netdev, i);
@@ -104,7 +104,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (atomic_dec_and_test(&qdma->users)) {
airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
@@ -2072,13 +2110,10 @@ static int airoha_dev_change_mtu(struct
@@ -2081,13 +2119,10 @@ static int airoha_dev_change_mtu(struct
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
@@ -122,7 +122,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -571,6 +571,7 @@ struct airoha_gdm_dev {
@@ -572,6 +572,7 @@ struct airoha_gdm_dev {
struct airoha_gdm_port {
struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS];
int id;
target/linux/airoha/patches-6.12/920-08-net-airoha-Introduce-WAN-device-flag.patch
+4 -4
View File
@@ -29,7 +29,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2049,36 +2049,80 @@ static int airoha_set_gdm2_loopback(stru
@@ -2058,36 +2058,80 @@ static int airoha_set_gdm2_loopback(stru
return 0;
}
@@ -127,7 +127,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -549,6 +549,10 @@ struct airoha_qdma {
@@ -550,6 +550,10 @@ struct airoha_qdma {
DECLARE_BITMAP(qos_channel_map, AIROHA_NUM_QOS_CHANNELS);
};
@@ -138,7 +138,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
struct airoha_gdm_dev {
struct airoha_gdm_port *port;
struct airoha_qdma *qdma;
@@ -565,6 +569,7 @@ struct airoha_gdm_dev {
@@ -566,6 +570,7 @@ struct airoha_gdm_dev {
u64 cpu_tx_packets;
u64 fwd_tx_packets;
@@ -146,7 +146,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
int nbq;
};
@@ -671,13 +676,7 @@ static inline u16 airoha_qdma_get_txq(st
@@ -672,13 +677,7 @@ static inline u16 airoha_qdma_get_txq(st
static inline bool airoha_is_lan_gdm_dev(struct airoha_gdm_dev *dev)
{
target/linux/airoha/patches-6.12/920-09-net-airoha-Support-multiple-LAN-WAN-interfaces-for-h.patch
+4 -4
View File
@@ -103,15 +103,15 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
- airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val);
+ airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), lmin);
+ airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), lmax);
+
+ airoha_ppe_init_upd_mem(dev, addr);
- airoha_ppe_init_upd_mem(dev);
+ airoha_ppe_init_upd_mem(dev, addr);
+
+ return 0;
}
static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,
@@ -1976,13 +2030,18 @@ static int airoha_dev_stop(struct net_de
@@ -1985,13 +2039,18 @@ static int airoha_dev_stop(struct net_de
static int airoha_dev_set_macaddr(struct net_device *netdev, void *p)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -134,7 +134,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -712,7 +712,7 @@ void airoha_ppe_check_skb(struct airoha_
@@ -713,7 +713,7 @@ void airoha_ppe_check_skb(struct airoha_
int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data);
int airoha_ppe_init(struct airoha_eth *eth);
void airoha_ppe_deinit(struct airoha_eth *eth);
target/linux/airoha/patches-6.12/920-10-net-airoha-Rename-airoha_set_gdm2_loopback-in-airoha.patch
+2 -2
View File
@@ -17,7 +17,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2046,7 +2046,7 @@ static int airoha_dev_set_macaddr(struct
@@ -2055,7 +2055,7 @@ static int airoha_dev_set_macaddr(struct
return 0;
}
@@ -26,7 +26,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
{
struct airoha_gdm_port *port = dev->port;
struct airoha_eth *eth = dev->eth;
@@ -2178,7 +2178,7 @@ static int airoha_dev_init(struct net_de
@@ -2187,7 +2187,7 @@ static int airoha_dev_init(struct net_de
(port->id == AIROHA_GDM3_IDX || port->id == AIROHA_GDM4_IDX)) {
int err;
target/linux/airoha/patches-6.12/920-12-net-airoha-Add-ethtool-priv_flags-callbacks.patch
+6 -6
View File
@@ -19,7 +19,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1906,6 +1906,11 @@ static int airoha_dev_open(struct net_de
@@ -1915,6 +1915,11 @@ static int airoha_dev_open(struct net_de
u32 cur_len, pse_port = FE_PSE_PORT_PPE1;
struct airoha_qdma *qdma = dev->qdma;
@@ -31,7 +31,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
#if defined(CONFIG_PCS_AIROHA)
if (airhoa_is_phy_external(port)) {
err = phylink_of_phy_connect(dev->phylink, netdev->dev.of_node, 0);
@@ -2108,6 +2113,45 @@ static int airoha_enable_gdm2_loopback(s
@@ -2117,6 +2122,45 @@ static int airoha_enable_gdm2_loopback(s
return 0;
}
@@ -77,7 +77,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static struct airoha_gdm_dev *
airoha_get_wan_gdm_dev(struct airoha_eth *eth)
{
@@ -2509,6 +2553,80 @@ error:
@@ -2521,6 +2565,80 @@ error:
return NETDEV_TX_OK;
}
@@ -158,7 +158,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static void airoha_ethtool_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *info)
{
@@ -2517,6 +2635,7 @@ static void airoha_ethtool_get_drvinfo(s
@@ -2529,6 +2647,7 @@ static void airoha_ethtool_get_drvinfo(s
strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver));
strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info));
@@ -166,7 +166,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
}
static void airoha_ethtool_get_mac_stats(struct net_device *netdev,
@@ -2581,6 +2700,56 @@ airoha_ethtool_get_rmon_stats(struct net
@@ -2593,6 +2712,56 @@ airoha_ethtool_get_rmon_stats(struct net
} while (u64_stats_fetch_retry(&port->stats.syncp, start));
}
@@ -223,7 +223,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev,
int channel, enum tx_sched_mode mode,
const u16 *weights, u8 n_weights)
@@ -3302,6 +3471,10 @@ static const struct ethtool_ops airoha_e
@@ -3314,6 +3483,10 @@ static const struct ethtool_ops airoha_e
.get_rmon_stats = airoha_ethtool_get_rmon_stats,
.get_link_ksettings = phy_ethtool_get_link_ksettings,
.get_link = ethtool_op_get_link,
target/linux/airoha/patches-6.12/920-13-net-airoha-Rework-MTU-configuration.patch
+6 -6
View File
@@ -33,7 +33,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
airoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK,
FIELD_PREP(CDM_VLAN_MASK, 0x8100));
@@ -1898,13 +1903,37 @@ static void airoha_update_hw_stats(struc
@@ -1907,13 +1912,37 @@ static void airoha_update_hw_stats(struc
spin_unlock(&port->stats.lock);
}
@@ -73,7 +73,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
if (port->id == AIROHA_GDM2_IDX && airoha_is_lan_gdm_dev(dev)) {
/* GDM2 can be used just as wan */
@@ -1937,19 +1966,12 @@ static int airoha_dev_open(struct net_de
@@ -1946,19 +1975,12 @@ static int airoha_dev_open(struct net_de
airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
GDM_STAG_EN_MASK);
@@ -99,7 +99,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
port->users++;
airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
@@ -1966,30 +1988,6 @@ static int airoha_dev_open(struct net_de
@@ -1975,30 +1997,6 @@ static int airoha_dev_open(struct net_de
return 0;
}
@@ -130,7 +130,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
static int airoha_dev_stop(struct net_device *netdev)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -2073,10 +2071,6 @@ static int airoha_enable_gdm2_loopback(s
@@ -2082,10 +2080,6 @@ static int airoha_enable_gdm2_loopback(s
FIELD_PREP(LPBK_CHAN_MASK, chan) |
LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK |
LBK_CHAN_MODE_MASK | LPBK_EN_MASK);
@@ -141,7 +141,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
/* Forward the traffic to the proper GDM port */
pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3
: FE_PSE_PORT_GDM4;
@@ -2600,6 +2594,9 @@ static int airoha_dev_set_wan_flag(struc
@@ -2612,6 +2606,9 @@ static int airoha_dev_set_wan_flag(struc
default:
return -EOPNOTSUPP;
}
@@ -153,7 +153,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
case AIROHA_GDM3_IDX:
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -705,6 +705,7 @@ int airoha_get_fe_port(struct airoha_gdm
@@ -706,6 +706,7 @@ int airoha_get_fe_port(struct airoha_gdm
bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
struct airoha_gdm_dev *dev);
target/linux/airoha/patches-6.12/920-14-net-airoha-Better-handle-MIB-for-GDM-with-multiple-p.patch
+12 -12
View File
@@ -31,7 +31,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -611,6 +611,14 @@ static int airoha_fe_init(struct airoha_
@@ -612,6 +612,14 @@ static int airoha_fe_init(struct airoha_
airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX),
GDM_PAD_EN_MASK | GDM_STRIP_CRC_MASK);
@@ -46,7 +46,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
airoha_fe_crsn_qsel_init(eth);
airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK);
@@ -1758,149 +1766,169 @@ static void airoha_qdma_stop_napi(struct
@@ -1767,149 +1775,169 @@ static void airoha_qdma_stop_napi(struct
}
}
@@ -270,7 +270,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
}
void airoha_set_port_mtu(struct airoha_eth *eth, struct airoha_gdm_port *port)
@@ -2228,23 +2256,22 @@ static void airoha_dev_get_stats64(struc
@@ -2237,23 +2265,22 @@ static void airoha_dev_get_stats64(struc
struct rtnl_link_stats64 *storage)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -306,7 +306,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
}
static int airoha_dev_change_mtu(struct net_device *netdev, int mtu)
@@ -2639,20 +2666,19 @@ static void airoha_ethtool_get_mac_stats
@@ -2651,20 +2678,19 @@ static void airoha_ethtool_get_mac_stats
struct ethtool_eth_mac_stats *stats)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -336,7 +336,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
}
static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = {
@@ -2672,8 +2698,7 @@ airoha_ethtool_get_rmon_stats(struct net
@@ -2684,8 +2710,7 @@ airoha_ethtool_get_rmon_stats(struct net
const struct ethtool_rmon_hist_range **ranges)
{
struct airoha_gdm_dev *dev = netdev_priv(netdev);
@@ -346,7 +346,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
unsigned int start;
BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) !=
@@ -2686,7 +2711,7 @@ airoha_ethtool_get_rmon_stats(struct net
@@ -2698,7 +2723,7 @@ airoha_ethtool_get_rmon_stats(struct net
do {
int i;
@@ -355,7 +355,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
stats->fragments = hw_stats->rx_fragment;
stats->jabbers = hw_stats->rx_jabber;
for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1;
@@ -2694,7 +2719,7 @@ airoha_ethtool_get_rmon_stats(struct net
@@ -2706,7 +2731,7 @@ airoha_ethtool_get_rmon_stats(struct net
stats->hist[i] = hw_stats->rx_len[i];
stats->hist_tx[i] = hw_stats->tx_len[i];
}
@@ -364,7 +364,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
}
static int airoha_ethtool_set_priv_flags(struct net_device *netdev, u32 flags)
@@ -3702,6 +3727,7 @@ static int airoha_alloc_gdm_device(struc
@@ -3714,6 +3739,7 @@ static int airoha_alloc_gdm_device(struc
netdev->dev.of_node = of_node_get(np);
dev = netdev_priv(netdev);
@@ -372,7 +372,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
dev->dev = netdev;
dev->port = port;
dev->eth = eth;
@@ -3750,9 +3776,8 @@ static int airoha_alloc_gdm_port(struct
@@ -3762,9 +3788,8 @@ static int airoha_alloc_gdm_port(struct
if (!port)
return -ENOMEM;
@@ -385,7 +385,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
err = airoha_metadata_dst_alloc(port);
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -226,8 +226,6 @@ struct airoha_tx_irq_queue {
@@ -227,8 +227,6 @@ struct airoha_tx_irq_queue {
};
struct airoha_hw_stats {
@@ -394,7 +394,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
struct u64_stats_sync syncp;
/* get_stats64 */
@@ -571,6 +569,8 @@ struct airoha_gdm_dev {
@@ -572,6 +570,8 @@ struct airoha_gdm_dev {
u32 flags;
int nbq;
@@ -403,7 +403,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
};
struct airoha_gdm_port {
@@ -578,7 +578,8 @@ struct airoha_gdm_port {
@@ -579,7 +579,8 @@ struct airoha_gdm_port {
int id;
int users;
target/linux/airoha/patches-6.12/920-15-net-airoha-fix-wrong-airoha_get_fe_port.patch
+1 -1
View File
@@ -18,7 +18,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2353,17 +2353,9 @@ static u32 airoha_get_dsa_tag(struct sk_
@@ -2362,17 +2362,9 @@ static u32 airoha_get_dsa_tag(struct sk_
int airoha_get_fe_port(struct airoha_gdm_dev *dev)
{
struct airoha_gdm_port *port = dev->port;
target/linux/mvebu/cortexa53/base-files/etc/board.d/05_compat_version
+15
View File
@@ -0,0 +1,15 @@
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
methode,udpu|\
methode,edpu)
ucidef_set_compat_version "2.0"
;;
esac
board_config_flush
exit 0
target/linux/mvebu/cortexa53/base-files/etc/init.d/bootcount
Executable
+12
View File
@@ -0,0 +1,12 @@
#!/bin/sh /etc/rc.common
START=99
boot() {
case $(board_name) in
methode,udpu|\
methode,edpu)
fw_setenv bootcount 0
;;
esac
}
target/linux/mvebu/cortexa53/base-files/lib/preinit/82_uDPU
-49
View File
@@ -1,49 +0,0 @@
#
# Copyright (C) 2014-2019 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
preinit_mount_udpu() {
. /lib/functions.sh
. /lib/upgrade/common.sh
case $(board_name) in
methode,udpu|\
methode,edpu)
# Check which device is detected
[ -b "/dev/mmcblk0" ] && mmcdev="/dev/mmcblk0" || mmcdev="/dev/mmcblk1"
if [ -b "${mmcdev}p4" ]; then
mkdir /misc
mount -o compress_algorithm=zstd -t f2fs ${mmcdev}p4 /misc
[ -f "/misc/$BACKUP_FILE" ] && {
echo "- Restoring configuration files -"
tar xzf "/misc/$BACKUP_FILE" -C /
rm -f "/misc/$BACKUP_FILE"
sync
}
[ -f "/misc/firmware/recovery.itb" ] && {
echo "- Updating /recovery partition -"
mkfs.ext4 -q ${mmcdev}p2 | echo y &> /dev/null
mkdir -p /tmp/recovery
mount ${mmcdev}p2 /tmp/recovery
cp /misc/firmware/recovery.itb /tmp/recovery
[ -f "/misc/firmware/boot.scr" ] && \
cp /misc/firmware/boot.scr /tmp/recovery
sync
umount /tmp/recovery
rm -rf /tmp/recovery
# Replace previous backup with the new one
[ -d "/misc/firmware_old" ] && rm -rf /misc/firmware_old
[ -d "/misc/firmware" ] && mv /misc/firmware /misc/firmware_old
}
fi
# Legacy support - if rootfs was booted, instruct u-boot to keep the current root dev
[ "$(df | grep /dev/root)" ] && fw_setenv root_ok '2'
;;
esac
}
boot_hook_add preinit_main preinit_mount_udpu
target/linux/mvebu/cortexa53/base-files/lib/upgrade/platform.sh
+75 -2
View File
@@ -7,6 +7,40 @@ RAMFS_COPY_BIN='fw_printenv fw_setenv mkfs.f2fs fdisk'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
REQUIRE_IMAGE_METADATA=1
# U-Boot loads the first boot.scr it finds, so keep the active slot's script in
# sync even when the full upgrade is written to the inactive slot.
methode_update_active_bootscript() {
local active_part="$1"
local updated_part="$2"
local active_dev
local updated_dev
local ret=0
[ "$active_part" -a "$updated_part" ] || return 0
active_dev="$(find_mmc_part "$active_part" "$CI_ROOTDEV")"
updated_dev="$(find_mmc_part "$updated_part" "$CI_ROOTDEV")"
[ "$active_dev" -a "$updated_dev" ] || return 1
mkdir -p /tmp/bootpart-new
mount -o ro "$updated_dev" /tmp/bootpart-new || return 1
cp /tmp/bootpart-new/boot.scr /tmp/boot.scr
ret=$?
umount /tmp/bootpart-new
[ $ret -eq 0 ] || return 1
mkdir -p /tmp/bootpart-active
mount "$active_dev" /tmp/bootpart-active || return 1
cp /tmp/boot.scr /tmp/bootpart-active/boot.scr || ret=1
sync
umount /tmp/bootpart-active
return $ret
}
platform_check_image() {
case "$(board_name)" in
glinet,gl-mv1000|\
@@ -35,7 +69,46 @@ platform_do_upgrade() {
;;
methode,udpu|\
methode,edpu)
platform_do_upgrade_uDPU "$1"
local active_kernpart
[ "$(rootfs_type)" = "tmpfs" ] && {
local firmware_active="$(fw_printenv -n bootactive)"
case "$firmware_active" in
1)
active_kernpart="kernel_1"
CI_KERNPART="kernel_2"
CI_ROOTPART="rootfs_2"
fw_setenv bootactive 2
;;
2)
active_kernpart="kernel_2"
CI_KERNPART="kernel_1"
CI_ROOTPART="rootfs_1"
fw_setenv bootactive 1
;;
esac
}
local root="$(cmdline_get_var root)"
case "$root" in
/dev/mmcblk*p2)
active_kernpart="kernel_1"
CI_KERNPART="kernel_2"
CI_ROOTPART="rootfs_2"
fw_setenv bootactive 2
;;
/dev/mmcblk*p4)
active_kernpart="kernel_2"
CI_KERNPART="kernel_1"
CI_ROOTPART="rootfs_1"
fw_setenv bootactive 1
;;
esac
emmc_do_upgrade "$1"
methode_update_active_bootscript "$active_kernpart" "$CI_KERNPART" || \
echo "Failed to update active boot script"
;;
*)
default_do_upgrade "$1"
@@ -54,7 +127,7 @@ platform_copy_config() {
;;
methode,udpu|\
methode,edpu)
platform_copy_config_uDPU
emmc_copy_config
;;
esac
}
target/linux/mvebu/cortexa53/base-files/lib/upgrade/uDPU.sh
-162
View File
@@ -1,162 +0,0 @@
udpu_check_emmc() {
# uDPU uses combined ext4 and f2fs partitions.
# partition layout:
# 1. boot (ext4)
# 2. recovery (ext4)
# 3. rootfs (f2fs)
# 4. misc (f2fs)
# Check which device is available, depending on the board revision
if [ -b "/dev/mmcblk1" ]; then
emmc_dev=/dev/mmcblk1
elif [ -b "/dev/mmcblk0" ]; then
emmc_dev=/dev/mmcblk0
else
echo "Cannot detect eMMC flash, aborting.."
exit 1
fi
}
udpu_part_prep() {
if grep -q "$1" /proc/mounts; then
mounted_part="$(grep -m 1 $1 /proc/mounts | awk '{print $2}')"
umount "$mounted_part"
grep -woq "$mounted_part" /proc/mounts && umount -l "$mounted_part"
fi
}
udpu_do_part_check() {
local emmc_parts="1 2 3 4"
local part_valid="1"
# Check if the block devices exist
for num in ${emmc_parts}; do
[ ! -b ${emmc_dev}p${num} ] && part_valid="0"
done
# If partitions are missing create a new partition table
if [ "$part_valid" != "1" ]; then
printf "Invalid partition table, creating a new one\n"
printf "o\nn\np\n1\n\n+256M\nn\np\n2\n\n+256M\nn\np\n3\n\n+1536M\nn\np\n\n\nw\n" | fdisk -W always $emmc_dev > /dev/null 2>&1
# Format the /misc part right away as we will need it for the firmware
printf "Formating /misc partition, this make take a while..\n"
udpu_part_prep ${emmc_dev}p4
if mkfs.f2fs -q -l misc -O extra_attr,compression ${emmc_dev}p4; then
printf "/misc partition formated successfully\n"
else
printf "/misc partition formatting failed\n"
fi
udpu_do_initial_setup
else
printf "Partition table looks ok\n"
fi
}
udpu_do_misc_prep() {
if ! grep -woq /misc /proc/mounts; then
mkdir -p /misc
# If the mount fails, try to reformat partition
# Leaving possiblity for multiple iterations
if ! mount ${emmc_dev}p4 /misc; then
printf "Error while mounting /misc, trying to reformat..\n"
format_count=0
while [ "$format_count" -lt "1" ]; do
udpu_part_prep ${emmc_dev}p4
mkfs.f2fs -q -l misc -O extra_attr,compression ${emmc_dev}p4
if ! mount ${emmc_dev}p4 /misc; then
umount -l /misc
printf "Failed while mounting /misc\n"
format_count=$((format_count +1))
else
printf "Mounted /misc successfully\n"
break
fi
done
fi
fi
}
udpu_do_initial_setup() {
# Prepare /recovery parition
udpu_part_prep ${emmc_dev}p2
mkfs.ext4 -qF ${emmc_dev}p2 2>&1 /dev/null
# Prepare /boot partition
udpu_part_prep ${emmc_dev}p1
mkfs.ext4 -qF ${emmc_dev}p1 2>&1 /dev/null
# Prepare /root partition
printf "Formating /root partition, this may take a while..\n"
udpu_part_prep ${emmc_dev}p3
mkfs.f2fs -q -l rootfs -O extra_attr,compression ${emmc_dev}p3 && printf "/root partition reformated\n"
}
udpu_do_regular_upgrade() {
# Clean /boot partition - mfks.ext4 is not available in chroot
grep -woq /boot /proc/mounts && umount /boot
mkdir -p /tmp/boot
mount ${emmc_dev}p1 /tmp/boot
rm -rf /tmp/boot/*
# Clean /root partition - mkfs.f2fs is not available in chroot
grep -woq /dev/root /proc/mounts && umount /
mkdir -p /tmp/rootpart
mount ${emmc_dev}p3 /tmp/rootpart
rm -rf /tmp/rootpart/*
}
platform_do_upgrade_uDPU() {
udpu_check_emmc
# Prepare and extract firmware on /misc partition
udpu_do_misc_prep
[ -f "/misc/firmware" ] && rm -r /misc/firmware
mkdir -p /misc/firmware
tar xzf "$1" -C /misc/firmware/
udpu_do_regular_upgrade
printf "Updating /boot partition\n"
if tar xzf /misc/firmware/boot.tgz -C /tmp/boot; then
printf "/boot partition updated successfully\n"
else
printf "/boot partition update failed\n"
fi
sync
printf "Updating /root partition\n"
if tar xzf /misc/firmware/rootfs.tgz -C /tmp/rootpart; then
printf "/root partition updated successfully\n"
else
printf "/root partition update failed\n"
fi
sync
# Saving configuration files over sysupgrade
platform_copy_config_uDPU
# Remove tmp mounts
tmp_parts=$(grep "${emmc_dev}" /proc/mounts | awk '{print $2}')
for part in ${tmp_parts}; do
umount "$part"
# Force umount is necessary
grep -q "${part}" /proc/mounts && umount -l "$part"
done
# Sysupgrade complains about /tmp and /dev, so we can detach them here
umount -l /tmp
umount -l /dev
}
platform_copy_config_uDPU() {
# Config is saved on the /misc partition and copied on the rootfs after the reboot
if [ -f "$UPGRADE_BACKUP" ]; then
cp -f "$UPGRADE_BACKUP" "/misc/$BACKUP_FILE"
sync
fi
}
target/linux/mvebu/cortexa53/target.mk
+1 -1
View File
@@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk
ARCH:=aarch64
BOARDNAME:=Marvell Armada 3700LP (ARM64)
CPU_TYPE:=cortex-a53
FEATURES+=ext4
FEATURES+=ext4 emmc
DEFAULT_PACKAGES+=e2fsprogs ethtool mkf2fs partx-utils
KERNELNAME:=Image dtbs
target/linux/mvebu/image/Makefile
-13
View File
@@ -136,19 +136,6 @@ define Build/sdcard-img-ext4
83 $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS)
endef
define Build/uDPU-firmware
(rm -fR $@-fw; mkdir -p $@-fw)
$(CP) $(BIN_DIR)/$(KERNEL_INITRAMFS_IMAGE) $@-fw/recovery.itb
$(CP) $(IMAGE_ROOTFS) $@-fw/rootfs.tgz
$(CP) $@-boot.scr $@-fw/boot.scr
$(TAR) -czp --numeric-owner --owner=0 --group=0 --sort=name \
$(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
-f $@-fw/boot.tgz -C $@.boot .
$(TAR) -czp --numeric-owner --owner=0 --group=0 --sort=name \
$(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
-f $(KDIR_TMP)/$(DEVICE_IMG_PREFIX)-firmware.tgz -C $@-fw .
endef
define Device/FitImage
KERNEL_SUFFIX := -uImage.itb
KERNEL = kernel-bin | libdeflate-gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
target/linux/mvebu/image/cortexa53.mk
+35 -8
View File
@@ -97,19 +97,46 @@ define Device/marvell_armada-3720-db
endef
TARGET_DEVICES += marvell_armada-3720-db
define Build/methode-gpt-emmc
cp $@ $@.tmp 2>/dev/null || true
ptgen -g -o $@.tmp -l 1024 \
-t 0x2e -N kernel_1 -r -B -p 32M@1M \
-t 0x2e -N rootfs_1 -r -p 1536M@33M \
-t 0x2e -N kernel_2 -r -B -p 32M@1569M \
-t 0x2e -N rootfs_2 -r -p 1536M@1601M
cat $@.tmp >> $@
rm $@.tmp
endef
define Build/append-boot-part
dd if=$@.bootimg bs=32M conv=sync >> $@
endef
define Device/eMMC-methode
DEVICE_DTS_DIR := $(DTS_DIR)/marvell
KERNEL_NAME := Image
KERNEL := kernel-bin
KERNEL_LOADADDR := 0x00800000
DEVICE_PACKAGES += kmod-i2c-pxa kmod-hwmon-lm75 kmod-dsa-mv88e6xxx
DEVICE_COMPAT_VERSION := 2.0
DEVICE_COMPAT_MESSAGE := Partition layout and image format was changed. \
Upgrade requires reinstallation from initramfs.
FILESYSTEMS := squashfs
IMAGES := sysupgrade.bin emmc-gpt.img.gz
IMAGE/sysupgrade.bin := boot-scr | boot-img-ext4 | sysupgrade-tar kernel=$$$$@.bootimg | append-metadata
IMAGE/emmc-gpt.img.gz := methode-gpt-emmc |\
pad-to 1M | boot-scr | boot-img-ext4 | append-boot-part |\
pad-to 33M | append-rootfs |\
gzip
BOOT_SCRIPT := udpu
endef
define Device/methode_udpu
$(call Device/Default-arm64)
$(call Device/eMMC-methode)
$(call Device/FitImage)
DEVICE_VENDOR := Methode
DEVICE_MODEL := micro-DPU (uDPU)
DEVICE_DTS := armada-3720-uDPU
KERNEL_LOADADDR := 0x00800000
DEVICE_PACKAGES += f2fs-tools fdisk kmod-i2c-pxa kmod-hwmon-lm75 kmod-dsa-mv88e6xxx
DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(2)
FILESYSTEMS := targz
IMAGES := firmware.tgz
IMAGE/firmware.tgz := boot-scr | boot-img-ext4 | uDPU-firmware | append-metadata
BOOT_SCRIPT := udpu
endef
TARGET_DEVICES += methode_udpu
target/linux/mvebu/image/udpu.bootscript
+51 -10
View File
@@ -8,26 +8,67 @@ gpio clear 12; gpio clear 40; gpio clear 45;
# Find eMMC device,
if mmc dev 0; then
setenv mmcdev 0
setenv rootdev 'root=/dev/mmcblk0p3'
elif mmc dev 1; then
setenv mmcdev 1
setenv rootdev 'root=/dev/mmcblk1p3'
fi
# Check if bootactive variable exists and if not, default to 1
if test -z "${bootactive}"; then
setenv bootactive 1
fi
# Check if bootcount variable exists and if not, default to 0
if test -z "${bootcount}"; then
setenv bootcount 0
fi
if itest ${bootcount} > 2; then
if itest ${bootactive} == 2; then
setenv bootactive 1
else
setenv bootactive 2
fi
setenv bootcount 0
fi
# Find A/B firmware to boot
if itest ${bootactive} == 2; then
setenv kernelpart 3
setenv rootfspart 4
else
setenv kernelpart 1
setenv rootfspart 2
fi
setenv rootdev 'root=/dev/mmcblk'${mmcdev}'p'${rootfspart}
# Set the variables if necessary
if test ${kernel_addr_r}; then
setenv kernel_addr_r 0x5000000
fi
setenv console 'rootfs_mount_options.compress_algorithm=zstd'
setenv bootargs ${console} $rootdev rw rootwait
echo 'Booting firmware:' ${bootactive}
load mmc ${mmcdev}:1 ${kernel_addr_r} Image
if itest ${bootcount} == 0; then
setenv bootcount 1
elif itest ${bootcount} == 1; then
setenv bootcount 2
elif itest ${bootcount} == 2; then
setenv bootcount 3
else
setenv bootcount 4
fi
env save
setenv bootargs $rootdev rootwait fstools_overlay_compression_type=zstd
load mmc ${mmcdev}:${kernelpart} ${kernel_addr_r} Image
bootm ${kernel_addr_r}
# If the boot command fails, fallback to recovery image
echo '-- Boot failed, falling back to the recovery image --'
setenv bootargs $console
load mmc ${mmcdev}:2 ${kernel_addr_r} recovery.itb
bootm ${kernel_addr_r}
# If booting fails before kernel is loaded then reboot
# so the bootcount can trigger a slot switch.
echo 'Booting firmware:' ${bootactive} 'failed, rebooting'
reset
target/linux/qualcommax/dts/ipq5018-wrc-x3000gst2.dts
+405
View File
@@ -0,0 +1,405 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ipq5018.dtsi"
#include "ipq5018-ess.dtsi"
#include "ipq5018-qcn6122.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "ELECOM WRC-X3000GST2";
compatible = "elecom,wrc-x3000gst2", "qcom,ipq5018";
aliases {
serial0 = &blsp1_uart1;
led-boot = &led_power_green;
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_green;
label-mac-device = <&dp1>;
};
chosen {
bootargs-append = " root=/dev/ubiblock0_1 coherent_pool=2M";
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
switch-router {
label = "router";
gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
};
reset-button {
label = "reset";
gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps-button {
label = "wps";
gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led-0 {
gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WPS;
};
led_power_green: led-1 {
gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
};
led_power_red: led-2 {
gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
};
led-3 {
gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_5GHZ;
linux,default-trigger = "phy1radio";
};
led-4 {
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WLAN_5GHZ;
};
led-5 {
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_2GHZ;
linux,default-trigger = "phy0radio";
};
led-6 {
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WLAN_2GHZ;
};
led-7 {
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
};
};
};
&sleep_clk {
clock-frequency = <32000>;
};
&xo_board_clk {
clock-div = <4>;
clock-mult = <1>;
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
};
&crypto {
status = "okay";
};
&cryptobam {
status = "okay";
};
&prng {
status = "okay";
};
&qfprom {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
pinctrl-0 = <&qpic_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
nand-ecc-engine = <&qpic_nand>;
/* strength=8 breaks NAND I/O, use 4 instead */
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
partition-0-appsblenv {
label = "0:appsblenv";
nvmem-layout {
compatible = "u-boot,env";
env-size = <0x40000>;
macaddr_appsblenv_ethaddr: ethaddr {
#nvmem-cell-cells = <1>;
};
};
};
};
};
};
&switch {
status = "okay";
switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
qcom,port_phyinfo {
port@1 {
port_id = <1>;
mdiobus = <&mdio0>;
phy_address = <7>;
};
port@2 {
port_id = <2>;
forced-speed = <1000>;
forced-duplex = <1>;
};
};
};
&dp1 {
status = "okay";
label = "wan";
nvmem-cells = <&macaddr_appsblenv_ethaddr 3>;
nvmem-cell-names = "mac-address";
};
&dp2 {
status = "okay";
nvmem-cells = <&macaddr_appsblenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&mdio0 {
status = "okay";
};
&mdio1 {
status = "okay";
pinctrl-0 = <&mdio1_pins>, <&switch_reset_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
qca8337_0: ethernet-phy@0 {
reg = <0>;
};
qca8337_1: ethernet-phy@1 {
reg = <1>;
};
qca8337_2: ethernet-phy@2 {
reg = <2>;
};
qca8337_3: ethernet-phy@3 {
reg = <3>;
};
ethernet-switch@18 {
compatible = "qca,qca8337";
reg = <0x18>;
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&qca8337_0>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&qca8337_1>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-handle = <&qca8337_2>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-handle = <&qca8337_3>;
};
port@6 {
reg = <6>;
phy-mode = "sgmii";
ethernet = <&dp2>;
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&tlmm {
button_pins: button-state {
button-pins {
pins = "gpio22", "gpio38";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
switch-pins {
pins = "gpio14";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
led_pins: led-state {
pins = "gpio12", "gpio13", "gpio16", "gpio24",
"gpio25", "gpio26", "gpio28", "gpio46";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
mdio1_pins: mdio-state {
mdc-pins {
pins = "gpio36";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio-pins {
pins = "gpio37";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
qpic_pins: qpic-state {
clock-pins {
pins = "gpio9";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
cs-pins {
pins = "gpio8";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
data-pins {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "qspi_data";
drive-strength = <8>;
bias-disable;
};
};
serial_0_pins: uart0-state {
pins = "gpio20", "gpio21";
function = "blsp0_uart0";
bias-disable;
};
switch_reset_pins: switch-reset-state {
pins = "gpio39";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
&q6v5_wcss {
status = "okay";
boot-args = <0x2 4 2 18 0 0>; /* pcie:1, len:4, updid:2, reset:gpio18 */
};
&wifi {
status = "okay";
qcom,rproc = <&q6_wcss_pd1>;
qcom,ath11k-calibration-variant = "ELECOM-WRC-X3000GS2";
qcom,ath11k-fw-memory-mode = <1>;
qcom,bdf-addr = <0x4c400000>;
ieee80211-freq-limit = <2400000 2483000>;
};
&wifi1 {
status = "okay";
qcom,rproc = <&q6_wcss_pd2>;
qcom,userpd-subsys-name = "q6v5_wcss_userpd2";
qcom,ath11k-calibration-variant = "ELECOM-WRC-X3000GS2";
qcom,ath11k-fw-memory-mode = <1>;
qcom,bdf-addr = <0x4d100000>;
qcom,m3-dump-addr = <0x4df00000>;
ieee80211-freq-limit = <5150000 5730000>;
};
target/linux/qualcommax/image/ipq50xx.mk
+19
View File
@@ -68,6 +68,25 @@ define Device/elecom_wrc-x3000gs2
endef
TARGET_DEVICES += elecom_wrc-x3000gs2
define Device/elecom_wrc-x3000gst2
$(call Device/FitImageLzma)
DEVICE_VENDOR := ELECOM
DEVICE_MODEL := WRC-X3000GST2
DEVICE_DTS_CONFIG := config@mp03.3
SOC := ipq5018
KERNEL_IN_UBI := 1
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 52480k
NAND_SIZE := 128m
IMAGES += factory.bin
IMAGE/factory.bin := append-ubi | qsdk-ipq-factory-nand | \
mstc-header 4.04(XZP.0)b90 | elecom-product-header WRC-X3000GST2
DEVICE_PACKAGES := ath11k-firmware-ipq5018-qcn6122 \
ipq-wifi-elecom_wrc-x3000gs2
endef
TARGET_DEVICES += elecom_wrc-x3000gst2
define Device/glinet_gl-b3000
$(call Device/FitImage)
DEVICE_VENDOR := GL.iNet
target/linux/qualcommax/ipq50xx/base-files/etc/board.d/01_leds
+1
View File
@@ -11,6 +11,7 @@ board=$(board_name)
case "$board" in
cmcc,pz-l8|\
elecom,wrc-x3000gs2|\
elecom,wrc-x3000gst2|\
iodata,wn-dax3000gr)
ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan" "tx rx link_10 link_100 link_1000"
;;
target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network
+1
View File
@@ -8,6 +8,7 @@ ipq50xx_setup_interfaces()
local board="$1"
case $board in
elecom,wrc-x3000gs2|\
elecom,wrc-x3000gst2|\
iodata,wn-dax3000gr|\
linksys,mr5500|\
zyxel,scr50axe)
target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
+2
View File
@@ -17,6 +17,7 @@ case "$FIRMWARE" in
ath11k_remove_regdomain
;;
elecom,wrc-x3000gs2|\
elecom,wrc-x3000gst2|\
iodata,wn-dax3000gr|\
zyxel,scr50axe)
caldata_extract "0:art" 0x1000 0x20000
@@ -70,6 +71,7 @@ case "$FIRMWARE" in
ath11k_set_macflag
;;
elecom,wrc-x3000gs2|\
elecom,wrc-x3000gst2|\
iodata,wn-dax3000gr|\
zyxel,scr50axe)
caldata_extract "0:art" 0x26800 0x20000
target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/ieee80211/05-wifi-migrate
+1
View File
@@ -49,6 +49,7 @@ WIRELESS_CHANGED=false
case "$(board_name)" in
elecom,wrc-x3000gs2|\
elecom,wrc-x3000gst2|\
glinet,gl-b3000|\
iodata,wn-dax3000gr|\
linksys,mx2000|\
target/linux/qualcommax/ipq50xx/base-files/lib/upgrade/platform.sh
+1
View File
@@ -182,6 +182,7 @@ platform_do_upgrade() {
cmcc,mr3000d-ci|\
cmcc,pz-l8|\
elecom,wrc-x3000gs2|\
elecom,wrc-x3000gst2|\
iodata,wn-dax3000gr)
local delay
target/linux/realtek/base-files/etc/board.d/02_network
+1
View File
@@ -56,6 +56,7 @@ realtek_setup_macs()
edgecore,ecs4100-12ph|\
linksys,lgs310c|\
linksys,lgs328c|\
linksys,lgs328mpc-v2|\
linksys,lgs352c|\
netgear,gs108t-v3|\
netgear,gs110tpp-v1|\
target/linux/realtek/base-files/etc/init.d/hwmon_fancontrol
+43
View File
@@ -46,6 +46,46 @@ dlink_dgs_1250() {
echo 57000 > "$path_temp_hwmon/temp1_max_hyst"
}
linksys_lgs328mpc_v2() {
# The U-Boot of this device does not set up the LM63 fan controller for us, so we do it ourselves:
# Let LM63 steer high/low speed full automatically, vendor defaults are 40C low->high and 31C high->low.
# For this, reduce PMW frequency as otherwise the fan won't start at low speeds.
# Temperature point 1 is set to 1C and a hysteresis of 9C gives 1C - 9C = -8C - most likely always on.
# Temperature point 2 is set to 40C and a hysteresis of 9C gives 40C - 9C = 31C.
# Other points must be monotonic for the kernel to accept auto mode.
local path_to_hwmon="$(find /sys/bus/i2c/devices/0-004c/hwmon/ -type d -maxdepth 1 -mindepth 1 -name 'hwmon*')"
[ -n "$path_to_hwmon" ] || return 0
# switch to manual mode, otherwise LUT is not writable
echo 1 > "$path_to_hwmon/pwm1_enable"
# Set PWM Frequency to 22Hz as otherwise the fan doesn't spin at low duty cycles.
echo 22 > "$path_to_hwmon/pwm1_freq"
echo 1000 > "$path_to_hwmon/pwm1_auto_point1_temp" # 1°C
echo 128 > "$path_to_hwmon/pwm1_auto_point1_pwm" # 50% fan speed
echo 40000 > "$path_to_hwmon/pwm1_auto_point2_temp" # 40°C
echo 255 > "$path_to_hwmon/pwm1_auto_point2_pwm" # 100% fan speed
echo 41000 > "$path_to_hwmon/pwm1_auto_point3_temp" # monotonically increasing entries so the driver accepts this LUT
echo 255 > "$path_to_hwmon/pwm1_auto_point3_pwm"
echo 42000 > "$path_to_hwmon/pwm1_auto_point4_temp"
echo 255 > "$path_to_hwmon/pwm1_auto_point4_pwm"
echo 43000 > "$path_to_hwmon/pwm1_auto_point5_temp"
echo 255 > "$path_to_hwmon/pwm1_auto_point5_pwm"
echo 44000 > "$path_to_hwmon/pwm1_auto_point6_temp"
echo 255 > "$path_to_hwmon/pwm1_auto_point6_pwm"
echo 45000 > "$path_to_hwmon/pwm1_auto_point7_temp"
echo 255 > "$path_to_hwmon/pwm1_auto_point7_pwm"
echo 46000 > "$path_to_hwmon/pwm1_auto_point8_temp"
echo 255 > "$path_to_hwmon/pwm1_auto_point8_pwm"
# set temperature hysteresis to 9K
echo 9000 > "$path_to_hwmon/pwm1_auto_point_temp_hyst"
# switch to automatic, LUT driven mode
echo 2 > "$path_to_hwmon/pwm1_enable"
}
boot() {
case $(board_name) in
plasmacloud,esx28|\
@@ -55,5 +95,8 @@ boot() {
d-link,dgs-1250-28x)
dlink_dgs_1250
;;
linksys,lgs328mpc-v2)
linksys_lgs328mpc_v2
;;
esac
}
target/linux/realtek/base-files/lib/upgrade/platform.sh
+1
View File
@@ -41,6 +41,7 @@ platform_do_upgrade() {
default_do_upgrade "$1"
;;
linksys,lgs328c|\
linksys,lgs328mpc-v2|\
linksys,lgs352c)
nand_do_upgrade "$1"
;;
target/linux/realtek/dts/rtl9301_linksys_lgs328c.dts
+1 -140
View File
@@ -1,148 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
/dts-v1/;
#include "rtl930x.dtsi"
#include "rtl93xx_linksys_lgs3xxc_nand_common.dtsi"
#include "rtl9301_linksys_lgs328x_nand_common.dtsi"
/ {
compatible = "linksys,lgs328c", "realtek,rtl9301-soc";
model = "Linksys LGS328C";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
<0x20000000 0x10000000>; /* 256 MiB highmem */
};
};
&i2c_mst1 {
status = "okay";
i2c2: i2c@2 {
reg = <2>;
};
i2c3: i2c@3 {
reg = <3>;
};
i2c4: i2c@4 {
reg = <4>;
};
i2c5: i2c@5 {
reg = <5>;
};
};
&sfp0 {
i2c-bus = <&i2c2>;
};
&sfp1 {
i2c-bus = <&i2c3>;
};
&sfp2 {
i2c-bus = <&i2c4>;
};
&sfp3 {
i2c-bus = <&i2c5>;
};
&mdio_aux {
status = "okay";
gpio1: expander@0 {
compatible = "realtek,rtl8231";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio1 0 0 37>;
led-controller {
compatible = "realtek,rtl8231-leds";
status = "disabled";
};
};
};
&mdio_bus0 {
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
};
&mdio_bus1 {
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
};
&mdio_bus2 {
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, usxgmii)
SWITCH_PORT_SDS(9, 10, 2, usxgmii)
SWITCH_PORT_SDS(10, 11, 2, usxgmii)
SWITCH_PORT_SDS(11, 12, 2, usxgmii)
SWITCH_PORT_SDS(12, 13, 2, usxgmii)
SWITCH_PORT_SDS(13, 14, 2, usxgmii)
SWITCH_PORT_SDS(14, 15, 2, usxgmii)
SWITCH_PORT_SDS(15, 16, 2, usxgmii)
SWITCH_PORT_SDS(16, 17, 3, usxgmii)
SWITCH_PORT_SDS(17, 18, 3, usxgmii)
SWITCH_PORT_SDS(18, 19, 3, usxgmii)
SWITCH_PORT_SDS(19, 20, 3, usxgmii)
SWITCH_PORT_SDS(20, 21, 3, usxgmii)
SWITCH_PORT_SDS(21, 22, 3, usxgmii)
SWITCH_PORT_SDS(22, 23, 3, usxgmii)
SWITCH_PORT_SDS(23, 24, 3, usxgmii)
SWITCH_PORT_SFP(24, 25, 4, 0, 0)
SWITCH_PORT_SFP(25, 26, 6, 0, 1)
SWITCH_PORT_SFP(26, 27, 8, 0, 2)
SWITCH_PORT_SFP(27, 28, 9, 0, 3)
port@28 {
reg = <28>;
ethernet = <&ethernet0>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
target/linux/realtek/dts/rtl9301_linksys_lgs328mpc-v2.dts
+51
View File
@@ -0,0 +1,51 @@
// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
/dts-v1/;
#include "rtl9301_linksys_lgs328x_nand_common.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "linksys,lgs328mpc-v2", "realtek,rtl9301-soc";
model = "Linksys LGS328MPC v2";
leds {
compatible = "gpio-leds";
led_poe_mode: led-poe-mode {
function = "poe-mode";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
led_poe_max: led-poe-max {
function = "poe-max";
color = <LED_COLOR_ID_AMBER>;
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
led-mode {
label = "led-mode";
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
debounce-interval = <60>;
};
};
};
&i2c_mst1 {
i2c1: i2c@1 {
reg = <1>;
lm63@4c {
compatible = "national,lm63";
reg = <0x4c>;
#thermal-sensor-cells = <1>;
};
};
};
target/linux/realtek/dts/rtl9301_linksys_lgs328x_nand_common.dtsi
+129
View File
@@ -0,0 +1,129 @@
// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
/dts-v1/;
#include "rtl930x.dtsi"
#include "rtl93xx_linksys_lgs3xxc_nand_common.dtsi"
/ {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
<0x20000000 0x10000000>; /* 256 MiB highmem */
};
};
&i2c_mst1 {
status = "okay";
i2c2: i2c@2 { reg = <2>; };
i2c3: i2c@3 { reg = <3>; };
i2c4: i2c@4 { reg = <4>; };
i2c5: i2c@5 { reg = <5>; };
};
&sfp0 { i2c-bus = <&i2c2>; };
&sfp1 { i2c-bus = <&i2c3>; };
&sfp2 { i2c-bus = <&i2c4>; };
&sfp3 { i2c-bus = <&i2c5>; };
&mdio_aux {
status = "okay";
gpio1: expander@0 {
compatible = "realtek,rtl8231";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio1 0 0 37>;
led-controller {
compatible = "realtek,rtl8231-leds";
status = "disabled";
};
};
};
&mdio_bus0 {
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
};
&mdio_bus1 {
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
};
&mdio_bus2 {
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, usxgmii)
SWITCH_PORT_SDS(9, 10, 2, usxgmii)
SWITCH_PORT_SDS(10, 11, 2, usxgmii)
SWITCH_PORT_SDS(11, 12, 2, usxgmii)
SWITCH_PORT_SDS(12, 13, 2, usxgmii)
SWITCH_PORT_SDS(13, 14, 2, usxgmii)
SWITCH_PORT_SDS(14, 15, 2, usxgmii)
SWITCH_PORT_SDS(15, 16, 2, usxgmii)
SWITCH_PORT_SDS(16, 17, 3, usxgmii)
SWITCH_PORT_SDS(17, 18, 3, usxgmii)
SWITCH_PORT_SDS(18, 19, 3, usxgmii)
SWITCH_PORT_SDS(19, 20, 3, usxgmii)
SWITCH_PORT_SDS(20, 21, 3, usxgmii)
SWITCH_PORT_SDS(21, 22, 3, usxgmii)
SWITCH_PORT_SDS(22, 23, 3, usxgmii)
SWITCH_PORT_SDS(23, 24, 3, usxgmii)
SWITCH_PORT_SFP(24, 25, 4, 0, 0)
SWITCH_PORT_SFP(25, 26, 6, 0, 1)
SWITCH_PORT_SFP(26, 27, 8, 0, 2)
SWITCH_PORT_SFP(27, 28, 9, 0, 3)
port@28 {
reg = <28>;
ethernet = <&ethernet0>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c
+4 -8
View File
@@ -1560,6 +1560,7 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
{
struct rtl838x_switch_priv *priv;
struct device *dev = &pdev->dev;
const struct rtldsa_config *r;
u64 bpdu_mask;
int err = 0;
@@ -1579,11 +1580,12 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
/* Initialize access to RTL switch tables */
rtl_table_init();
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
r = device_get_match_data(&pdev->dev);
priv = devm_kzalloc(dev, struct_size(priv, msts, r->n_mst - 1), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->r = device_get_match_data(&pdev->dev);
priv->r = r;
priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
if (!priv->ds)
@@ -1620,12 +1622,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
return err;
}
priv->msts = devm_kcalloc(priv->dev,
priv->r->n_mst - 1, sizeof(struct rtldsa_mst),
GFP_KERNEL);
if (!priv->msts)
return -ENOMEM;
priv->wq = create_singlethread_workqueue("rtl83xx");
if (!priv->wq) {
dev_err(dev, "Error creating workqueue: %d\n", err);
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h
+6 -5
View File
@@ -1555,11 +1555,6 @@ struct rtl838x_switch_priv {
u16 intf_mtus[MAX_INTF_MTUS];
int intf_mtu_count[MAX_INTF_MTUS];
/**
* @msts: MSTI to HW MST slot allocations. index 0 is for HW slot 1 because CIST is
* not stored in @msts
*/
struct rtldsa_mst *msts;
struct delayed_work counters_work;
/**
@@ -1568,6 +1563,12 @@ struct rtl838x_switch_priv {
* periodically.
*/
struct mutex counters_lock;
/**
* @msts: MSTI to HW MST slot allocations. index 0 is for HW slot 1 because CIST is
* not stored in @msts
*/
struct rtldsa_mst msts[];
};
struct fdb_update_work {
target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c
+98 -27
View File
@@ -821,6 +821,16 @@ static int rtpcs_838x_sds_power(struct rtpcs_serdes *sds, bool power_on)
return ret;
}
static int rtpcs_838x_sds_deactivate(struct rtpcs_serdes *sds)
{
return rtpcs_838x_sds_power(sds, false);
}
static int rtpcs_838x_sds_activate(struct rtpcs_serdes *sds)
{
return rtpcs_838x_sds_power(sds, true);
}
/*
* RTL838X wrapper: after setting the MAC mode, SerDes 4-5 also need the
* companion INT_MODE_CTRL field written.
@@ -930,7 +940,7 @@ static int rtpcs_838x_setup_serdes(struct rtpcs_serdes *sds,
if (!rtpcs_838x_sds_is_hw_mode_supported(sds, hw_mode))
return -ENOTSUPP;
rtpcs_838x_sds_power(sds, false);
rtpcs_838x_sds_deactivate(sds);
/* take reset */
rtpcs_sds_write(sds, 0x0, 0x0, 0xc00);
@@ -948,7 +958,7 @@ static int rtpcs_838x_setup_serdes(struct rtpcs_serdes *sds,
/* release reset */
rtpcs_sds_write(sds, 0, 3, 0x7106);
rtpcs_838x_sds_power(sds, true);
rtpcs_838x_sds_activate(sds);
/*
* Run a switch queue reset after the first start of a SerDes. This recovers ports that
@@ -1794,7 +1804,6 @@ static int rtpcs_930x_sds_apply_ip_mode(struct rtpcs_serdes *sds,
* if this sequence should quit early in case of errors.
*/
rtpcs_930x_sds_set_power(sds, false);
ret = rtpcs_93xx_sds_set_ip_mode(sds, RTPCS_SDS_MODE_OFF);
if (ret < 0)
return ret;
@@ -1818,8 +1827,6 @@ static int rtpcs_930x_sds_apply_ip_mode(struct rtpcs_serdes *sds,
pr_err("%s: SDS %d could not reset state machine\n", __func__,
sds->id);
rtpcs_930x_sds_set_power(sds, true);
rtpcs_930x_sds_rx_reset(sds, hw_mode);
return 0;
}
@@ -1845,6 +1852,14 @@ static int rtpcs_930x_sds_set_mode(struct rtpcs_serdes *sds, enum rtpcs_sds_mode
break;
}
/*
* MAC-driven modes: release the IP mode force-lock so the MAC side
* takes over. deactivate forces IP=OFF; this undoes that.
*/
ret = rtpcs_sds_write_bits(sds, 0x1f, 0x09, 6, 6, 0);
if (ret)
return ret;
ret = rtpcs_93xx_sds_set_mac_mode(sds, hw_mode);
if (ret)
return ret;
@@ -1852,6 +1867,58 @@ static int rtpcs_930x_sds_set_mode(struct rtpcs_serdes *sds, enum rtpcs_sds_mode
return rtpcs_93xx_sds_apply_usxgmii_submode(sds, hw_mode);
}
static int rtpcs_930x_sds_deactivate(struct rtpcs_serdes *sds)
{
int ret;
/* Power down the SerDes core analog block. */
rtpcs_930x_sds_set_power(sds, false);
/* Force MAC and IP mode registers to OFF, leaving the SerDes inert. */
ret = rtpcs_93xx_sds_set_mac_mode(sds, RTPCS_SDS_MODE_OFF);
if (ret)
return ret;
ret = rtpcs_93xx_sds_set_ip_mode(sds, RTPCS_SDS_MODE_OFF);
if (ret)
return ret;
/* Disable fiber RX. */
ret = rtpcs_sds_write_bits(sds, 0x20, 2, 12, 12, 1);
if (ret)
return ret;
/* Power down the 1G PHY block. */
ret = rtpcs_sds_write_bits(sds, 0x02, MII_BMCR, 11, 11, 1); /* BMCR_PDOWN */
if (ret)
return ret;
/* Power down the 10G PHY block. */
return rtpcs_sds_write_bits(sds, 0x04, MII_BMCR, 11, 11, 1); /* BMCR_PDOWN */
}
static int rtpcs_930x_sds_activate(struct rtpcs_serdes *sds)
{
int ret;
/* Power up the SerDes core analog block and reset its RX path. */
rtpcs_930x_sds_set_power(sds, true);
rtpcs_930x_sds_rx_reset(sds, sds->hw_mode);
/* Enable fiber RX. */
ret = rtpcs_sds_write_bits(sds, 0x20, 2, 12, 12, 0);
if (ret)
return ret;
/* Power up the 1G PHY block. */
ret = rtpcs_sds_write_bits(sds, 0x02, MII_BMCR, 11, 11, 0); /* BMCR_PDOWN */
if (ret)
return ret;
/* Power up the 10G PHY block. */
return rtpcs_sds_write_bits(sds, 0x04, MII_BMCR, 11, 11, 0); /* BMCR_PDOWN */
}
static void rtpcs_930x_sds_tx_config(struct rtpcs_serdes *sds,
enum rtpcs_sds_mode hw_mode)
{
@@ -2734,18 +2801,6 @@ static int rtpcs_930x_sds_check_calibration(struct rtpcs_serdes *sds,
return 0;
}
static void rtpcs_930x_phy_enable_10g_1g(struct rtpcs_serdes *sds)
{
/* Enable 1GBit PHY */
rtpcs_sds_write_bits(sds, 0x02, MII_BMCR, 11, 11, 0x0); /* BMCR_PDOWN */
/* Enable 10GBit PHY */
rtpcs_sds_write_bits(sds, 0x04, MII_BMCR, 11, 11, 0x0); /* BMCR_PDOWN */
/* dal_longan_construct_mac_default_10gmedia_fiber */
rtpcs_sds_write_bits(sds, 0x1f, 11, 1, 1, 0x1);
}
static int rtpcs_930x_sds_10g_idle(struct rtpcs_serdes *sds)
{
struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
@@ -3003,8 +3058,7 @@ static int rtpcs_930x_setup_serdes(struct rtpcs_serdes *sds,
{
int calib_tries = 0, ret;
/* Turn Off Serdes */
ret = rtpcs_930x_sds_set_mode(sds, RTPCS_SDS_MODE_OFF);
ret = rtpcs_930x_sds_deactivate(sds);
if (ret < 0)
return ret;
@@ -3015,8 +3069,12 @@ static int rtpcs_930x_setup_serdes(struct rtpcs_serdes *sds,
/* Maybe use dal_longan_sds_init */
/* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
rtpcs_930x_phy_enable_10g_1g(sds);
/*
* dal_longan_construct_mac_default_10gmedia_fiber: set medium to fiber.
* TODO: this is unconditional regardless of hw_mode; needs mode-aware
* handling.
*/
rtpcs_sds_write_bits(sds, 0x1f, 11, 1, 1, 1);
/* Enable SDS in desired mode */
ret = rtpcs_930x_sds_set_mode(sds, hw_mode);
@@ -3025,8 +3083,7 @@ static int rtpcs_930x_setup_serdes(struct rtpcs_serdes *sds,
sds->hw_mode = hw_mode;
/* Enable Fiber RX */
rtpcs_sds_write_bits(sds, 0x20, 2, 12, 12, 0);
rtpcs_930x_sds_activate(sds);
if (hw_mode == RTPCS_SDS_MODE_QSGMII)
goto skip_cali;
@@ -3238,6 +3295,22 @@ static int rtpcs_931x_sds_set_mode(struct rtpcs_serdes *sds,
return rtpcs_93xx_sds_apply_usxgmii_submode(sds, hw_mode);
}
static int rtpcs_931x_sds_deactivate(struct rtpcs_serdes *sds)
{
int ret;
ret = rtpcs_931x_sds_power(sds, false);
if (ret)
return ret;
return rtpcs_931x_sds_set_mode(sds, RTPCS_SDS_MODE_OFF);
}
static int rtpcs_931x_sds_activate(struct rtpcs_serdes *sds)
{
return rtpcs_931x_sds_power(sds, true);
}
static void rtpcs_931x_sds_reset(struct rtpcs_serdes *sds)
{
u32 o_mode, f_bit;
@@ -3782,8 +3855,7 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_serdes *sds,
if (hw_mode == RTPCS_SDS_MODE_XSGMII)
return 0;
rtpcs_931x_sds_power(sds, false);
rtpcs_931x_sds_set_mode(sds, RTPCS_SDS_MODE_OFF);
rtpcs_931x_sds_deactivate(sds);
ret = rtpcs_931x_sds_config_hw_mode(sds, hw_mode);
if (ret < 0)
@@ -3813,14 +3885,13 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_serdes *sds,
return ret;
}
rtpcs_931x_sds_power(sds, true);
ret = rtpcs_931x_sds_set_mode(sds, hw_mode);
if (ret < 0)
return ret;
sds->hw_mode = hw_mode;
rtpcs_931x_sds_activate(sds);
return 0;
}
target/linux/realtek/image/rtl930x_nand.mk
+16 -4
View File
@@ -2,19 +2,16 @@
include ./common.mk
define Device/linksys_lgs328c
define Device/linksys_lgs328
$(Device/uimage-rt-loader)
SOC := rtl9301
IMAGE_SIZE := 29696k
KERNEL_SIZE := 10240k
DEVICE_VENDOR := Linksys
DEVICE_MODEL := LGS328C
BELKIN_MODEL := BKS-RTL93xx
BELKIN_HEADER := 0x07600001
LINKSYS_MODEL := 60412040
PAGESIZE := 2048
BLOCKSIZE := 128k
UBINIZE_OPTS := -E 5
KERNEL := \
$$(KERNEL) | \
pad-to $$(BLOCKSIZE)
@@ -24,4 +21,19 @@ define Device/linksys_lgs328c
sysupgrade-tar rootfs=$$$$@ | \
append-metadata
endef
define Device/linksys_lgs328c
$(Device/linksys_lgs328)
DEVICE_MODEL := LGS328C
LINKSYS_MODEL := 60412040
endef
TARGET_DEVICES += linksys_lgs328c
define Device/linksys_lgs328mpc-v2
$(Device/linksys_lgs328)
DEVICE_MODEL := LGS328MPC
DEVICE_VARIANT := v2
DEVICE_PACKAGES += kmod-hwmon-lm63
LINKSYS_MODEL := 60412060
endef
TARGET_DEVICES += linksys_lgs328mpc-v2
target/linux/rockchip/Makefile
+1 -2
View File
@@ -7,8 +7,7 @@ BOARDNAME:=Rockchip
FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
SUBTARGETS:=armv8
KERNEL_PATCHVER:=6.12
KERNEL_TESTING_PATCHVER:=6.18
KERNEL_PATCHVER:=6.18
define Target/Description
Build firmware image for Rockchip SoC devices.
target/linux/rockchip/armv8/config-6.12
-787
View File
@@ -1,787 +0,0 @@
CONFIG_64BIT=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PKEY_BITS=3
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SELECTS_KEXEC_FILE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANTS_EXECMEM_LATE=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARC_EMAC_CORE=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2658417=y
CONFIG_ARM64_ERRATUM_3117295=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PLATFORM_DEVICES=y
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=48
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
# CONFIG_ARM64_VA_BITS_52 is not set
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_MHU=y
CONFIG_ARM_MHU_V2=y
# CONFIG_ARM_MHU_V3 is not set
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
CONFIG_ARM_SCMI_CPUFREQ=y
# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_PERF_DOMAIN=y
CONFIG_ARM_SCMI_POWER_CONTROL=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCMI_PROTOCOL=y
# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_V3=y
# CONFIG_ARM_SMMU_V3_SVA is not set
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_BSG_COMMON=y
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NVME=y
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_BUFFER_HEAD=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CHARGER_GPIO=y
CONFIG_CHARGER_RK817=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3576=y
CONFIG_CLK_RK3588=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMA=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_SIZE_MBYTES=64
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CONTIG_ALLOC=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_ISOLATION=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRASH_DUMP=y
CONFIG_CRASH_RESERVE=y
CONFIG_CRC16=y
CONFIG_CRC64=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_T10DIF=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_CRYPTD=y
# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_POLYVAL=y
CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_NEON=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DEVMEM=y
# CONFIG_DEVPORT is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_CMA=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS_HELPERS=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DNOTIFY=y
CONFIG_DTC=y
CONFIG_DT_IDLE_GENPD=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DW_WATCHDOG=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_EMAC_ROCKCHIP=y
CONFIG_ENERGY_MODEL=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FANOTIFY=y
CONFIG_FHANDLE=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUNCTION_ALIGNMENT=4
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_ROCKCHIP=y
CONFIG_GPIO_SYSCON=y
CONFIG_GRO_CELLS=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_PCIE is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y
CONFIG_HWMON=y
CONFIG_HWSPINLOCK=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_ROCKCHIP=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_RK3X=y
CONFIG_IIO=y
# CONFIG_IIO_SCMI is not set
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INDIRECT_PIO=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_IOMMUFD is not set
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_IO_PGTABLE=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_SUPPORT=y
# CONFIG_IO_STRICT_DEVMEM is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_MSI_LIB=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JFFS2_ZLIB=y
CONFIG_KALLSYMS=y
CONFIG_KEXEC_CORE=y
CONFIG_KEXEC_FILE=y
CONFIG_KSM=y
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LIBCRC32C=y
CONFIG_LIBFDT=y
CONFIG_LOCALVERSION_AUTO=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_LRU_GEN_WALKS_MMU=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEDIATEK_GE_PHY=y
# CONFIG_MEDIATEK_GE_SOC_PHY is not set
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_KHADAS_MCU is not set
CONFIG_MFD_RK8XX=y
CONFIG_MFD_RK8XX_I2C=y
CONFIG_MFD_RK8XX_SPI=y
CONFIG_MFD_ROCKCHIP_MFPWM=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_CQHCI=y
CONFIG_MMC_DW=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_HI3798MV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MOTORCOMM_PHY=y
CONFIG_MQ_IOSCHED_DEADLINE=y
# CONFIG_MTD_CFI is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_FLAGS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DEVMEM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
CONFIG_NET_DSA_MT7530_MMIO=y
CONFIG_NET_DSA_REALTEK=y
CONFIG_NET_DSA_REALTEK_MDIO=y
CONFIG_NET_DSA_REALTEK_RTL8365MB=y
CONFIG_NET_DSA_REALTEK_RTL8366RB=y
CONFIG_NET_DSA_REALTEK_RTL8366RB_LEDS=y
CONFIG_NET_DSA_REALTEK_SMI=y
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_DSA_TAG_RTL4_A=y
CONFIG_NET_DSA_TAG_RTL8_4=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=256
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVME_CORE=y
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_MULTIPATH is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IOMMU=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_PME=y
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_DW=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_STUB=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PCS_XPCS=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PGTABLE_HAS_HUGE_LEAVES=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_ROCKCHIP_DP=y
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
CONFIG_PHY_ROCKCHIP_EMMC=y
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_PCIE=y
# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SCMI is not set
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PL330_DMA=y
CONFIG_PLATFORM_MHU=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_OPP=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_RESET=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_HWMON=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_VMCORE=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_ROCKCHIP_V4=y
# CONFIG_QFMT_V2 is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_QUOTA=y
CONFIG_QUOTACTL=y
CONFIG_RAID_ATTRS=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
# CONFIG_RAVE_SP_CORE is not set
CONFIG_RCU_TRACE=y
CONFIG_REALTEK_PHY=y
CONFIG_REALTEK_PHY_HWMON=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_SPI=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK808=y
CONFIG_RELOCATABLE=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
CONFIG_RFKILL_FULL=y
CONFIG_RFKILL_GPIO=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFS_ACCEL=y
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_ERRATUM_3568002=y
CONFIG_ROCKCHIP_ERRATUM_3588001=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_ROCKCHIP_MFPWM=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PWM_CAPTURE=y
CONFIG_ROCKCHIP_SARADC=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPS=y
CONFIG_RSEQ=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_RK808=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_NVMEM=y
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_CLUSTER=y
CONFIG_SCHED_MC=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_SCSI_SAS_ATTRS=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SAS_LIBSAS=y
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_HWMON=y
CONFIG_SCSI_UFS_ROCKCHIP=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_NR_UARTS=12
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_PCILIB=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=12
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIO=y
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_SFC=y
CONFIG_SPI_SPIDEV=y
CONFIG_SPLIT_PMD_PTLOCKS=y
CONFIG_SPLIT_PTE_PTLOCKS=y
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SRAM=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_STACKTRACE=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_STRICT_DEVMEM=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_SWAP is not set
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYNC_FILE=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYSFS_SYSCALL=y
# CONFIG_TEXTSEARCH is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_EMULATION=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_CLOCK=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set
CONFIG_TRANS_TABLE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_TYPEC=y
# CONFIG_TYPEC_ANX7411 is not set
CONFIG_TYPEC_FUSB302=y
# CONFIG_TYPEC_HD3SS3220 is not set
# CONFIG_TYPEC_MUX_FSA4480 is not set
# CONFIG_TYPEC_MUX_GPIO_SBU is not set
# CONFIG_TYPEC_MUX_IT5205 is not set
# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# CONFIG_TYPEC_MUX_PTN36502 is not set
# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set
# CONFIG_TYPEC_RT1719 is not set
# CONFIG_TYPEC_STUSB160X is not set
# CONFIG_TYPEC_TCPCI is not set
CONFIG_TYPEC_TCPM=y
# CONFIG_TYPEC_TPS6598X is not set
# CONFIG_TYPEC_WUSB3801 is not set
# CONFIG_UCLAMP_TASK is not set
# CONFIG_UEVENT_HELPER is not set
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_HOST=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_PHY=y
CONFIG_USB_ROLE_SWITCH=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_ONBOARD_DEV=y
# CONFIG_USB_ONBOARD_DEV_USB5744 is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_VDSO_GETRANDOM=y
# CONFIG_VIRTIO_MENU is not set
CONFIG_VMAP_STACK=y
CONFIG_VMCORE_INFO=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XARRAY_MULTI=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
target/linux/rockchip/patches-6.12/001-01-v6.13-arm64-dts-rockchip-Split-up-RK3588-s-PCIe-pinctrls.patch
-444
View File
@@ -1,444 +0,0 @@
From 4294e32111781b3de4d73b944cbd1bc1662a9a7a Mon Sep 17 00:00:00 2001
From: Sam Edwards <cfsworks@gmail.com>
Date: Wed, 11 Sep 2024 19:50:30 -0700
Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
These pinctrls manage the low-speed PCIe signals:
- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
request that external clock-generation circuitry provide a clock.
- PERST#: An input on the RK3588 in EP mode, used to detect a reset
signal from the RC. In RC mode, the hardware does not use this signal:
Linux itself generates it by putting the pin in GPIO mode.
- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
Each of these signals serves a distinct purpose, and more importantly,
PERST# should not be muxed when the RK3588 is in the RC role. Bundling
them together in pinctrl groups prevents proper use: indeed, almost none
of the current board-specific .dts files make any use of them.
(Exception: Rock 5A recently had a patch land that misuses _pins; this
patch corrects that.)
However, on some RK3588 boards, the PCIe 3 controller will indefinitely
stall the boot if CLKREQ# is not muxed (details in the next patch).
This patch unbundles the signals to allow them to be used.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
@@ -1612,23 +1612,43 @@
pcie20x1 {
/omit-if-no-ref/
- pcie20x1m0_pins: pcie20x1m0-pins {
+ pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
rockchip,pins =
/* pcie20x1_2_clkreqn_m0 */
- <3 RK_PC7 4 &pcfg_pull_none>,
+ <3 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m0_perstn: pcie20x1m0-perstn {
+ rockchip,pins =
/* pcie20x1_2_perstn_m0 */
- <3 RK_PD1 4 &pcfg_pull_none>,
+ <3 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m0_waken: pcie20x1m0-waken {
+ rockchip,pins =
/* pcie20x1_2_waken_m0 */
<3 RK_PD0 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie20x1m1_pins: pcie20x1m1-pins {
+ pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
rockchip,pins =
/* pcie20x1_2_clkreqn_m1 */
- <4 RK_PB7 4 &pcfg_pull_none>,
+ <4 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m1_perstn: pcie20x1m1-perstn {
+ rockchip,pins =
/* pcie20x1_2_perstn_m1 */
- <4 RK_PC1 4 &pcfg_pull_none>,
+ <4 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m1_waken: pcie20x1m1-waken {
+ rockchip,pins =
/* pcie20x1_2_waken_m1 */
<4 RK_PC0 4 &pcfg_pull_none>;
};
@@ -1654,52 +1674,127 @@
pcie30x1 {
/omit-if-no-ref/
- pcie30x1m0_pins: pcie30x1m0-pins {
+ pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m0 */
- <0 RK_PC0 12 &pcfg_pull_none>,
+ <0 RK_PC0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m0 */
- <0 RK_PC5 12 &pcfg_pull_none>,
+ <0 RK_PC5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_0_waken: pcie30x1m0-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m0 */
- <0 RK_PC4 12 &pcfg_pull_none>,
+ <0 RK_PC4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m0 */
- <0 RK_PB5 12 &pcfg_pull_none>,
+ <0 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m0 */
- <0 RK_PB7 12 &pcfg_pull_none>,
+ <0 RK_PB7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m0_1_waken: pcie30x1m0-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m0 */
<0 RK_PB6 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x1m1_pins: pcie30x1m1-pins {
+ pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m1 */
- <4 RK_PA3 4 &pcfg_pull_none>,
+ <4 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m1 */
- <4 RK_PA5 4 &pcfg_pull_none>,
+ <4 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_0_waken: pcie30x1m1-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m1 */
- <4 RK_PA4 4 &pcfg_pull_none>,
+ <4 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m1 */
- <4 RK_PA0 4 &pcfg_pull_none>,
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m1 */
- <4 RK_PA2 4 &pcfg_pull_none>,
+ <4 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_1_waken: pcie30x1m1-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m1 */
<4 RK_PA1 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x1m2_pins: pcie30x1m2-pins {
+ pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
rockchip,pins =
/* pcie30x1_0_clkreqn_m2 */
- <1 RK_PB5 4 &pcfg_pull_none>,
+ <1 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
+ rockchip,pins =
/* pcie30x1_0_perstn_m2 */
- <1 RK_PB4 4 &pcfg_pull_none>,
+ <1 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_0_waken: pcie30x1m2-0-waken {
+ rockchip,pins =
/* pcie30x1_0_waken_m2 */
- <1 RK_PB3 4 &pcfg_pull_none>,
+ <1 RK_PB3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
+ rockchip,pins =
/* pcie30x1_1_clkreqn_m2 */
- <1 RK_PA0 4 &pcfg_pull_none>,
+ <1 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
+ rockchip,pins =
/* pcie30x1_1_perstn_m2 */
- <1 RK_PA7 4 &pcfg_pull_none>,
+ <1 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_1_waken: pcie30x1m2-1-waken {
+ rockchip,pins =
/* pcie30x1_1_waken_m2 */
<1 RK_PA1 4 &pcfg_pull_none>;
};
@@ -1721,45 +1816,85 @@
pcie30x2 {
/omit-if-no-ref/
- pcie30x2m0_pins: pcie30x2m0-pins {
+ pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m0 */
- <0 RK_PD1 12 &pcfg_pull_none>,
+ <0 RK_PD1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m0_perstn: pcie30x2m0-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m0 */
- <0 RK_PD4 12 &pcfg_pull_none>,
+ <0 RK_PD4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m0_waken: pcie30x2m0-waken {
+ rockchip,pins =
/* pcie30x2_waken_m0 */
<0 RK_PD2 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m1_pins: pcie30x2m1-pins {
+ pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m1 */
- <4 RK_PA6 4 &pcfg_pull_none>,
+ <4 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_perstn: pcie30x2m1-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m1 */
- <4 RK_PB0 4 &pcfg_pull_none>,
+ <4 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_waken: pcie30x2m1-waken {
+ rockchip,pins =
/* pcie30x2_waken_m1 */
<4 RK_PA7 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m2_pins: pcie30x2m2-pins {
+ pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m2 */
- <3 RK_PD2 4 &pcfg_pull_none>,
+ <3 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_perstn: pcie30x2m2-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m2 */
- <3 RK_PD4 4 &pcfg_pull_none>,
+ <3 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_waken: pcie30x2m2-waken {
+ rockchip,pins =
/* pcie30x2_waken_m2 */
<3 RK_PD3 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x2m3_pins: pcie30x2m3-pins {
+ pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
rockchip,pins =
/* pcie30x2_clkreqn_m3 */
- <1 RK_PD7 4 &pcfg_pull_none>,
+ <1 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m3_perstn: pcie30x2m3-perstn {
+ rockchip,pins =
/* pcie30x2_perstn_m3 */
- <1 RK_PB7 4 &pcfg_pull_none>,
+ <1 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m3_waken: pcie30x2m3-waken {
+ rockchip,pins =
/* pcie30x2_waken_m3 */
<1 RK_PB6 4 &pcfg_pull_none>;
};
@@ -1774,45 +1909,85 @@
pcie30x4 {
/omit-if-no-ref/
- pcie30x4m0_pins: pcie30x4m0-pins {
+ pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m0 */
- <0 RK_PC6 12 &pcfg_pull_none>,
+ <0 RK_PC6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m0_perstn: pcie30x4m0-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m0 */
- <0 RK_PD0 12 &pcfg_pull_none>,
+ <0 RK_PD0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m0_waken: pcie30x4m0-waken {
+ rockchip,pins =
/* pcie30x4_waken_m0 */
<0 RK_PC7 12 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m1_pins: pcie30x4m1-pins {
+ pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m1 */
- <4 RK_PB4 4 &pcfg_pull_none>,
+ <4 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m1_perstn: pcie30x4m1-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m1 */
- <4 RK_PB6 4 &pcfg_pull_none>,
+ <4 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m1_waken: pcie30x4m1-waken {
+ rockchip,pins =
/* pcie30x4_waken_m1 */
<4 RK_PB5 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m2_pins: pcie30x4m2-pins {
+ pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m2 */
- <3 RK_PC4 4 &pcfg_pull_none>,
+ <3 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m2_perstn: pcie30x4m2-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m2 */
- <3 RK_PC6 4 &pcfg_pull_none>,
+ <3 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m2_waken: pcie30x4m2-waken {
+ rockchip,pins =
/* pcie30x4_waken_m2 */
<3 RK_PC5 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
- pcie30x4m3_pins: pcie30x4m3-pins {
+ pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
rockchip,pins =
/* pcie30x4_clkreqn_m3 */
- <1 RK_PB0 4 &pcfg_pull_none>,
+ <1 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m3_perstn: pcie30x4m3-perstn {
+ rockchip,pins =
/* pcie30x4_perstn_m3 */
- <1 RK_PB2 4 &pcfg_pull_none>,
+ <1 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m3_waken: pcie30x4m3-waken {
+ rockchip,pins =
/* pcie30x4_waken_m3 */
<1 RK_PB1 4 &pcfg_pull_none>;
};
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -311,7 +311,7 @@
};
&pcie2x1l2 {
- pinctrl-0 = <&pcie20x1m0_pins>;
+ pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
pinctrl-names = "default";
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_wf>;
@@ -329,6 +329,10 @@
pow_en: pow-en {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
+
+ pcie2_reset: pcie2-reset {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
power {
target/linux/rockchip/patches-6.12/001-02-v6.13-arm64-dts-rockchip-Add-HDMI0-node-to-rk3588.patch
-61
View File
@@ -1,61 +0,0 @@
From d7bb71e69f58c1b3665a9f926bf8d3855111bf8e Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Sat, 19 Oct 2024 13:12:10 +0300
Subject: arm64: dts: rockchip: Add HDMI0 node to rk3588
Add support for the HDMI0 output port found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1369,6 +1369,47 @@
status = "disabled";
};
+ hdmi0: hdmi@fde80000 {
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
+ reg = <0x0 0xfde80000 0x0 0x20000>;
+ clocks = <&cru PCLK_HDMITX0>,
+ <&cru CLK_HDMITX0_EARC>,
+ <&cru CLK_HDMITX0_REF>,
+ <&cru MCLK_I2S5_8CH_TX>,
+ <&cru CLK_HDMIHDP0>,
+ <&cru HCLK_VO1>;
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
+ phys = <&hdptxphy_hdmi0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda>;
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo-grf = <&vo1_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi0_in: port@0 {
+ reg = <0>;
+ };
+
+ hdmi0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
qos_gpu_m0: qos@fdf35000 {
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;
target/linux/rockchip/patches-6.12/001-03-v6.15-arm64-dts-rockchip-Use-dma-noncoherent-in-base-RK358.patch
-51
View File
@@ -1,51 +0,0 @@
From 33b561eb66f1e271f2899e103c857d20425076f4 Mon Sep 17 00:00:00 2001
From: Dragan Simic <dsimic@manjaro.org>
Date: Wed, 8 Jan 2025 05:26:45 +0100
Subject: arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi
The preferred way to denote hardware with non-coherent DMA is to use the
"dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS
levels, [1] instead of relying on the compatibles to handle hardware errata,
in this case the Rockchip 3588001 errata. [2]
Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi,
which also goes along with adding initial support for the Rockchip RK3582 SoC
variant, with its separate compatible. [2][3]
[1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
[2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/
[3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/
Cc: Marc Zyngier <maz@kernel.org>
Cc: FUKAUMI Naoki <naoki@radxa.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -2020,6 +2020,7 @@
<0x0 0xfe680000 0 0x100000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-controller;
+ dma-noncoherent;
mbi-alias = <0x0 0xfe610000>;
mbi-ranges = <424 56>;
msi-controller;
@@ -2031,6 +2032,7 @@
its0: msi-controller@fe640000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0xfe640000 0x0 0x20000>;
+ dma-noncoherent;
msi-controller;
#msi-cells = <1>;
};
@@ -2038,6 +2040,7 @@
its1: msi-controller@fe660000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0xfe660000 0x0 0x20000>;
+ dma-noncoherent;
msi-controller;
#msi-cells = <1>;
};
target/linux/rockchip/patches-6.12/001-04-v6.15-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch
-28
View File
@@ -1,28 +0,0 @@
From d0f17738778c12be629ba77ff00c43c3e9eb8428 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 4 Feb 2025 14:40:07 +0200
Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI0 PHY.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -2813,6 +2813,7 @@
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
clock-names = "ref", "apb";
+ #clock-cells = <0>;
#phy-cells = <0>;
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
target/linux/rockchip/patches-6.12/001-05-v6.15-arm64-dts-rockchip-Add-HDMI0-PHY-PLL-clock-source-to.patch
-38
View File
@@ -1,38 +0,0 @@
From eb4262203d7d85eb7b6f2696816db272e41f5464 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 4 Feb 2025 14:40:08 +0200
Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on
RK3588
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
For now only HDMI0 output is supported, hence add the related PLL clock.
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1261,14 +1261,16 @@
<&cru DCLK_VOP1>,
<&cru DCLK_VOP2>,
<&cru DCLK_VOP3>,
- <&cru PCLK_VOP_ROOT>;
+ <&cru PCLK_VOP_ROOT>,
+ <&hdptxphy_hdmi0>;
clock-names = "aclk",
"hclk",
"dclk_vp0",
"dclk_vp1",
"dclk_vp2",
"dclk_vp3",
- "pclk_vop";
+ "pclk_vop",
+ "pll_hdmiphy0";
iommus = <&vop_mmu>;
power-domains = <&power RK3588_PD_VOP>;
rockchip,grf = <&sys_grf>;
target/linux/rockchip/patches-6.12/001-06-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch
-44
View File
@@ -1,44 +0,0 @@
From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding@rock-chips.com>
Date: Thu, 6 Feb 2025 11:03:30 +0800
Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
and eDP Link. Therefore, it is better to name it hdptxphy0 other than
hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
[added armsom-sige7, where hdmi-support was added recently and also
the hdptxphy0-as-dclk source I just added]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1262,7 +1262,7 @@
<&cru DCLK_VOP2>,
<&cru DCLK_VOP3>,
<&cru PCLK_VOP_ROOT>,
- <&hdptxphy_hdmi0>;
+ <&hdptxphy0>;
clock-names = "aclk",
"hclk",
"dclk_vp0",
@@ -1387,7 +1387,7 @@
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "avp", "cec", "earc", "main", "hpd";
- phys = <&hdptxphy_hdmi0>;
+ phys = <&hdptxphy0>;
pinctrl-names = "default";
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda>;
@@ -2810,7 +2810,7 @@
#dma-cells = <1>;
};
- hdptxphy_hdmi0: phy@fed60000 {
+ hdptxphy0: phy@fed60000 {
compatible = "rockchip,rk3588-hdptx-phy";
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
target/linux/rockchip/patches-6.12/001-07-v6.15-arm64-dts-rockchip-Add-PHY-node-for-HDMI1-TX-port-on.patch
-52
View File
@@ -1,52 +0,0 @@
From ea97212a0f66b7bd71c23c12f781f1770dd6fcff Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Wed, 11 Dec 2024 01:06:15 +0200
Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
In preparation to enable the second HDMI output port found on RK3588
SoC, add the related PHY node. This requires a GRF, hence add the
dependent node as well.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -67,6 +67,11 @@
};
};
+ hdptxphy1_grf: syscon@fd5e4000 {
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+ reg = <0x0 0xfd5e4000 0x0 0x100>;
+ };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -395,6 +400,22 @@
};
};
+ hdptxphy1: phy@fed70000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed70000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
+ clock-names = "ref", "apb";
+ #phy-cells = <0>;
+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
+ <&cru SRST_HDPTX1_LCPLL>;
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+ "lcpll";
+ rockchip,grf = <&hdptxphy1_grf>;
+ status = "disabled";
+ };
+
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;
target/linux/rockchip/patches-6.12/001-08-v6.15-arm64-dts-rockchip-Add-HDMI1-node-on-RK3588.patch
-63
View File
@@ -1,63 +0,0 @@
From bed6964e779b5853de042da14320edf9f79506fe Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Wed, 11 Dec 2024 01:06:16 +0200
Subject: arm64: dts: rockchip: Add HDMI1 node on RK3588
Add support for the second HDMI TX port found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-3-02cdca22ff68@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -140,6 +140,47 @@
status = "disabled";
};
+ hdmi1: hdmi@fdea0000 {
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
+ reg = <0x0 0xfdea0000 0x0 0x20000>;
+ clocks = <&cru PCLK_HDMITX1>,
+ <&cru CLK_HDMITX1_EARC>,
+ <&cru CLK_HDMITX1_REF>,
+ <&cru MCLK_I2S6_8CH_TX>,
+ <&cru CLK_HDMIHDP1>,
+ <&cru HCLK_VO1>;
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
+ phys = <&hdptxphy1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
+ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo-grf = <&vo1_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi1_in: port@0 {
+ reg = <0>;
+ };
+
+ hdmi1_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
target/linux/rockchip/patches-6.12/001-09-v6.15-arm64-dts-rockchip-Enable-HDMI1-PHY-clk-provider-on-.patch
-27
View File
@@ -1,27 +0,0 @@
From aadaa27956e3430217d9e6b8af5880e39b05b961 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Sun, 23 Feb 2025 11:31:39 +0200
Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI1 PHY.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -446,6 +446,7 @@
reg = <0x0 0xfed70000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
clock-names = "ref", "apb";
+ #clock-cells = <0>;
#phy-cells = <0>;
resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
<&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
target/linux/rockchip/patches-6.12/001-10-v6.15-arm64-dts-rockchip-Add-HDMI1-PHY-PLL-clock-source-to.patch
-48
View File
@@ -1,48 +0,0 @@
From b2e668a60ed866ba960acb5310d1fb6bf81d154f Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Sun, 23 Feb 2025 11:31:40 +0200
Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on
RK3588
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
The HDMI1 PHY PLL clock source cannot be added directly to vop node in
rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
optional feature and its PHY node belongs to a separate (extra) DT file.
Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
clocks & clock-names properties in the extra DT file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -509,3 +509,24 @@
status = "disabled";
};
};
+
+&vop {
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&cru PCLK_VOP_ROOT>,
+ <&hdptxphy0>,
+ <&hdptxphy1>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "pclk_vop",
+ "pll_hdmiphy0",
+ "pll_hdmiphy1";
+};
target/linux/rockchip/patches-6.12/001-11-v6.15-arm64-dts-rockchip-Add-HDMI-audio-outputs-for-rk3588.patch
-91
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@@ -1,91 +0,0 @@
From b8c6c136971c0e9750eec89f367529b2854d3a3c Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Mon, 17 Feb 2025 16:47:41 -0500
Subject: arm64: dts: rockchip: Add HDMI audio outputs for rk3588
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node
as CODEC and the i2s5 device as CPU.
Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is
i2s6, but only added in the rk3588-extra.dtsi device tree as the second
TX HDMI port is not available on base versions of the SoC.
The simple-audio-card,mclk-fs value is set to 128 as it is done in
the downstream driver.
The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so
that they can be used as audio codec nodes.
Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger Haikou
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node")
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -382,6 +382,22 @@
};
};
+ hdmi0_sound: hdmi0-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "hdmi0";
+ status = "disabled";
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi0>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s5_8ch>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
@@ -1396,6 +1412,7 @@
reset-names = "ref", "hdp";
rockchip,grf = <&sys_grf>;
rockchip,vo-grf = <&vo1_grf>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -7,6 +7,22 @@
#include "rk3588-extra-pinctrl.dtsi"
/ {
+ hdmi1_sound: hdmi1-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "hdmi1";
+ status = "disabled";
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi1>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s6_8ch>;
+ };
+ };
+
usb_host1_xhci: usb@fc400000 {
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
@@ -165,6 +181,7 @@
reset-names = "ref", "hdp";
rockchip,grf = <&sys_grf>;
rockchip,vo-grf = <&vo1_grf>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {
target/linux/rockchip/patches-6.12/001-12-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch
-46
View File
@@ -1,46 +0,0 @@
From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 20 Feb 2025 19:58:11 +0100
Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
RK3588
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.
This means the system might run into a failure state hanging the
whole system for the following use cases:
* if the GPU driver is being probed late (e.g. build as a
module and firmware is not in initramfs), the regulator
might already have been disabled. In that case the power
domain is enabled before the regulator.
* unbinding the GPU driver will disable the PM domain and
the regulator. When the driver is bound again, the PM
domain will be enabled before the regulator and error
appears.
Avoid this by adding an explicit regulator dependency to the
power domain.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -880,7 +880,7 @@
};
};
/* These power domains are grouped by VD_GPU */
- power-domain@RK3588_PD_GPU {
+ pd_gpu: power-domain@RK3588_PD_GPU {
reg = <RK3588_PD_GPU>;
clocks = <&cru CLK_GPU>,
<&cru CLK_GPU_COREGROUP>,
target/linux/rockchip/patches-6.12/001-13-v6.15-arm64-dts-rockchip-Add-device-tree-support-for-HDMI-.patch
-88
View File
@@ -1,88 +0,0 @@
From 0327238991ba2d1de25e1116b1c064f433e45b8d Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Fri, 7 Mar 2025 12:18:56 +0300
Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller
Add device tree support for Synopsys DesignWare HDMI RX
Controller.
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Link: https://lore.kernel.org/r/20250307091857.646581-2-dmitry.osipenko@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -23,6 +23,30 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * The 4k HDMI capture controller works only with 32bit
+ * phys addresses and doesn't support IOMMU. HDMI RX CMA
+ * must be reserved below 4GB.
+ * The size of 160MB was determined as follows:
+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
+ * To ensure sufficient support for practical use-cases,
+ * we doubled the 66MB value.
+ */
+ hdmi_receiver_cma: hdmi-receiver-cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
+ size = <0x0 (160 * 0x100000)>; /* 160MiB */
+ alignment = <0x0 0x40000>; /* 64K */
+ no-map;
+ status = "disabled";
+ };
+ };
+
usb_host1_xhci: usb@fc400000 {
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
@@ -198,6 +222,37 @@
};
};
+ hdmi_receiver: hdmi_receiver@fdee0000 {
+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
+ reg = <0x0 0xfdee0000 0x0 0x6000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "cec", "hdmi", "dma";
+ clocks = <&cru ACLK_HDMIRX>,
+ <&cru CLK_HDMIRX_AUD>,
+ <&cru CLK_CR_PARA>,
+ <&cru PCLK_HDMIRX>,
+ <&cru CLK_HDMIRX_REF>,
+ <&cru PCLK_S_HDMIRX>,
+ <&cru HCLK_VO1>;
+ clock-names = "aclk",
+ "audio",
+ "cr_para",
+ "pclk",
+ "ref",
+ "hclk_s_hdmirx",
+ "hclk_vo1";
+ memory-region = <&hdmi_receiver_cma>;
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
+ reset-names = "axi", "apb", "ref", "biu";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo1-grf = <&vo1_grf>;
+ status = "disabled";
+ };
+
pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
target/linux/rockchip/patches-6.12/001-14-v6.19-arm64-dts-rockchip-add-eMMC-CQE-support-for-rk3588.patch
-25
View File
@@ -1,25 +0,0 @@
From 9d856aa1c81930a5d8df0e29d6cb0faa3fa87206 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Fri, 31 Oct 2025 16:58:24 +0100
Subject: [PATCH] arm64: dts: rockchip: add eMMC CQE support for rk3588
The RK3588 eMMC controller supports CQE, so add the missing
DT flag.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://patch.msgid.link/20251031-rockchip-emmc-cqe-support-v2-2-958171f5edad@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1935,6 +1935,7 @@
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;
reset-names = "core", "bus", "axi", "block", "timer";
+ supports-cqe;
status = "disabled";
};
target/linux/rockchip/patches-6.12/002-01-v6.13-arm64-dts-rockchip-add-and-enable-gpu-node-for-Radxa.patch
-25
View File
@@ -1,25 +0,0 @@
From a98053d098c4ad91a45a3a55604d9574dfc6ffdb Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Sat, 19 Oct 2024 02:50:08 +0000
Subject: arm64: dts: rockchip: add and enable gpu node for Radxa ROCK 5A
add gpu node to make it usable on Radxa ROCK 5A.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20241019025008.852-1-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -166,6 +166,11 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
target/linux/rockchip/patches-6.12/002-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5a.patch
-90
View File
@@ -1,90 +0,0 @@
From f57a8daf6bbd8e71f16693ad6d8421cb881c7fe0 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 22 Oct 2024 19:04:42 +0300
Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5a
Add the necessary DT changes to enable HDMI0 on Radxa ROCK 5A.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20241022-rk3588-hdmi0-dt-v3-1-3cc981e89afb@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588s.dtsi"
/ {
@@ -35,6 +36,17 @@
stdout-path = "serial2:1500000n8";
};
+ hdmi0-con {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi0_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -302,6 +314,31 @@
status = "okay";
};
+&hdmi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec
+ &hdmim1_tx0_hpd
+ &hdmim0_tx0_scl
+ &hdmim0_tx0_sda>;
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&hdmi0_out {
+ hdmi0_out_con: endpoint {
+ remote-endpoint = <&hdmi0_con_in>;
+ };
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
/* RTL8211F */
@@ -794,3 +831,18 @@
&usb_host2_xhci {
status = "okay";
};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
target/linux/rockchip/patches-6.12/002-03-v6.13-arm64-dts-rockchip-sort-rk3588s-rock5a-properly-in-M.patch
-21
View File
@@ -1,21 +0,0 @@
From 9f3360b42bb5b0c99073827a3dd81d2568b2a4ed Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Mon, 28 Oct 2024 07:23:44 +0000
Subject: arm64: dts: rockchip: sort rk3588s-rock5a properly in Makefile
sort target dtb files properly in Makefile for rockchip.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20241028072344.1514-1-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -151,6 +151,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-i
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
target/linux/rockchip/patches-6.12/002-04-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch
-72
View File
@@ -1,72 +0,0 @@
From 5c96e63301978f4657c9082c55a066763c8db7b1 Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx6244@gmail.com>
Date: Sat, 5 Oct 2024 22:40:12 +0200
Subject: arm64: dts: rockchip: adapt regulator nodenames to preferred form
The preferred nodename for fixed-regulators has changed to
pattern: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$'
Fix all Rockchip DT regulator nodenames.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/0ae40493-93e9-40cd-9ca9-990ae064f21a@gmail.com
[adapted rebased on top of a number of other changes and included
neu6a-wifi + wolfvision-pf5-io-expander overlays]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -68,7 +68,7 @@
#cooling-cells = <2>;
};
- vcc12v_dcin: vcc12v-dcin-regulator {
+ vcc12v_dcin: regulator-vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
@@ -77,7 +77,7 @@
regulator-max-microvolt = <12000000>;
};
- vcc3v3_wf: vcc3v3-wf-regulator {
+ vcc3v3_wf: regulator-vcc3v3-wf {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_wf";
regulator-min-microvolt = <3300000>;
@@ -89,7 +89,7 @@
vin-supply = <&vcc5v0_sys>;
};
- vcc5v0_host: vcc5v0-host-regulator {
+ vcc5v0_host: regulator-vcc5v0-host {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
@@ -103,7 +103,7 @@
vin-supply = <&vcc5v0_sys>;
};
- vcc5v0_sys: vcc5v0-sys-regulator {
+ vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
@@ -113,7 +113,7 @@
vin-supply = <&vcc12v_dcin>;
};
- vcc_5v0: vcc-5v0-regulator {
+ vcc_5v0: regulator-vcc-5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
@@ -127,7 +127,7 @@
vin-supply = <&vcc5v0_sys>;
};
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
target/linux/rockchip/patches-6.12/002-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch
-26
View File
@@ -1,26 +0,0 @@
From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding@rock-chips.com>
Date: Thu, 6 Feb 2025 11:03:30 +0800
Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
and eDP Link. Therefore, it is better to name it hdptxphy0 other than
hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
[added armsom-sige7, where hdmi-support was added recently and also
the hdptxphy0-as-dclk source I just added]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -335,7 +335,7 @@
};
};
-&hdptxphy_hdmi0 {
+&hdptxphy0 {
status = "okay";
};
target/linux/rockchip/patches-6.12/002-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch
-48
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@@ -1,48 +0,0 @@
From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 20 Feb 2025 19:58:11 +0100
Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
RK3588
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.
This means the system might run into a failure state hanging the
whole system for the following use cases:
* if the GPU driver is being probed late (e.g. build as a
module and firmware is not in initramfs), the regulator
might already have been disabled. In that case the power
domain is enabled before the regulator.
* unbinding the GPU driver will disable the PM domain and
the regulator. When the driver is bound again, the PM
domain will be enabled before the regulator and error
appears.
Avoid this by adding an explicit regulator dependency to the
power domain.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -360,6 +360,10 @@
status = "okay";
};
+&pd_gpu {
+ domain-supply = <&vdd_gpu_s0>;
+};
+
&pinctrl {
leds {
io_led: io-led {
target/linux/rockchip/patches-6.12/003-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch
-24
View File
@@ -1,24 +0,0 @@
From 3ca743f8a5b568dc5e5d5f1bab0298a4a43c2360 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 27 Sep 2024 14:42:22 +0200
Subject: arm64: dts: rockchip: Switch to hp-det-gpios
Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Audio
Graph Card and Realtek RT5651 Audio Codec device nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -32,7 +32,7 @@
"Headphones", "HPOR";
dais = <&i2s0_8ch_p0>;
- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hp_detect>;
};
target/linux/rockchip/patches-6.12/003-02-v6.13-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch
-86
View File
@@ -1,86 +0,0 @@
From c8152f79c2dd8039e14073be76fdbce8760175da Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Sat, 19 Oct 2024 13:12:11 +0300
Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5b
Add the necessary DT changes to enable HDMI0 on Radxa ROCK 5B.
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-2-466cd80e8ff9@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588.dtsi"
/ {
@@ -37,6 +38,17 @@
pinctrl-0 = <&hp_detect>;
};
+ hdmi0-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -192,6 +204,26 @@
status = "okay";
};
+&hdmi0 {
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&hdmi0_out {
+ hdmi0_out_con: endpoint {
+ remote-endpoint = <&hdmi0_con_in>;
+ };
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@@ -858,3 +890,18 @@
&usb_host2_xhci {
status = "okay";
};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
target/linux/rockchip/patches-6.12/003-03-v6.13-arm64-dts-rockchip-adapt-regulator-nodenames-to-pref.patch
-72
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@@ -1,72 +0,0 @@
From 5c96e63301978f4657c9082c55a066763c8db7b1 Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx6244@gmail.com>
Date: Sat, 5 Oct 2024 22:40:12 +0200
Subject: arm64: dts: rockchip: adapt regulator nodenames to preferred form
The preferred nodename for fixed-regulators has changed to
pattern: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$'
Fix all Rockchip DT regulator nodenames.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/0ae40493-93e9-40cd-9ca9-990ae064f21a@gmail.com
[adapted rebased on top of a number of other changes and included
neu6a-wifi + wolfvision-pf5-io-expander overlays]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -84,7 +84,7 @@
shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
};
- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
@@ -99,7 +99,7 @@
vin-supply = <&vcc5v0_sys>;
};
- vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
+ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie2x1l2";
regulator-min-microvolt = <3300000>;
@@ -108,7 +108,7 @@
vin-supply = <&vcc_3v3_s3>;
};
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
@@ -121,7 +121,7 @@
vin-supply = <&vcc5v0_sys>;
};
- vcc5v0_host: vcc5v0-host-regulator {
+ vcc5v0_host: regulator-vcc5v0-host {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
@@ -135,7 +135,7 @@
vin-supply = <&vcc5v0_sys>;
};
- vcc5v0_sys: vcc5v0-sys-regulator {
+ vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
@@ -144,7 +144,7 @@
regulator-max-microvolt = <5000000>;
};
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
target/linux/rockchip/patches-6.12/003-04-v6.13-arm64-dts-rockchip-rename-rfkill-label-for-Radxa-ROC.patch
-30
View File
@@ -1,30 +0,0 @@
From 2ddd93481bce86c6a46223f45accdb3b149a43e4 Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Thu, 28 Nov 2024 12:06:30 +0000
Subject: arm64: dts: rockchip: rename rfkill label for Radxa ROCK 5B
on ROCK 5B, there is no PCIe slot, instead there is a M.2 slot.
rfkill pin is not exclusive to PCIe devices, there is SDIO Wi-Fi
devices.
rename rfkill label from "rfkill-pcie-wlan" to "rfkill-m2-wlan", it
matches with rfkill-bt.
Fixes: 82d40b141a4c ("arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b")
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Fixes: 82d40b141a4c ("arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b")
Link: https://lore.kernel.org/r/20241128120631.37458-1-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -72,7 +72,7 @@
rfkill {
compatible = "rfkill-gpio";
- label = "rfkill-pcie-wlan";
+ label = "rfkill-m2-wlan";
radio-type = "wlan";
shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
};
target/linux/rockchip/patches-6.12/003-05-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch
-26
View File
@@ -1,26 +0,0 @@
From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding@rock-chips.com>
Date: Thu, 6 Feb 2025 11:03:30 +0800
Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
and eDP Link. Therefore, it is better to name it hdptxphy0 other than
hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
[added armsom-sige7, where hdmi-support was added recently and also
the hdptxphy0-as-dclk source I just added]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -220,7 +220,7 @@
};
};
-&hdptxphy_hdmi0 {
+&hdptxphy0 {
status = "okay";
};
target/linux/rockchip/patches-6.12/003-06-v6.15-arm64-dts-rockchip-Enable-HDMI1-on-rock-5b.patch
-94
View File
@@ -1,94 +0,0 @@
From 77cea7ca13680e14119a3b9635c7ef16cd7ee44e Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Wed, 11 Dec 2024 01:06:17 +0200
Subject: arm64: dts: rockchip: Enable HDMI1 on rock-5b
Add the necessary DT changes to enable the second HDMI output port on
Radxa ROCK 5B.
While at it, switch the position of &vop_mmu and @vop to maintain the
alphabetical order.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-4-02cdca22ff68@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -49,6 +49,17 @@
};
};
+ hdmi1-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi1_con_in: endpoint {
+ remote-endpoint = <&hdmi1_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -220,10 +231,32 @@
};
};
+&hdmi1 {
+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
+ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+ status = "okay";
+};
+
+&hdmi1_in {
+ hdmi1_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_hdmi1>;
+ };
+};
+
+&hdmi1_out {
+ hdmi1_out_con: endpoint {
+ remote-endpoint = <&hdmi1_con_in>;
+ };
+};
+
&hdptxphy0 {
status = "okay";
};
+&hdptxphy1 {
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@@ -891,11 +924,11 @@
status = "okay";
};
-&vop_mmu {
+&vop {
status = "okay";
};
-&vop {
+&vop_mmu {
status = "okay";
};
@@ -905,3 +938,10 @@
remote-endpoint = <&hdmi0_in_vp0>;
};
};
+
+&vp1 {
+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
+ remote-endpoint = <&hdmi1_in_vp1>;
+ };
+};
target/linux/rockchip/patches-6.12/003-07-v6.15-arm64-dts-rockchip-Enable-HDMI-audio-outputs-for-Roc.patch
-54
View File
@@ -1,54 +0,0 @@
From 97aa62ed1e970bf8aa9f57e87c946a95fa3d5bef Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Mon, 17 Feb 2025 16:47:42 -0500
Subject: arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5B
HDMI audio is available on the Rock 5B HDMI TX ports.
Enable it for both ports.
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node")
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/20250217215641.372723-4-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -231,6 +231,10 @@
};
};
+&hdmi0_sound {
+ status = "okay";
+};
+
&hdmi1 {
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda>;
@@ -249,6 +253,10 @@
};
};
+&hdmi1_sound {
+ status = "okay";
+};
+
&hdptxphy0 {
status = "okay";
};
@@ -351,6 +359,14 @@
};
};
+&i2s5_8ch {
+ status = "okay";
+};
+
+&i2s6_8ch {
+ status = "okay";
+};
+
&package_thermal {
polling-delay = <1000>;
target/linux/rockchip/patches-6.12/003-08-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch
-48
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@@ -1,48 +0,0 @@
From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 20 Feb 2025 19:58:11 +0100
Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
RK3588
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.
This means the system might run into a failure state hanging the
whole system for the following use cases:
* if the GPU driver is being probed late (e.g. build as a
module and firmware is not in initramfs), the regulator
might already have been disabled. In that case the power
domain is enabled before the regulator.
* unbinding the GPU driver will disable the PM domain and
the regulator. When the driver is bound again, the PM
domain will be enabled before the regulator and error
appears.
Avoid this by adding an explicit regulator dependency to the
power domain.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -425,6 +425,10 @@
status = "okay";
};
+&pd_gpu {
+ domain-supply = <&vdd_gpu_s0>;
+};
+
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
target/linux/rockchip/patches-6.12/003-09-v6.15-arm64-dts-rockchip-Enable-HDMI-receiver-on-rock-5b.patch
-47
View File
@@ -1,47 +0,0 @@
From c62d8fdb27391ee72bfdf53328463813997844f1 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Fri, 7 Mar 2025 12:18:57 +0300
Subject: arm64: dts: rockchip: Enable HDMI receiver on rock-5b
The Rock 5B has a Micro HDMI port, which can be used for receiving
HDMI data. This enables support for it.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Link: https://lore.kernel.org/r/20250307091857.646581-3-dmitry.osipenko@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -257,6 +257,17 @@
status = "okay";
};
+&hdmi_receiver_cma {
+ status = "okay";
+};
+
+&hdmi_receiver {
+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&hdptxphy0 {
status = "okay";
};
@@ -430,6 +441,12 @@
};
&pinctrl {
+ hdmirx {
+ hdmirx_hpd: hdmirx-5v-detection {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
target/linux/rockchip/patches-6.12/003-10-v6.16-arm64-dts-rockchip-Add-vcc-supply-to-SPI-flash-on-rk.patch
-28
View File
@@ -1,28 +0,0 @@
From 425af91c58023a8924cc2330384e040d388adc4e Mon Sep 17 00:00:00 2001
From: Diederik de Haas <didi.debian@cknow.org>
Date: Fri, 25 Apr 2025 10:44:44 +0200
Subject: arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3588-rock-5b
The Radxa Rock 5B component placement document identifies the SPI Nor
Flash chip as 'U4300' which is described on page 25 of the Schematic
v1.45. There we can see that the VCC connector is connected to the
VCC_3V3_S3 power source.
This fixes the following warning:
spi-nor spi5.0: supply vcc not found, using dummy regulator
Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Link: https://lore.kernel.org/r/20250425092601.56549-5-didi.debian@cknow.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -562,6 +562,7 @@
spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
+ vcc-supply = <&vcc_3v3_s3>;
};
};
target/linux/rockchip/patches-6.12/003-11-v6.16-arm64-dts-rockchip-move-rock-5b-to-include-file.patch
-1948
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target/linux/rockchip/patches-6.12/003-12-v6.16-arm64-dts-rockchip-add-Rock-5B.patch
-149
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@@ -1,149 +0,0 @@
From 376cb9696298df2028afb620a9dc6c4b10a18605 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 8 May 2025 19:48:53 +0200
Subject: arm64: dts: rockchip: add Rock 5B+
Add ROCK 5B+, which is an improved version of the ROCK 5B with the
following changes:
* Memory LPDDR4X -> LPDDR5
* HDMI input connector size
* eMMC socket -> onboard
* M.2 E-Key is replaced by onboard RTL8852BE WLAN/BT
* M.2 M-Key 1x4 lanes is replaced by 2x2 lanes
* Added M.2 B-Key for USB connected WWAN modules (untested)
* Add second camera port (not yet supported in upstream Linux)
* Add dedicated USB-C port for device power (no impact in DT;
the existing port has not been changed and the new port is
handled by CH224D standalone chip)
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-4-677033cc1ac2@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588-rock-5b.dtsi"
+
+/ {
+ model = "Radxa ROCK 5B+";
+ compatible = "radxa,rock-5b-plus", "rockchip,rk3588";
+
+ rfkill-wwan {
+ compatible = "rfkill-gpio";
+ label = "rfkill-m2-wwan";
+ radio-type = "wwan";
+ shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ };
+
+ vcc3v3_4g: regulator-vcc3v3-4g {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */
+ regulator-name = "vcc3v3_4g";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_wwan_pwr: regulator-vcc3v3-wwan {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wwan_power_en>;
+ regulator-name = "vcc3v3_wwan_pwr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_4g>;
+ };
+};
+
+&gpio0 {
+ wwan-disable2-n-hog {
+ gpios = <RK_PB2 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "M.2 B-key W_DISABLE2#";
+ gpio-hog;
+ };
+};
+
+&gpio2 {
+ wwan-reset-n-hog {
+ gpios = <RK_PB3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "M.2 B-key RESET#";
+ gpio-hog;
+ };
+
+ wwan-wake-n-hog {
+ gpios = <RK_PB2 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "M.2 B-key WoWWAN#";
+ gpio-hog;
+ };
+};
+
+&pcie30phy {
+ data-lanes = <1 1 2 2>;
+};
+
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x2_rst>;
+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pcie3x4 {
+ num-lanes = <2>;
+};
+
+&pinctrl {
+ wwan {
+ wwan_power_en: wwan-pwr-en {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie3 {
+ pcie3x2_rst: pcie3x2-rst {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&vcc5v0_host {
+ enable-active-high;
+ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+};
target/linux/rockchip/patches-6.12/003-13-v6.17-arm64-dts-rockchip-rename-rk3588-rock-5b.dtsi.patch
-1934
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target/linux/rockchip/patches-6.12/003-14-v6.17-arm64-dts-rockchip-move-common-ROCK-5B-nodes-into-ow.patch
-265
View File
@@ -1,265 +0,0 @@
From 988035f152709549a095b12fcdcb3cf26cbad63f Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Tue, 20 May 2025 20:50:10 +0200
Subject: arm64: dts: rockchip: move common ROCK 5B/+ nodes into own tree
A few device tree nodes are shared between ROCK 5B and ROCK 5B+ that are
not shared with ROCK 5T.
Move them into their own device tree include.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-3-1f1971850a20@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
@@ -18,23 +18,6 @@
stdout-path = "serial2:1500000n8";
};
- analog-sound {
- compatible = "audio-graph-card";
- label = "rk3588-es8316";
-
- widgets = "Microphone", "Mic Jack",
- "Headphone", "Headphones";
-
- routing = "MIC2", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR";
-
- dais = <&i2s0_8ch_p0>;
- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&hp_detect>;
- };
-
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
@@ -57,19 +40,6 @@
};
};
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_rgb_b>;
-
- led_rgb_b {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 120 150 180 210 240 255>;
@@ -78,13 +48,6 @@
#cooling-cells = <2>;
};
- rfkill {
- compatible = "rfkill-gpio";
- label = "rfkill-m2-wlan";
- radio-type = "wlan";
- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- };
-
rfkill-bt {
compatible = "rfkill-gpio";
label = "rfkill-m2-bt";
@@ -95,9 +58,6 @@
vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
compatible = "regulator-fixed";
enable-active-high;
- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_0_vcc3v3_en>;
regulator-name = "vcc3v3_pcie2x1l0";
regulator-always-on;
regulator-boot-on;
@@ -105,6 +65,7 @@
regulator-max-microvolt = <3300000>;
startup-delay-us = <50000>;
vin-supply = <&vcc5v0_sys>;
+ status = "disabled";
};
vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
@@ -255,10 +216,8 @@
};
&hdmi_receiver {
- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
pinctrl-names = "default";
- status = "okay";
};
&hdptxphy0 {
@@ -434,39 +393,17 @@
};
&pinctrl {
- hdmirx {
- hdmirx_hpd: hdmirx-5v-detection {
- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
- leds {
- led_rgb_b: led-rgb-b {
- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sound {
- hp_detect: hp-detect {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
pcie2 {
pcie2_0_rst: pcie2-0-rst {
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
- pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
pcie2_2_rst: pcie2-2-rst {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -918,10 +855,6 @@
status = "okay";
};
-&usb_host2_xhci {
- status = "okay";
-};
-
&vop {
status = "okay";
};
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
@@ -2,7 +2,7 @@
/dts-v1/;
-#include "rk3588-rock-5b-5bp-5t.dtsi"
+#include "rk3588-rock-5b.dtsi"
/ {
model = "Radxa ROCK 5B+";
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -2,7 +2,7 @@
/dts-v1/;
-#include "rk3588-rock-5b-5bp-5t.dtsi"
+#include "rk3588-rock-5b.dtsi"
/ {
model = "Radxa ROCK 5B";
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588-rock-5b-5bp-5t.dtsi"
+
+/ {
+ analog-sound {
+ compatible = "audio-graph-card";
+ label = "rk3588-es8316";
+
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+
+ dais = <&i2s0_8ch_p0>;
+ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_b>;
+
+ led_rgb_b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ rfkill {
+ compatible = "rfkill-gpio";
+ label = "rfkill-m2-wlan";
+ radio-type = "wlan";
+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&hdmi_receiver {
+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pinctrl {
+ hdmirx {
+ hdmirx_hpd: hdmirx-5v-detection {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_rgb_b: led-rgb-b {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie2 {
+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&usb_host2_xhci {
+ status = "okay";
+};
+
+&vcc3v3_pcie2x1l0 {
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
+ status = "okay";
+};
target/linux/rockchip/patches-6.12/003-15-v6.17-arm64-dts-rockchip-add-ROCK-5T-device-tree.patch
-134
View File
@@ -1,134 +0,0 @@
From 0ea651de9b79a17cbe410a69399877805c136b76 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Tue, 20 May 2025 20:50:11 +0200
Subject: arm64: dts: rockchip: add ROCK 5T device tree
The RADXA ROCK 5T is a single board computer quite similar to the ROCK
5B+, except it has one more PCIe-to-Ethernet controller (at the expense
of a USB3 port) and a barrel jack for power input instead. Some pins are
shuffled around as well.
Add a device tree for it.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-4-1f1971850a20@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -143,6 +143,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588-rock-5b-5bp-5t.dtsi"
+
+/ {
+ model = "Radxa ROCK 5T";
+ compatible = "radxa,rock-5t", "rockchip,rk3588";
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ label = "rk3588-es8316";
+
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+
+ dais = <&i2s0_8ch_p0>;
+ hp-det-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_b>;
+
+ led_rgb_b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ rfkill {
+ compatible = "rfkill-gpio";
+ label = "rfkill-m2-wlan";
+ radio-type = "wlan";
+ shutdown-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+ };
+
+ vcc3v3_pcie2x1l1: regulator-vcc3v3-pcie2x1l2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+};
+
+&hdmi_receiver {
+ hpd-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie2x1l1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_rst>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l1>;
+ status = "okay";
+};
+
+&pinctrl {
+ hdmirx {
+ hdmirx_hpd: hdmirx-5v-detection {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_rgb_b: led-rgb-b {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie2 {
+ pcie2_1_rst: pcie2-1-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&vcc3v3_pcie2x1l0 {
+ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
+ status = "okay";
+};
target/linux/rockchip/patches-6.12/003-16-v6.17-arm64-dts-rockchip-fix-USB-on-RADXA-ROCK-5T.patch
-40
View File
@@ -1,40 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Mon, 25 Aug 2025 09:27:08 +0200
Subject: arm64: dts: rockchip: fix USB on RADXA ROCK 5T
The RADXA ROCK 5T board uses the same GPIO pin for controlling the USB
host port regulator. This control pin was mistakenly left out of the
ROCK 5T device tree.
Reported-by: FUKAUMI Naoki <naoki@radxa.com>
Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38609886;
Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree")
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
@@ -95,6 +95,12 @@
rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&vcc3v3_pcie2x1l0 {
@@ -103,3 +109,10 @@
pinctrl-0 = <&pcie2_0_vcc3v3_en>;
status = "okay";
};
+
+&vcc5v0_host {
+ enable-active-high;
+ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+};
target/linux/rockchip/patches-6.12/003-17-v6.17-arm64-dts-rockchip-fix-second-M.2-slot-on-ROCK-5T.patch
-56
View File
@@ -1,56 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Tue, 26 Aug 2025 10:08:36 +0200
Subject: arm64: dts: rockchip: fix second M.2 slot on ROCK 5T
The Radxa ROCK 5T has two M.2 slots, much like the Radxa Rock 5B+. As it
stands, the board won't be able to use PCIe3 if the second M.2 slot is
in use.
Fix this by adding the necessary node enablement and data-lanes property
to the ROCK 5T device tree, mirroring what's in the ROCK 5B+ device
tree.
Reported-by: FUKAUMI Naoki <naoki@radxa.com>
Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38610630;
Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree")
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
@@ -68,6 +68,22 @@
status = "okay";
};
+&pcie30phy {
+ data-lanes = <1 1 2 2>;
+};
+
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x2_rst>;
+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pcie3x4 {
+ num-lanes = <2>;
+};
+
&pinctrl {
hdmirx {
hdmirx_hpd: hdmirx-5v-detection {
@@ -90,6 +106,12 @@
};
};
+ pcie3 {
+ pcie3x2_rst: pcie3x2-rst {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sound {
hp_detect: hp-detect {
rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
target/linux/rockchip/patches-6.12/004-01-v6.13-arm64-dts-rockchip-Switch-to-hp-det-gpios.patch
-24
View File
@@ -1,24 +0,0 @@
From 3ca743f8a5b568dc5e5d5f1bab0298a4a43c2360 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 27 Sep 2024 14:42:22 +0200
Subject: arm64: dts: rockchip: Switch to hp-det-gpios
Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Audio
Graph Card and Realtek RT5651 Audio Codec device nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
@@ -46,7 +46,7 @@
compatible = "audio-graph-card";
label = "rk3588-es8316";
dais = <&i2s0_8ch_p0>;
- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hp_detect>;
routing = "MIC2", "Mic Jack",
target/linux/rockchip/patches-6.12/004-02-v6.13-arm64-dts-rockchip-fix-the-pcie-refclock-oscillator-.patch
-94
View File
@@ -1,94 +0,0 @@
From e684f02492f99d6f6f037a35a613607339cf8e8f Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Fri, 6 Sep 2024 10:25:11 +0200
Subject: arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX
The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its
SATA controller with 2 lanes each. The supply for the refclk oscillator is
the same that supplies the M.2 slot, but the SATA controller port is
supplied by a different rail.
This leads to the effect that if the PCIe30x4 controller for the M.2
probes first, everything works normally. But if the PCIe30x2 controller
that is connected to the SATA controller probes first, it will hang on
the first DBI read as nothing will have enabled the refclock before.
Fix this by describing the clock generator with its supplies so that
both controllers can reference it as needed.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240906082511.2963890-6-heiko@sntech.de
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
@@ -72,6 +72,15 @@
};
};
+ /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
+ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
+ compatible = "gated-fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "pcie30_refclk";
+ vdd-supply = <&vcc3v3_pi6c_05>;
+ };
+
fan0: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
@@ -146,13 +155,14 @@
vin-supply = <&vcc_3v3_s3>;
};
- vcc3v3_mkey: regulator-vcc3v3-mkey {
+ /* The PCIE30x4_PWREN_H controls two regulators */
+ vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_pwren_h>;
- regulator-name = "vcc3v3_mkey";
+ regulator-name = "vcc3v3_pi6c_05";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <5000>;
@@ -513,6 +523,18 @@
/* ASMedia ASM1164 Sata controller */
&pcie3x2 {
+ /*
+ * The board has a "pcie_refclk" oscillator that needs enabling,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
+ <&pcie30_port1_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe",
+ "ref";
pinctrl-names = "default";
pinctrl-0 = <&pcie30x2_perstn_m1_l>;
reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
@@ -522,6 +544,18 @@
/* M.2 M.key */
&pcie3x4 {
+ /*
+ * The board has a "pcie_refclk" oscillator that needs enabling,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
+ <&pcie30_port0_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe",
+ "ref";
num-lanes = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_perstn_m1_l>;
target/linux/rockchip/patches-6.12/004-03-v6.14-arm64-dts-rockchip-slow-down-emmc-freq-for-rock-5-it.patch
-35
View File
@@ -1,35 +0,0 @@
From b36402e4a0772d1b3da06a4f5fbd1cfe4d6f1cc0 Mon Sep 17 00:00:00 2001
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Date: Fri, 28 Feb 2025 22:33:08 +0800
Subject: arm64: dts: rockchip: slow down emmc freq for rock 5 itx
The current max-frequency 200000000 of emmc is not stable. When doing
heavy write there will be I/O Error. After setting max-frequency to
150000000 the emmc is stable under write.
Also remove property mmc-hs200-1_8v because we are already running at
HS400 mode.
Tested with fio command:
fio -filename=./test_randread -direct=1 -iodepth 1 -thread \
-rw=randwrite -ioengine=psync -bs=16k -size=1G -numjobs=10 \
-runtime=600 -group_reporting -name=mytest
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Link: https://lore.kernel.org/r/20250228143341.70244-1-liujianfeng1994@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
@@ -690,10 +690,9 @@
&sdhci {
bus-width = <8>;
- max-frequency = <200000000>;
+ max-frequency = <150000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
- mmc-hs200-1_8v;
no-sdio;
no-sd;
non-removable;
target/linux/rockchip/patches-6.12/004-04-v6.15-arm64-dts-rockchip-add-hdmi1-support-to-ROCK-5-ITX.patch
-87
View File
@@ -1,87 +0,0 @@
From 3eac9319af62dbc56d1f06fcb240e4a092fa5b2f Mon Sep 17 00:00:00 2001
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Date: Tue, 25 Feb 2025 11:08:48 +0800
Subject: arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX
Enable the HDMI port next to ethernet port.
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Link: https://lore.kernel.org/r/20250225030904.2813023-1-liujianfeng1994@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "dt-bindings/usb/pd.h"
#include "rk3588.dtsi"
@@ -72,6 +73,17 @@
};
};
+ hdmi1-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi1_con_in: endpoint {
+ remote-endpoint = <&hdmi1_out_con>;
+ };
+ };
+ };
+
/* Unnamed gated oscillator: 100MHz,3.3V,3225 */
pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
compatible = "gated-fixed-clock";
@@ -261,6 +273,28 @@
status = "okay";
};
+&hdmi1 {
+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
+ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+ status = "okay";
+};
+
+&hdmi1_in {
+ hdmi1_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_hdmi1>;
+ };
+};
+
+&hdmi1_out {
+ hdmi1_out_con: endpoint {
+ remote-endpoint = <&hdmi1_con_in>;
+ };
+};
+
+&hdptxphy1 {
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@@ -1208,3 +1242,18 @@
rockchip,dp-lane-mux = <2 3>;
status = "okay";
};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp1 {
+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
+ remote-endpoint = <&hdmi1_in_vp1>;
+ };
+};
target/linux/rockchip/patches-6.12/004-05-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch
-48
View File
@@ -1,48 +0,0 @@
From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 20 Feb 2025 19:58:11 +0100
Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
RK3588
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.
This means the system might run into a failure state hanging the
whole system for the following use cases:
* if the GPU driver is being probed late (e.g. build as a
module and firmware is not in initramfs), the regulator
might already have been disabled. In that case the power
domain is enabled before the regulator.
* unbinding the GPU driver will disable the PM domain and
the regulator. When the driver is bound again, the PM
domain will be enabled before the regulator and error
appears.
Avoid this by adding an explicit regulator dependency to the
power domain.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
@@ -598,6 +598,10 @@
status = "okay";
};
+&pd_gpu {
+ domain-supply = <&vdd_gpu_s0>;
+};
+
&pinctrl {
hym8563 {
rtc_int: rtc-int {
target/linux/rockchip/patches-6.12/005-01-v6.13-arm64-dts-rockchip-add-Radxa-ROCK-5C.patch
-957
View File
@@ -1,957 +0,0 @@
From 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Mon, 21 Oct 2024 09:05:47 +0000
Subject: arm64: dts: rockchip: add Radxa ROCK 5C
Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip
RK3588S2 chip:
- Rockchip RK3588S2
- Quad A76 and Quad A55 CPU
- 6 TOPS NPU
- up to 32GB LPDDR4x RAM
- eMMC / SPI flash connector
- Micro SD Card slot
- Gigabit ethernet port (supports PoE with add-on PoE HAT)
- WiFi6 / BT5.4
- 1x USB 3.0 Type-A HOST port
- 1x USB 3.0 Type-A OTG port
- 2x USB 2.0 Type-A HOST port
- 1x USB Type-C 5V power port
[1] https://radxa.com/products/rock5/5c
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -156,3 +156,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-n
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -0,0 +1,920 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Radxa ROCK 5C";
+ compatible = "radxa,rock-5c", "rockchip,rk3588s";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ label = "rk3588-es8316";
+ dais = <&i2s0_8ch_p0>;
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ hdmi0-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-levels = <0 64 128 192 255>;
+ fan-supply = <&vcc_5v0>;
+ pwms = <&pwm3 0 10000 0>;
+ };
+
+ pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pow_en>;
+ regulator-name = "pcie2x1l2_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc5v_dcin: regulator-vcc5v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_usb_host: regulator-vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren_h>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg_pwren_h>;
+ regulator-name = "vcc5v0_usb_otg0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_3v3_pmu: regulator-vcc-3v3-pmu {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_3v3_s0: regulator-vcc-3v3-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_1v8_s0>;
+ };
+
+ vcc_5v0: regulator-vcc-5v0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_5v0_pwren_h>;
+ regulator-name = "vcc_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_sysin: regulator-vcc-sysin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sysin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_dcin>;
+ };
+
+ vcca: regulator-vcca {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vdd_3v3: regulator-vdd-3v3 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_wifi_pwr>;
+ regulator-name = "vdd_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac1 {
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3_s0>;
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus
+ &gmac1_clkinout>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&hdmi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec
+ &hdmim1_tx0_hpd
+ &hdmim0_tx0_scl
+ &hdmim0_tx0_sda>;
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&hdmi0_out {
+ hdmi0_out_con: endpoint {
+ remote-endpoint = <&hdmi0_con_in>;
+ };
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ vcc-supply = <&vcc_3v3_pmu>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m2_xfer>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "rtcic_32kout";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int_l>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_rstn>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&pcie2x1l2_3v3>;
+ status = "okay";
+};
+
+&pinctrl {
+ leds {
+ led_pins: led-pins {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ mdio {
+ gmac1_rstn: gmac1-rstn {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pow_en: pow-en {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rtc {
+ rtc_int_l: rtc-int-l {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_host_pwren_h: usb-host-pwren-h {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_otg_pwren_h: usb-otg-pwren-h {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_wifi_pwr: usb-wifi-pwr {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc_5v0_pwren_h: vcc-5v0-pwren-h {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3m1_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim0_pins>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+
+ vcc1-supply = <&vcc_sysin>;
+ vcc2-supply = <&vcc_sysin>;
+ vcc3-supply = <&vcc_sysin>;
+ vcc4-supply = <&vcc_sysin>;
+ vcc5-supply = <&vcc_sysin>;
+ vcc6-supply = <&vcc_sysin>;
+ vcc7-supply = <&vcc_sysin>;
+ vcc8-supply = <&vcc_sysin>;
+ vcc9-supply = <&vcc_sysin>;
+ vcc10-supply = <&vcc_sysin>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc_sysin>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcca>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg3 {
+ regulator-name = "vdd_logic_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu_ddr_s3: dcdc-reg10 {
+ regulator-name = "vcc1v8_pmu_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg1 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg2 {
+ regulator-name = "vcca_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-name = "vdda_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-name = "vcca_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg3 {
+ regulator-name = "vdda_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-name = "vdda_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg0>;
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ /* connected to USB hub, which is powered by vcc_5v0 */
+ phy-supply = <&vcc_5v0>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host2_xhci {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
target/linux/rockchip/patches-6.12/005-02-v6.15-arm64-dts-rockchip-Add-finer-grained-PWM-states-for-.patch
-34
View File
@@ -1,34 +0,0 @@
From 6ed35e6ff556626734c400fff5a636b38b91fe19 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Mon, 20 Jan 2025 23:22:46 +0400
Subject: arm64: dts: rockchip: Add finer-grained PWM states for the fan on
Rock 5C
Radxa Heatsink 6540B, which is the official cooling accessory for the
Rock 5C board, includes a small 5V fan, which in my testing spins up
reliably at a PWM setting of 24 (out of 255). It is also quite loud
at the current minimum setting of 64, and noticeably less so at 24.
Introduce two intermediate PWM states at the lower end of the fan's
operating range to enable better balance between noise and cooling.
Note further that, in my testing, having the fan run at 44 is enough
to keep the system from thermal throttling with sustained 100% load
on its 8 CPU cores (in 22C ambient temperature and no case)
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-1-5fb8446c981b@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -71,7 +71,7 @@
fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
- cooling-levels = <0 64 128 192 255>;
+ cooling-levels = <0 24 44 64 128 192 255>;
fan-supply = <&vcc_5v0>;
pwms = <&pwm3 0 10000 0>;
};
target/linux/rockchip/patches-6.12/005-03-v6.15-arm64-dts-rockchip-Enable-automatic-fan-control-on-R.patch
-62
View File
@@ -1,62 +0,0 @@
From cd5681e63fb9887bd05d4ef59151d6a6b39c9d33 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Mon, 20 Jan 2025 23:22:47 +0400
Subject: arm64: dts: rockchip: Enable automatic fan control on Radxa Rock 5C
Add the necessary cooling map to enable the kernel's thermal subsystem
to manage the fan speed automatically depending on the overall SoC
package temperature on Radxa Rock 5C
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-2-5fb8446c981b@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -68,7 +68,7 @@
};
};
- fan {
+ fan: fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
cooling-levels = <0 24 44 64 128 192 255>;
@@ -417,6 +417,36 @@
};
};
+&package_thermal {
+ polling-delay = <1000>;
+
+ trips {
+ package_fan0: package-fan0 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ package_fan1: package-fan1 {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&package_fan0>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map1 {
+ trip = <&package_fan1>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&pcie2x1l2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie20x1_2_perstn_m0>;
target/linux/rockchip/patches-6.12/005-04-v6.15-arm64-dts-rockchip-Fix-label-name-of-hdptxphy-for-RK.patch
-26
View File
@@ -1,26 +0,0 @@
From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding@rock-chips.com>
Date: Thu, 6 Feb 2025 11:03:30 +0800
Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
and eDP Link. Therefore, it is better to name it hdptxphy0 other than
hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
[added armsom-sige7, where hdmi-support was added recently and also
the hdptxphy0-as-dclk source I just added]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -278,7 +278,7 @@
};
};
-&hdptxphy_hdmi0 {
+&hdptxphy0 {
status = "okay";
};
target/linux/rockchip/patches-6.12/005-05-v6.15-arm64-dts-rockchip-switch-Rock-5C-to-PMIC-based-TSHU.patch
-36
View File
@@ -1,36 +0,0 @@
From 52cababc9c1914ebf50929bfb9a67c8f74cd60ab Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Tue, 4 Feb 2025 13:02:28 +0400
Subject: arm64: dts: rockchip: switch Rock 5C to PMIC-based TSHUT reset
Radxa Rock 5C supports both CRU-based (default) and PMIC-based reset
upon thermal runaway conditions. The former resets the SoC by internally
poking the CRU from TSADC, while the latter power-cycles the whole board
by pulling the PMIC reset line low in case of uncontrolled overheating.
Switch to a PMIC-based reset, as the more 'thorough' of the two.
Tested by temporarily setting rockchip,hw-tshut-temp to 65C to simulate
overheating - this causes the board to reset when any of the on-chip
temperature sensors surpasses the tshut temperature.
Requires Alexander's patch [1] fixing TSADC pinctrl assignment
[1] https://lore.kernel.org/r/20250130053849.4902-1-eagle.alexander923@gmail.com
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20250204-rock-5c-tshut-v1-1-33301e4eef64@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -873,6 +873,8 @@
};
&tsadc {
+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
status = "okay";
};
target/linux/rockchip/patches-6.12/005-06-v6.15-arm64-dts-rockchip-Add-GPU-power-domain-regulator-de.patch
-48
View File
@@ -1,48 +0,0 @@
From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 20 Feb 2025 19:58:11 +0100
Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
RK3588
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.
This means the system might run into a failure state hanging the
whole system for the following use cases:
* if the GPU driver is being probed late (e.g. build as a
module and firmware is not in initramfs), the regulator
might already have been disabled. In that case the power
domain is enabled before the regulator.
* unbinding the GPU driver will disable the PM domain and
the regulator. When the driver is bound again, the PM
domain will be enabled before the regulator and error
appears.
Avoid this by adding an explicit regulator dependency to the
power domain.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com>
Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -455,6 +455,10 @@
status = "okay";
};
+&pd_gpu {
+ domain-supply = <&vdd_gpu_s0>;
+};
+
&pinctrl {
leds {
led_pins: led-pins {
target/linux/rockchip/patches-6.12/006-01-v6.14-arm64-dts-rockchip-Add-Radxa-E52C.patch
-780
View File
@@ -1,780 +0,0 @@
From 9be4171219b659a8f0fa0a7913af2c6ab20c714e Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Thu, 26 Dec 2024 02:46:30 +0000
Subject: arm64: dts: rockchip: Add Radxa E52C
Radxa E52C[1] is a compact network computer based on the Rockchip
RK3582 SoC:
- Dual Cortex-A76 and quad Cortex-A55 CPU
- 5TOPS NPU
- 2GB/4GB/8GB LPDDR4 RAM
- 16GB/32GB/64GB on-board eMMC
- microSD card slot
- USB 3.0 Type-A HOST port
- USB Type-C debug port
- USB Type-C power port (5V only)
- 2x 2.5GbE ports
[1] https://radxa.com/products/network-computer/e52c
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20241226024630.13702-3-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-genbook.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts
@@ -0,0 +1,743 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Radxa E52C";
+ compatible = "radxa,e52c", "rockchip,rk3582", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ keys-0 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <18000>;
+ poll-interval = <100>;
+
+ button-0 {
+ label = "Maskrom";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ keys-1 {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&btn_0>;
+
+ button-1 {
+ label = "User";
+ gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ wakeup-source;
+ };
+ };
+
+ leds-0 {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_0>;
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ leds-1 {
+ compatible = "pwm-leds";
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_LAN;
+ linux,default-trigger = "netdev";
+ pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>;
+ max-brightness = <255>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_WAN;
+ linux,default-trigger = "netdev";
+ pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>;
+ max-brightness = <255>;
+ };
+ };
+
+ vcc_1v1_nldo_s3: regulator-1v1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_3v3_pmu: regulator-3v3-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_3v3_s0: regulator-3v3-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcca: regulator-4v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc5v0_usb_otg0: regulator-5v0-0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg_pwren_h>;
+ regulator-name = "vcc5v0_usb_otg0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_5v0: regulator-5v0-1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_5v0_pwren_h>;
+ regulator-name = "vcc_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sysin>;
+ };
+
+ vcc_sysin: regulator-5v0-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sysin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+/*
+ * In the Rockchip RK3582 SoC, some CPU cores end up disabled
+ * and unused because they're marked in the efuses as defective.
+ * The disabling in the DT is performed by the boot loader.
+ */
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ vcc-supply = <&vcc_3v3_pmu>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m2_xfer>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "rtcic_32kout";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int_l>;
+ wakeup-source;
+ };
+};
+
+&pcie2x1l1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20x1_1_perstn_m1>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3_s3>;
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3_s3>;
+ status = "okay";
+};
+
+&pinctrl {
+ keys {
+ btn_0: button-0 {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_0: led-0 {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie20x1_1_perstn_m1: pcie-1 {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie20x1_2_perstn_m0: pcie-2 {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ regulators {
+ vcc_5v0_pwren_h: regulator-5v0-1 {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rtc {
+ rtc_int_l: rtc-0 {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_otg_pwren_h: regulator-5v0-0 {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm11 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm11m1_pins>;
+ status = "okay";
+};
+
+&pwm14 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm14m1_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sd;
+ no-sdio;
+ non-removable;
+ vmmc-supply = <&vcc_3v3_s0>;
+ vqmmc-supply = <&vcc_1v8_s3>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-sdio;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+
+ vcc1-supply = <&vcc_sysin>;
+ vcc2-supply = <&vcc_sysin>;
+ vcc3-supply = <&vcc_sysin>;
+ vcc4-supply = <&vcc_sysin>;
+ vcc5-supply = <&vcc_sysin>;
+ vcc6-supply = <&vcc_sysin>;
+ vcc7-supply = <&vcc_sysin>;
+ vcc8-supply = <&vcc_sysin>;
+ vcc9-supply = <&vcc_sysin>;
+ vcc10-supply = <&vcc_sysin>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc_sysin>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcca>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg3 {
+ regulator-name = "vdd_logic_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vcc_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg1 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg2 {
+ regulator-name = "vcca_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-name = "vdda_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-name = "vcca_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg3 {
+ regulator-name = "vdda_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-name = "vdda_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg0>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
target/linux/rockchip/patches-6.12/007-01-v6.13-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R3S-board.patch
-596
View File
@@ -1,596 +0,0 @@
From 50decd493c8394c52d04561fe4ede34df27a46ba Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Mon, 21 Oct 2024 01:39:46 +0800
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
Ethernet ports designed and developed by FriendlyElec for IoT
applications.
Specification:
- Rockchip RK3566
- 2GB LPDDR4X RAM
- optional 32GB eMMC module
- SD card slot
- 2x 1000 Base-T
- 3x LEDs (POWER, LAN, WAN)
- 2x Buttons (Reset, MaskROM)
- 1x USB 3.0 Port
- Type-C 5V 2A Power
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241020173946.225960-2-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3566-nanopi-r3s.dts | 554 ++++++++++++++++++
2 files changed, 555 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
@@ -0,0 +1,554 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R3S";
+ compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&reset_button_pin>;
+
+ button-reset {
+ label = "reset";
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <50>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>;
+
+ power_led: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ lan_led: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+ };
+
+ wan_led: led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ vcc3v3_sys: regulator-vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_usbc>;
+ };
+
+ vcc5v0_usb: regulator-vcc5v0_usb {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vdd_usbc: regulator-vdd-usbc {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usbc";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-mode = "rgmii-id";
+ phy-handle = <&rgmii_phy1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2_level3
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk_level2
+ &gmac1m0_rgmii_bus_level3>;
+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth_phy_reset_pin>;
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_h>;
+ reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-leds {
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ power_led_pin: power-led-pin {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gmac {
+ eth_phy_reset_pin: eth-phy-reset-pin {
+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pcie {
+ pcie_reset_h: pcie-reset-h {
+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rtc {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
target/linux/rockchip/patches-6.12/007-02-v6.13-arm64-dts-rockchip-fix-model-name-for-FriendlyElec-NanoPi.patch
-38
View File
@@ -1,38 +0,0 @@
From b5bf84206a5c77528f9dd4cbca4e72caa063c102 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Wed, 23 Oct 2024 03:35:26 +0800
Subject: [PATCH] arm64: dts: rockchip: fix model name for FriendlyElec NanoPi
R3S
Use the marketing name for model name, this matches the dt-binding.
Also update the website url in copyright.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-2-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
@@ -3,7 +3,7 @@
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*
* Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
+ * (http://www.friendlyelec.com)
*
* Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
*/
@@ -17,7 +17,7 @@
#include "rk3566.dtsi"
/ {
- model = "FriendlyARM NanoPi R3S";
+ model = "FriendlyElec NanoPi R3S";
compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
aliases {
target/linux/rockchip/patches-6.12/007-03-v1.13-arm64-dts-rockchip-replace-deprecated-snps-reset-props-fo.patch
-40
View File
@@ -1,40 +0,0 @@
From 82b2868937883b65732da498b26366d34db61510 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Wed, 23 Oct 2024 03:35:27 +0800
Subject: [PATCH] arm64: dts: rockchip: replace deprecated snps,reset props for
NanoPi R3S
Replace deprecated snps,reset props and move them to the PHY node.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-3-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
@@ -149,10 +149,6 @@
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk_level2
&gmac1m0_rgmii_bus_level3>;
- snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
status = "okay";
};
@@ -414,6 +410,9 @@
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&eth_phy_reset_pin>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
target/linux/rockchip/patches-6.12/007-04-v6.13-arm64-dts-rockchip-sort-props-in-pmu_io_domains-node-for.patch
-35
View File
@@ -1,35 +0,0 @@
From 17e150fdd983c7e59b9240e34a166285f3c3fb39 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Wed, 23 Oct 2024 03:35:28 +0800
Subject: [PATCH] arm64: dts: rockchip: sort props in pmu_io_domains node for
NanoPi R3S
The status prop is typically the last prop.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-4-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
@@ -476,7 +476,6 @@
};
&pmu_io_domains {
- status = "okay";
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
@@ -486,6 +485,7 @@
vccio5-supply = <&vcc_1v8>;
vccio6-supply = <&vcc_3v3>;
vccio7-supply = <&vcc_3v3>;
+ status = "okay";
};
&sdhci {
target/linux/rockchip/patches-6.12/007-05-v6.13-arm64-dts-rockchip-enable-eMMC-HS200-mode-for-NanoPi-R3S.patch
-26
View File
@@ -1,26 +0,0 @@
From 1b5365034410f1ca21adadadd492b99bdf4f2c55 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Wed, 23 Oct 2024 03:35:29 +0800
Subject: [PATCH] arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
It is required to boot from eMMC without additional patch in u-boot.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-5-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
@@ -491,6 +491,7 @@
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
+ mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
target/linux/rockchip/patches-6.12/007-06-v6.13-arm64-dts-rockchip-reorder-mmc-aliases-for-NanoPi-R3S.patch
-31
View File
@@ -1,31 +0,0 @@
From b7cd1115456d312f8c5e60c80fdc35fd35ea6eab Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Wed, 23 Oct 2024 03:35:30 +0800
Subject: [PATCH] arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
Typically any non-removable storage (emmc) is listed before removable
storage (sd-card) options. Also U-Boot will try to override and use
mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-6-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
@@ -22,8 +22,8 @@
aliases {
ethernet0 = &gmac1;
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
};
chosen: chosen {
target/linux/rockchip/patches-6.12/008-01-v6.15-arm64-dts-rockchip-rk356x-Add-MSI-controller-node.patch
-51
View File
@@ -1,51 +0,0 @@
From f15be3d4a0a55db2b50f319c378a2d16ceb21f86 Mon Sep 17 00:00:00 2001
From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Date: Mon, 17 Feb 2025 01:16:33 +0300
Subject: [PATCH] arm64: dts: rockchip: rk356x: Add MSI controller node
Rockchip 356x SoC's GIC has two hardware integration issues that
affect MSI functionality of the GIC. Previously, both these GIC
issues were worked around by using MBI for MSI instead of ITS
because kernel GIC driver didn't have necessary quirks.
First issue is about RK356x GIC not supporting programmable
shareability, while reporting it as supported in a GIC's feature
register. Rockchip assigned Erratum ID #3568001 for this issue. This
patch adds dma-noncoherent property to the GIC node, denoting that a SW
workaround is required for mitigating the issue.
Second issue is about GIC AXI master interface addressing limited to
the first 4GB of physical address space. Rockchip assigned Erratum
ID #3568002 for this issue.
Now that kernel supports quirks for both of the erratums, add
MSI controller node to RK356x device-tree.
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20250216221634.364158-3-dmitry.osipenko@collabora.com
---
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -364,6 +364,18 @@
mbi-alias = <0x0 0xfd410000>;
mbi-ranges = <296 24>;
msi-controller;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-noncoherent;
+
+ its: msi-controller@fd440000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0xfd440000 0 0x20000>;
+ dma-noncoherent;
+ msi-controller;
+ #msi-cells = <1>;
+ };
};
usb_host0_ehci: usb@fd800000 {

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