eternalwrt/eternalwrt-mt798x
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

uboot-rockchip: fix enter download mode (MaskROM) for RK356x/RK3588

Browse Source 
These SOC_CON1 regs needs to be cleared before a reset or the
BOOT_MODE_REG do not retain its value and it is not possible
to reset to bootrom download mode once TF-A has been started.

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 8b63a55fe2)
This commit is contained in:
Tianling Shen
2026-01-06 11:39:23 +08:00
parent 9d5928ce8b
commit 7f1426692f
7 changed files with 198 additions and 172 deletions
Download Patch File Download Diff File Expand all files Collapse all files
package/boot/uboot-rockchip/patches/101-rockchip-Reset-to-bootrom-download-mode-on-hang.patch
+185
View File
@@ -0,0 +1,185 @@
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH RFC] rockchip: Reset to bootrom download mode on hang
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 02 Feb 2024 00:12:18 +0000
Message-Id: <20240202001221.531207-1-jonas@kwiboo.se>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Add support to reset to bootrom download mode on hang in U-Boot SPL and
proper. ROCKCHIP_HANG_TO_BROM can be used to enable this feature.
Example when SPL cannot load FIT:
U-Boot SPL 2024.04-rc1 (Feb 01 2024 - 23:01:12 +0000)
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC2
Card did not respond to voltage select! : -110
spl: mmc init failed with error: -95
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
entering download mode ...
resetting ...
Procedure to start bootrom download mode:
- U-Boot SPL or proper write 0xEF08A53C to BOOT_MODE_REG and then reset
- Bootrom loads and run boot code (TPL) from e.g. SPI > eMMC > SD-card
- TPL check for 0xEF08A53C in BOOT_MODE_REG very early, i.e. Rockchip
TPL blobs check for this value directly at start
- TPL return to bootrom with a return value != 0
- Bootrom enter download mode
This also fixes an issue where the BOOT_MODE_REG is reset to 0 when
board is reset on RK35xx after TF-A has been loaded. To fix this the
SOC_CON1 reg value is reset prior to issuing a global reset.
The RK356x TF-A blobs will clear SOC_CON1 as part of a PSCI reset,
however the RK3588 TF-A blobs does not seem to clear SOC_CON1.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
- Is reset to bootrom download mode on hang a feature of intereset to
anyone else?
- How can we best handle the issue with BOOT_MODE_REG being reset?
- Should we instead enable SYSRESET_PSCI and relay on TF-A to properly
reset without loosing value in BOOT_MODE_REG? Currently works on
RK356x bl31 blobs but not on the RK3588 bl31 blobs.
---
arch/arm/mach-rockchip/Kconfig | 9 +++++++
arch/arm/mach-rockchip/Makefile | 9 ++++---
arch/arm/mach-rockchip/boot_mode.c | 38 ++++++++++++++++++++++++++----
configs/generic-rk3568_defconfig | 1 +
configs/generic-rk3588_defconfig | 1 +
5 files changed, 48 insertions(+), 10 deletions(-)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -584,6 +584,15 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
This enables support code in the BOOT0 hook for the TPL stage
to allow multiple entries.
+config ROCKCHIP_HANG_TO_BROM
+ bool "Reset to bootrom download mode on hang"
+ select SHOW_BOOT_PROGRESS
+
+config SPL_ROCKCHIP_HANG_TO_BROM
+ bool "Reset to bootrom download mode on hang in SPL"
+ default y if ROCKCHIP_HANG_TO_BROM
+ select SPL_SHOW_BOOT_PROGRESS
+
config SPL_MMC
default y if !SPL_ROCKCHIP_BACK_TO_BROM
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -16,16 +16,15 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
+endif
+ifeq ($(CONFIG_TPL_BUILD),)
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
-obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
-endif
-
-ifeq ($(CONFIG_TPL_BUILD),)
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
endif
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -4,6 +4,7 @@
*/
#include <adc.h>
+#include <bootstage.h>
#include <command.h>
#include <env.h>
#include <log.h>
@@ -22,11 +23,31 @@ int setup_boot_mode(void)
#else
-void set_back_to_bootrom_dnl_flag(void)
+static void set_back_to_bootrom_dnl_flag(void)
{
+ /*
+ * These SOC_CON1 regs needs to be cleared before a reset or the
+ * BOOT_MODE_REG do not retain its value and it is not possible
+ * to reset to bootrom download mode once TF-A has been started.
+ *
+ * TF-A blobs for RK3568 already clear SOC_CON1 for PSCI reset.
+ * However, the TF-A blobs for RK3588 does not clear SOC_CON1.
+ */
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ writel(0x40000, 0xFDC20104);
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588))
+ writel(0xFFFF0000, 0xFD58A004);
+
writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
}
+static void rockchip_reset_to_dnl_mode(void)
+{
+ puts("entering download mode ...\n");
+ set_back_to_bootrom_dnl_flag();
+ do_reset(NULL, 0, 0, NULL);
+}
+
/*
* detect download key status by adc, most rockchip
* based boards use adc sample the download key status,
@@ -74,12 +95,19 @@ __weak int rockchip_dnl_key_pressed(void
#endif
}
-void rockchip_dnl_mode_check(void)
+#if CONFIG_IS_ENABLED(ROCKCHIP_HANG_TO_BROM)
+void show_boot_progress(int val)
+{
+ if (val == -BOOTSTAGE_ID_NEED_RESET)
+ rockchip_reset_to_dnl_mode();
+}
+#endif
+
+static void rockchip_dnl_mode_check(void)
{
if (rockchip_dnl_key_pressed()) {
- printf("download key pressed, entering download mode...");
- set_back_to_bootrom_dnl_flag();
- do_reset(NULL, 0, 0, NULL);
+ puts("download key pressed, ");
+ rockchip_reset_to_dnl_mode();
}
}
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_HANG_TO_BROM=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rk3588-generic"
CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_HANG_TO_BROM=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_EVB_RK3588=y
CONFIG_DEBUG_UART_BASE=0xFEB50000
package/boot/uboot-rockchip/patches/101-rockchip-boot_mode-Allow-rockchip_dnl_key_pressed-in-SPL.patch
-130
View File
@@ -1,130 +0,0 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: u-boot@lists.denx.de
Cc: andre.przywara@arm.com, kever.yang@rock-chips.com,
philipp.tomsich@vrull.eu, sjg@chromium.org, jagan@edgeble.ai,
jonas@kwiboo.se, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V4 3/7] rockchip: boot_mode: Allow rockchip_dnl_key_pressed() in SPL
Date: Tue, 2 Jan 2024 09:46:50 -0600 [thread overview]
Message-ID: <20240102154654.191055-4-macroalpha82@gmail.com> (raw)
In-Reply-To: <20240102154654.191055-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Update the rockchip_dnl_key_pressed() so that it can run in
SPL. Also change the ADC channel to a define that can be
overridden by a board specific option.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/mach-rockchip/Makefile | 4 ++--
arch/arm/mach-rockchip/boot_mode.c | 11 ++++++++++-
2 files changed, 12 insertions(+), 3 deletions(-)
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
-
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
endif
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -37,6 +37,10 @@ void set_back_to_bootrom_dnl_flag(void)
#define KEY_DOWN_MIN_VAL 0
#define KEY_DOWN_MAX_VAL 30
+#ifndef RK_DNL_ADC_CHAN
+#define RK_DNL_ADC_CHAN 0
+#endif
+
__weak int rockchip_dnl_key_pressed(void)
{
#if CONFIG_IS_ENABLED(ADC)
@@ -52,7 +56,8 @@ __weak int rockchip_dnl_key_pressed(void
ret = -ENODEV;
uclass_foreach_dev(dev, uc) {
if (!strncmp(dev->name, "saradc", 6)) {
- ret = adc_channel_single_shot(dev->name, 1, &val);
+ ret = adc_channel_single_shot(dev->name,
+ RK_DNL_ADC_CHAN, &val);
break;
}
}
@@ -76,11 +81,13 @@ __weak int rockchip_dnl_key_pressed(void
void rockchip_dnl_mode_check(void)
{
+#if CONFIG_IS_ENABLED(ADC)
if (rockchip_dnl_key_pressed()) {
printf("download key pressed, entering download mode...");
set_back_to_bootrom_dnl_flag();
do_reset(NULL, 0, 0, NULL);
}
+#endif
}
int setup_boot_mode(void)
@@ -93,6 +100,7 @@ int setup_boot_mode(void)
boot_mode = readl(reg);
debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
/* Clear boot mode */
writel(BOOT_NORMAL, reg);
@@ -106,6 +114,7 @@ int setup_boot_mode(void)
env_set("preboot", "setenv preboot; ums mmc 0");
break;
}
+#endif
return 0;
}
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -6,6 +6,7 @@
#include <dm.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/boot_mode.h>
#include <asm/arch-rockchip/grf_rk3568.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
@@ -133,3 +134,26 @@ int arch_cpu_init(void)
#endif
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+
+void __weak led_setup(void)
+{
+}
+
+void spl_board_init(void)
+{
+ led_setup();
+
+#if (CONFIG_IS_ENABLED(DM_REGULATOR))
+ /*
+ * Turning the eMMC and SPI back on (if disabled via the Qseven
+ * BIOS_ENABLE) signal is done through a always-on regulator).
+ */
+ if (regulators_enable_boot_on(false))
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+ setup_boot_mode();
+}
+#endif
package/boot/uboot-rockchip/patches/102-rockchip-boot_mode-fix-rockchip_dnl_key_pressed-read.patch
+11
View File
@@ -0,0 +1,11 @@
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -73,7 +73,7 @@ __weak int rockchip_dnl_key_pressed(void
ret = -ENODEV;
uclass_foreach_dev(dev, uc) {
if (!strncmp(dev->name, "saradc", 6)) {
- ret = adc_channel_single_shot(dev->name, 1, &val);
+ ret = adc_channel_single_shot(dev->name, 0, &val);
break;
}
}
package/boot/uboot-rockchip/patches/111-rockchip-rk3588-generic-Enable-support-for-RK3582.patch
+1 -1
View File
@@ -51,7 +51,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
aliases {
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL_FIT_SIGNATURE=y
@@ -17,6 +17,7 @@ CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
package/boot/uboot-rockchip/patches/900-enable-good-state-big-bluster2-for-rk3582.patch
+1 -1
View File
@@ -1,6 +1,6 @@
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -342,9 +342,11 @@ int ft_system_setup(void *blob, struct b
@@ -327,9 +327,11 @@ int ft_system_setup(void *blob, struct b
if (ip_state[0] & FAIL_CPU_CLUSTER2)
ip_state[0] |= FAIL_CPU_CLUSTER2;
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r68s-u-boot.dtsi
-36
View File
@@ -8,43 +8,7 @@
};
};
&i2c0 {
bootph-pre-ram;
};
&i2c0_xfer {
bootph-pre-ram;
};
&pmic_int {
bootph-pre-ram;
};
&rk809 {
bootph-pre-ram;
regulators {
bootph-pre-ram;
};
};
&saradc {
bootph-pre-ram;
};
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
};
&usb_host0_xhci {
dr_mode = "otg";
};
&vcca_1v8 {
bootph-pre-ram;
};
package/boot/uboot-rockchip/src/configs/fastrhino-r68s-rk3568_defconfig
-4
View File
@@ -22,8 +22,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
@@ -67,14 +65,12 @@ CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y