rockchip: refresh upstreamed otp patches
Mark upstream accepted patches as backport. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
+70
@@ -0,0 +1,70 @@
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From 2d7b5e1c962158833ef778a09d9293ed710fcc84 Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko@sntech.de>
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Date: Thu, 12 Mar 2026 22:30:18 +0100
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Subject: [PATCH] arm64: dts: rockchip: Enable OTP controller for RK356x
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Enable the One Time Programmable Controller (OTPC) in RK356x and add
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an initial nvmem fixed layout.
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Tested-by: Diederik de Haas <diederik@cknow-tech.com> # NanoPi R5S, PineNote
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://patch.msgid.link/20260312213019.13965-3-heiko@sntech.de
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---
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arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++++++++++
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1 file changed, 46 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -1134,6 +1134,52 @@
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status = "disabled";
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};
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+ otp: efuse@fe38c000 {
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+ compatible = "rockchip,rk3568-otp";
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+ reg = <0x0 0xfe38c000 0x0 0x4000>;
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+ clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>,
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+ <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>;
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+ clock-names = "otp", "apb_pclk", "phy", "sbpi";
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+ resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>,
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+ <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>;
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+ reset-names = "otp", "apb", "phy", "sbpi";
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+
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+ nvmem-layout {
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+ compatible = "fixed-layout";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ cpu_code: cpu-code@2 {
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+ reg = <0x02 0x2>;
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+ };
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+
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+ otp_cpu_version: cpu-version@8 {
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+ reg = <0x08 0x1>;
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+ bits = <3 3>;
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+ };
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+
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+ otp_id: id@a {
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+ reg = <0x0a 0x10>;
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+ };
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+
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+ cpu_leakage: cpu-leakage@1a {
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+ reg = <0x1a 0x1>;
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+ };
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+
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+ log_leakage: log-leakage@1b {
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+ reg = <0x1b 0x1>;
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+ };
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+
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+ npu_leakage: npu-leakage@1c {
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+ reg = <0x1c 0x1>;
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+ };
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+
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+ gpu_leakage: gpu-leakage@1d {
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+ reg = <0x1d 0x1>;
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+ };
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+ };
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+ };
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+
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i2s0_8ch: i2s@fe400000 {
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compatible = "rockchip,rk3568-i2s-tdm";
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reg = <0x0 0xfe400000 0x0 0x1000>;
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+5
-2
@@ -1,6 +1,6 @@
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From 7f6f8fc3ee62f6eb633320c7989d4ba502787e3c Mon Sep 17 00:00:00 2001
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From 9e7aba140eba2aeb72e65ea778c89a245fa235a4 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 16 Mar 2025 19:18:58 +0000
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Date: Thu, 5 Feb 2026 22:18:58 +0100
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Subject: [PATCH] nvmem: rockchip-otp: Handle internal word_size in main
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reg_read op
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@@ -19,8 +19,11 @@ specific read_reg operation and allow code reuse in a future RK3568
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reg_read operation.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Tested-by: Willy Tarreau <w@1wt.eu>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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Tested-by: Heiko Stuebner <heiko@sntech.de>
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Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
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---
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drivers/nvmem/rockchip-otp.c | 72 ++++++++++++++++++++----------------
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1 file changed, 40 insertions(+), 32 deletions(-)
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+4
-3
@@ -1,15 +1,16 @@
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From 24ddbf99c76a352cc1931ccb5118bca0656034b8 Mon Sep 17 00:00:00 2001
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From 11e01bcb827d369344f7f0e960698d33db9ced5a Mon Sep 17 00:00:00 2001
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From: Finley Xiao <finley.xiao@rock-chips.com>
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Date: Tue, 15 Apr 2025 18:32:02 +0800
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Date: Thu, 5 Feb 2026 22:18:59 +0100
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Subject: [PATCH] nvmem: rockchip-otp: Add support for RK3568
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This adds the necessary data for handling otp the rk3568.
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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Tested-by: Heiko Stuebner <heiko@sntech.de>
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
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---
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drivers/nvmem/rockchip-otp.c | 69 ++++++++++++++++++++++++++++++++++++
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1 file changed, 69 insertions(+)
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+5
-2
@@ -1,12 +1,15 @@
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From 249b07e24d3d1d47b7ec23d5f09a56837b66d7f5 Mon Sep 17 00:00:00 2001
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From 85e2134182e21dc9550a1e316d690b1dda52d8cf Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 16 Mar 2025 00:05:45 +0000
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Date: Thu, 5 Feb 2026 22:19:01 +0100
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Subject: [PATCH] nvmem: rockchip-otp: Add support for RK3528
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Add support for the OTP controller in RK3528. The OTPC is similar to the
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OTPC in RK3562 and RK3568, exept for a missing phy clock and reset.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Tested-by: Willy Tarreau <w@1wt.eu>
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Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
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---
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drivers/nvmem/rockchip-otp.c | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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+11
-11
@@ -1,31 +1,31 @@
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From 8a50a4471e4b0db33a74c01229a7ad386918344b Mon Sep 17 00:00:00 2001
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From a956b54f33de96e0d879e679c22a717d390e1afa Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 16 Mar 2025 00:06:43 +0000
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Subject: [PATCH] arm64: dts: rockchip: Enable OTP controller for RK3528
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Date: Thu, 12 Mar 2026 22:30:19 +0100
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Subject: arm64: dts: rockchip: Enable OTP controller for RK3528
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Enable the One Time Programmable Controller (OTPC) in RK3528 and add
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an initial nvmem fixed layout.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://patch.msgid.link/20260312213019.13965-4-heiko@sntech.de
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---
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arch/arm64/boot/dts/rockchip/rk3528.dtsi | 49 ++++++++++++++++++++++++
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1 file changed, 49 insertions(+)
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arch/arm64/boot/dts/rockchip/rk3528.dtsi | 47 ++++++++++++++++++++++++++++++++
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1 file changed, 47 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@@ -1190,6 +1190,55 @@
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@@ -1206,6 +1206,53 @@
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status = "disabled";
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};
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+ otp: nvmem@ffce0000 {
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+ otp: efuse@ffce0000 {
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+ compatible = "rockchip,rk3528-otp";
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+ reg = <0x0 0xffce0000 0x0 0x4000>;
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+ clocks = <&cru CLK_USER_OTPC_NS>,
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+ <&cru PCLK_OTPC_NS>,
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+ clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>,
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+ <&cru CLK_SBPI_OTPC_NS>;
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+ clock-names = "otp", "apb_pclk", "sbpi";
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+ resets = <&cru SRST_USER_OTPC_NS>,
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+ <&cru SRST_P_OTPC_NS>,
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+ resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
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+ <&cru SRST_SBPI_OTPC_NS>;
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+ reset-names = "otp", "apb", "sbpi";
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+
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+1
-1
@@ -79,7 +79,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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qos_crypto_a: qos@ff200000 {
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compatible = "rockchip,rk3528-qos", "syscon";
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reg = <0x0 0xff200000 0x0 0x20>;
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@@ -1275,6 +1323,35 @@
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@@ -1273,6 +1321,35 @@
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rockchip,pipe-phy-grf = <&pipe_phy_grf>;
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status = "disabled";
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};
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-61
@@ -1,61 +0,0 @@
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From e8c0448b695911c5a0cc37cadaacaf71d16b04d2 Mon Sep 17 00:00:00 2001
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From: Finley Xiao <finley.xiao@rock-chips.com>
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Date: Thu, 12 Nov 2020 15:43:28 +0800
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Subject: [PATCH] arm64: dts: rockchip: rk3568: Add otp device node
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: I4ec51ba8d4e1381f787c0137cb475a21e546789d
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 29 ++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -894,6 +894,47 @@
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};
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};
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+ otp: otp@fe38c000 {
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+ compatible = "rockchip,rk3568-otp";
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+ reg = <0x0 0xfe38c000 0x0 0x4000>;
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+ clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>,
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+ <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
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+ clock-names = "usr", "sbpi", "apb", "phy";
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+ resets = <&cru SRST_OTPPHY>;
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+ reset-names = "otp_phy";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ cpu_code: cpu-code@2 {
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+ reg = <0x02 0x2>;
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+ };
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+
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+ otp_cpu_version: cpu-version@8 {
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+ reg = <0x08 0x1>;
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+ bits = <3 3>;
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+ };
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+
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+ otp_id: id@a {
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+ reg = <0x0a 0x10>;
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+ };
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+
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+ cpu_leakage: cpu-leakage@1a {
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+ reg = <0x1a 0x1>;
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+ };
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+
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+ log_leakage: log-leakage@1b {
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+ reg = <0x1b 0x1>;
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+ };
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+
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+ npu_leakage: npu-leakage@1c {
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+ reg = <0x1c 0x1>;
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+ };
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+
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+ gpu_leakage: gpu-leakage@1d {
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+ reg = <0x1d 0x1>;
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+ };
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+ };
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+
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qos_gpu: qos@fe128000 {
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compatible = "rockchip,rk3568-qos", "syscon";
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reg = <0x0 0xfe128000 0x0 0x20>;
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+1
-1
@@ -11,7 +11,7 @@ Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -1188,10 +1188,10 @@
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@@ -1147,10 +1147,10 @@
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};
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rng: rng@fe388000 {
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+1
-1
@@ -1,6 +1,6 @@
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--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@@ -1365,6 +1365,16 @@
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@@ -1363,6 +1363,16 @@
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};
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};
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