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qualcommbe: ipq9574: fix MISC2 mode field and cover USXGMII

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The MISC2 phy mode field is modelled as two bits at the wrong offset:
the hardware field is three bits wide and starts one bit lower. The
SGMII and 2500BASE-X values only come out right because the power-on
default happens to keep the missed bit set, and USXGMII is not
programmed at all, leaving the uniphy in its power-on SGMII
personality.

Model the field at its documented position, add the USXGMII mode
value and write the rate field explicitly instead of relying on its
power-on default, matching the values the vendor SSDK programs.

Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/24033
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Kenneth Kasilag
2026-07-06 11:53:43 +02:00
committed by Robert Marko
parent 8a108c529c
commit d9a98ed59d
1 changed files with 52 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/qualcommbe/patches-6.18/0360-net-pcs-qcom-ipq9574-set-MISC2-phy-mode-for-USXGMII.patch
+52
View File
@@ -0,0 +1,52 @@
From: Kenneth Kasilag <kenneth@kasilag.me>
Date: Thu, 02 Jul 2026 00:00:00 +0000
Subject: [PATCH] net: pcs: qcom-ipq9574: fix MISC2 phy mode field and cover USXGMII
The MISC2 phy mode field is modelled as two bits at the wrong offset:
the hardware field is three bits wide and starts one bit lower. The
SGMII and 2500BASE-X values only come out right because the power-on
default happens to keep the missed bit set, and USXGMII is not
programmed at all, leaving the uniphy in its power-on SGMII
personality.
Model the field at its documented position, add the USXGMII mode
value and write the rate field explicitly instead of relying on its
power-on default, matching the values the vendor SSDK programs.
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
---
drivers/net/pcs/pcs-qcom-ipq9574.c | 14 +++++++++-----
1 file changed, 10 insertions(+), 4 deletions(-)
--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
+++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
@@ -29,9 +29,11 @@
#define PCS_CLKOUT_50M_DIV2_SEL BIT(5)
#define PCS_MISC2 0x218
-#define PCS_MISC2_MODE_MASK GENMASK(6, 5)
-#define PCS_MISC2_MODE_SGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x1)
-#define PCS_MISC2_MODE_SGMII_PLUS FIELD_PREP(PCS_MISC2_MODE_MASK, 0x2)
+#define PCS_MISC2_RATE_MASK GENMASK(1, 0)
+#define PCS_MISC2_MODE_MASK GENMASK(6, 4)
+#define PCS_MISC2_MODE_SGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x3)
+#define PCS_MISC2_MODE_SGMII_PLUS FIELD_PREP(PCS_MISC2_MODE_MASK, 0x5)
+#define PCS_MISC2_MODE_USXGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x7)
#define PCS_MODE_CTRL 0x46c
#define PCS_MODE_SEL_MASK GENMASK(12, 8)
@@ -356,9 +358,13 @@ static int ipq_pcs_config_mode(struct ip
return ret;
}
+ if (interface == PHY_INTERFACE_MODE_USXGMII)
+ misc2 = PCS_MISC2_MODE_USXGMII;
+
if (misc2) {
ret = regmap_update_bits(qpcs->regmap, PCS_MISC2,
- PCS_MISC2_MODE_MASK, misc2);
+ PCS_MISC2_MODE_MASK |
+ PCS_MISC2_RATE_MASK, misc2);
if (ret)
return ret;
}