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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2026-05-07 09:48:50 +08:00
parent 164adef68c 6018bd5b11
commit f4b3098ad3
25 changed files with 340 additions and 408 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts
+5 -5
View File
@@ -70,12 +70,12 @@
};
};
&mdio_bus0 {
&mdio_bus1 {
/* External phy RTL8214FC #1 */
PHY_C22_SFP(48, 48, 0)
PHY_C22_SFP(49, 49, 1)
PHY_C22_SFP(50, 50, 2)
PHY_C22_SFP(51, 51, 3)
PHY_C22_SFP(48, 24, 0)
PHY_C22_SFP(49, 25, 1)
PHY_C22_SFP(50, 26, 2)
PHY_C22_SFP(51, 27, 3)
};
&switch0 {
target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts
+30 -28
View File
@@ -40,42 +40,44 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
/* External phy RTL8214FC */
PHY_C22_SFP(48, 48, 0)
PHY_C22_SFP(49, 49, 1)
PHY_C22_SFP(50, 50, 2)
PHY_C22_SFP(51, 51, 3)
PHY_C22_SFP(48, 24, 0)
PHY_C22_SFP(49, 25, 1)
PHY_C22_SFP(50, 26, 2)
PHY_C22_SFP(51, 27, 3)
};
&switch0 {
target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts
+6 -4
View File
@@ -180,12 +180,14 @@
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
};
&mdio_bus1 {
/* External phy RTL8214FC */
PHY_C22_SFP(48, 48, 0)
PHY_C22_SFP(49, 49, 1)
PHY_C22_SFP(50, 50, 2)
PHY_C22_SFP(51, 51, 3)
PHY_C22_SFP(48, 24, 0)
PHY_C22_SFP(49, 25, 1)
PHY_C22_SFP(50, 26, 2)
PHY_C22_SFP(51, 27, 3)
};
&spi0 {
target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts
+5 -5
View File
@@ -90,11 +90,11 @@
};
};
&mdio_bus0 {
PHY_C22_SFP(48, 48, 0)
PHY_C22_SFP(49, 49, 1)
PHY_C22_SFP(50, 50, 2)
PHY_C22_SFP(51, 51, 3)
&mdio_bus1 {
PHY_C22_SFP(48, 24, 0)
PHY_C22_SFP(49, 25, 1)
PHY_C22_SFP(50, 26, 2)
PHY_C22_SFP(51, 27, 3)
};
&switch0 {
target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts
+5 -5
View File
@@ -80,11 +80,11 @@
};
&mdio_bus0 {
PHY_C22_SFP(48, 48, 1)
PHY_C22_SFP(49, 49, 3)
PHY_C22_SFP(50, 50, 0)
PHY_C22_SFP(51, 51, 2)
&mdio_bus1 {
PHY_C22_SFP(48, 24, 1)
PHY_C22_SFP(49, 25, 3)
PHY_C22_SFP(50, 26, 0)
PHY_C22_SFP(51, 27, 2)
};
target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
+26 -24
View File
@@ -51,33 +51,35 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
&mdio_bus1 {
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_netgear_gs750e.dts
+26 -24
View File
@@ -135,36 +135,38 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts
+26 -24
View File
@@ -269,34 +269,36 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
&mdio_bus1 {
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* RTL8218FB */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
+26 -24
View File
@@ -309,36 +309,38 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi
+26 -24
View File
@@ -274,36 +274,38 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl839x.dtsi
+5
View File
@@ -236,6 +236,11 @@
#address-cells = <1>;
#size-cells = <0>;
};
mdio_bus1: mdio-bus@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mdio_aux: mdio-aux {
target/linux/realtek/dts/rtl9301_d-link_dgs-1250-28x.dts
+1 -1
View File
@@ -79,7 +79,7 @@
compatible = "microchip,tcn75";
reg = <0x48>;
#thermal-sensor-cells = <0>;
alert-polarity-active-high;
ti,alert-polarity-active-high;
};
eeprom@50 {
target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.c
+12 -12
View File
@@ -1326,14 +1326,14 @@ static const struct rteth_config rteth_838x_cfg = {
.qm_pkt2cpu_intpri_map = RTETH_838X_QM_PKT2CPU_INTPRI_MAP,
.qm_rsn2cpuqid_ctrl = RTETH_838X_QM_PKT2CPU_INTPRI_0,
.qm_rsn2cpuqid_cnt = RTETH_838X_QM_PKT2CPU_INTPRI_CNT,
.dma_if_ctrl = RTETH_838X_DMA_IF_CTRL,
.dma_if_intr_sts = RTETH_838X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_838X_DMA_IF_INTR_MSK,
.dma_if_rx_ring_cntr = RTETH_838X_DMA_IF_RX_RING_CNTR,
.dma_if_rx_ring_size = RTETH_838X_DMA_IF_RX_RING_SIZE,
.dma_if_ctrl = RTL838X_DMA_IF_CTRL,
.dma_rx_base = RTETH_838X_DMA_RX_BASE,
.dma_tx_base = RTETH_838X_DMA_TX_BASE,
.mac_force_mode_ctrl = RTETH_838X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL838X_DMA_RX_BASE,
.dma_tx_base = RTL838X_DMA_TX_BASE,
.rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
.mac_reg = { RTETH_838X_MAC_ADDR_CTRL,
RTETH_838X_MAC_ADDR_CTRL_ALE,
@@ -1372,14 +1372,14 @@ static const struct rteth_config rteth_839x_cfg = {
.qm_pkt2cpu_intpri_map = RTETH_839X_QM_PKT2CPU_INTPRI_MAP,
.qm_rsn2cpuqid_ctrl = RTETH_839X_QM_PKT2CPU_INTPRI_0,
.qm_rsn2cpuqid_cnt = RTETH_839X_QM_PKT2CPU_INTPRI_CNT,
.dma_if_ctrl = RTETH_839X_DMA_IF_CTRL,
.dma_if_intr_sts = RTETH_839X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_839X_DMA_IF_INTR_MSK,
.dma_if_rx_ring_cntr = RTETH_839X_DMA_IF_RX_RING_CNTR,
.dma_if_rx_ring_size = RTETH_839X_DMA_IF_RX_RING_SIZE,
.dma_if_ctrl = RTL839X_DMA_IF_CTRL,
.dma_rx_base = RTETH_839X_DMA_RX_BASE,
.dma_tx_base = RTETH_839X_DMA_TX_BASE,
.mac_force_mode_ctrl = RTETH_839X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL839X_DMA_RX_BASE,
.dma_tx_base = RTL839X_DMA_TX_BASE,
.rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
.mac_reg = { RTETH_839X_MAC_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
@@ -1416,16 +1416,16 @@ static const struct rteth_config rteth_930x_cfg = {
.mac_l2_port_ctrl = RTETH_930X_MAC_L2_PORT_CTRL,
.qm_rsn2cpuqid_ctrl = RTETH_930X_QM_RSN2CPUQID_CTRL_0,
.qm_rsn2cpuqid_cnt = RTETH_930X_QM_RSN2CPUQID_CTRL_CNT,
.dma_if_ctrl = RTETH_930X_DMA_IF_CTRL,
.dma_if_intr_sts = RTETH_930X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_930X_DMA_IF_INTR_MSK,
.dma_if_rx_ring_cntr = RTETH_930X_DMA_IF_RX_RING_CNTR,
.dma_if_rx_ring_size = RTETH_930X_DMA_IF_RX_RING_SIZE,
.dma_rx_base = RTETH_930X_DMA_RX_BASE,
.dma_tx_base = RTETH_930X_DMA_TX_BASE,
.l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
.l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
.dma_if_ctrl = RTL930X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTETH_930X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL930X_DMA_RX_BASE,
.dma_tx_base = RTL930X_DMA_TX_BASE,
.rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
.mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
@@ -1461,16 +1461,16 @@ static const struct rteth_config rteth_931x_cfg = {
.mac_l2_port_ctrl = RTETH_931X_MAC_L2_PORT_CTRL,
.qm_rsn2cpuqid_ctrl = RTETH_931X_QM_RSN2CPUQID_CTRL_0,
.qm_rsn2cpuqid_cnt = RTETH_931X_QM_RSN2CPUQID_CTRL_CNT,
.dma_if_ctrl = RTETH_931X_DMA_IF_CTRL,
.dma_if_intr_sts = RTETH_931X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_931X_DMA_IF_INTR_MSK,
.dma_if_rx_ring_cntr = RTETH_931X_DMA_IF_RX_RING_CNTR,
.dma_if_rx_ring_size = RTETH_931X_DMA_IF_RX_RING_SIZE,
.dma_rx_base = RTETH_931X_DMA_RX_BASE,
.dma_tx_base = RTETH_931X_DMA_TX_BASE,
.l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
.l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
.dma_if_ctrl = RTL931X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTETH_931X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL931X_DMA_RX_BASE,
.dma_tx_base = RTL931X_DMA_TX_BASE,
.rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
.mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
target/linux/realtek/files-6.18/drivers/net/ethernet/rtl838x_eth.h
+12 -17
View File
@@ -8,10 +8,13 @@
/* Register definition */
#define RTETH_838X_CPU_PORT 28
#define RTETH_838X_DMA_IF_CTRL (0x9f58)
#define RTETH_838X_DMA_IF_INTR_MSK (0x9f50)
#define RTETH_838X_DMA_IF_INTR_STS (0x9f54)
#define RTETH_838X_DMA_IF_RX_RING_CNTR (0xb7e8)
#define RTETH_838X_DMA_IF_RX_RING_SIZE (0xb7e4)
#define RTETH_838X_DMA_RX_BASE (0x9f00)
#define RTETH_838X_DMA_TX_BASE (0x9f40)
#define RTETH_838X_MAC_ADDR_CTRL (0xa9ec)
#define RTETH_838X_MAC_ADDR_CTRL_ALE (0x6b04)
#define RTETH_838X_MAC_ADDR_CTRL_MAC (0xa320)
@@ -24,10 +27,13 @@
#define RTETH_838X_RMA_CTRL_1 (0x4304)
#define RTETH_839X_CPU_PORT 52
#define RTETH_839X_DMA_IF_CTRL (0x786c)
#define RTETH_839X_DMA_IF_INTR_MSK (0x7864)
#define RTETH_839X_DMA_IF_INTR_STS (0x7868)
#define RTETH_839X_DMA_IF_RX_RING_CNTR (0x603c)
#define RTETH_839X_DMA_IF_RX_RING_SIZE (0x6038)
#define RTETH_839X_DMA_RX_BASE (0x780c)
#define RTETH_839X_DMA_TX_BASE (0x784c)
#define RTETH_839X_MAC_ADDR_CTRL (0x02b4)
#define RTETH_839X_MAC_FORCE_MODE_CTRL (0x02bc + RTETH_839X_CPU_PORT * 4)
#define RTETH_839X_MAC_L2_PORT_CTRL (0x8004 + RTETH_839X_CPU_PORT * 128)
@@ -40,10 +46,13 @@
#define RTETH_839X_RMA_CTRL_3 (0x120c)
#define RTETH_930X_CPU_PORT 28
#define RTETH_930X_DMA_IF_CTRL (0xe028)
#define RTETH_930X_DMA_IF_INTR_MSK (0xe010)
#define RTETH_930X_DMA_IF_INTR_STS (0xe01c)
#define RTETH_930X_DMA_IF_RX_RING_CNTR (0x7c8c)
#define RTETH_930X_DMA_IF_RX_RING_SIZE (0x7c60)
#define RTETH_930X_DMA_RX_BASE (0xdf00)
#define RTETH_930X_DMA_TX_BASE (0xe000)
#define RTETH_930X_MAC_FORCE_MODE_CTRL (0xca1c + RTETH_930X_CPU_PORT * 4)
#define RTETH_930X_MAC_L2_ADDR_CTRL (0xc714)
#define RTETH_930X_MAC_L2_PORT_CTRL (0x3268 + RTETH_930X_CPU_PORT * 64)
@@ -54,10 +63,13 @@
#define RTETH_930X_RMA_CTRL_2 (0x9e68)
#define RTETH_931X_CPU_PORT 56
#define RTETH_931X_DMA_IF_CTRL (0x0928)
#define RTETH_931X_DMA_IF_INTR_MSK (0x0910)
#define RTETH_931X_DMA_IF_INTR_STS (0x091c)
#define RTETH_931X_DMA_IF_RX_RING_CNTR (0x20ac)
#define RTETH_931X_DMA_IF_RX_RING_SIZE (0x2080)
#define RTETH_931X_DMA_RX_BASE (0x0800)
#define RTETH_931X_DMA_TX_BASE (0x0900)
#define RTETH_931X_MAC_FORCE_MODE_CTRL (0x0dcc + RTETH_931X_CPU_PORT * 4)
#define RTETH_931X_MAC_L2_ADDR_CTRL (0x135c)
#define RTETH_931X_MAC_L2_PORT_CTRL (0x6000 + RTETH_931X_CPU_PORT * 128)
@@ -87,32 +99,15 @@
*/
/* DMA interrupt control and status registers */
#define RTL838X_DMA_IF_CTRL (0x9f58)
#define RTL839X_DMA_IF_CTRL (0x786c)
#define RTL930X_DMA_IF_CTRL (0xe028)
#define RTL930X_L2_NTFY_IF_INTR_MSK (0xe04C)
#define RTL930X_L2_NTFY_IF_INTR_STS (0xe050)
/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */
#define RTL931X_DMA_IF_CTRL (0x0928)
#define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4)
#define RTL931X_L2_NTFY_IF_INTR_STS (0x09E8)
#define RTL839X_DMA_IF_INTR_NOTIFY_MASK GENMASK(22, 20)
/* Ringbuffer setup */
#define RTL838X_DMA_RX_BASE (0x9f00)
#define RTL839X_DMA_RX_BASE (0x780c)
#define RTL930X_DMA_RX_BASE (0xdf00)
#define RTL931X_DMA_RX_BASE (0x0800)
#define RTL838X_DMA_TX_BASE (0x9f40)
#define RTL839X_DMA_TX_BASE (0x784c)
#define RTL930X_DMA_TX_BASE (0xe000)
#define RTL931X_DMA_TX_BASE (0x0900)
#define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0x9F48)
#define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0xE008)
target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto-serdes.c
+1 -1
View File
@@ -462,7 +462,7 @@ static int rtsds_probe(struct platform_device *pdev)
bus->parent = dev;
bus->read_c45 = rtsds_read;
bus->write_c45 = rtsds_write;
bus->phy_mask = ~0ULL;
bus->phy_mask = ~0;
ret = devm_of_mdiobus_register(dev, bus, dev->of_node);
if (ret)
target/linux/realtek/files-6.18/drivers/net/mdio/mdio-realtek-otto.c
+1 -2
View File
@@ -916,8 +916,7 @@ static int rtmdio_map_ports(struct device *dev)
return dev_err_probe(dev, -EINVAL, "%pfwP no phy address\n",
of_fwnode_handle(phy));
/* relaxed check as RTL839x uses MDIO addresses 0..51 */
if (smi_addr >= ctrl->cfg->num_phys)
if (smi_addr >= PHY_MAX_ADDR)
return dev_err_probe(dev, -EINVAL, "%pfwP illegal phy address\n",
of_fwnode_handle(phy));
target/linux/realtek/patches-6.18/028-v7.1-hwmon-lm75-fix-configuration-register-writes.patch
+40
View File
@@ -0,0 +1,40 @@
From ccef20232ded30ca6e73865458ebe89c0fe48dfe Mon Sep 17 00:00:00 2001
From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Sat, 2 May 2026 19:32:07 +0200
Subject: hwmon: (lm75) Fix configuration register writes.
Sensors configurations are defined by set and clear masks. These
do not follow a consistent "clear mask is a superset of set mask"
rule. This relaxed definition breaks lm75_write_config()
static inline int lm75_write_config(struct lm75_data *data, u16 set_mask,
u16 clr_mask)
{
return regmap_update_bits(data->regmap, LM75_REG_CONF,
clr_mask | LM75_SHUTDOWN, set_mask);
}
Basically all bits from set_mask that are not defined in clr_mask are
dropped. Fix that by enhancing the helper to always combine clr_mask
and set_mask into the mask bits of regmap_update_bits().
Fixes: 6da24a25f766 ("hwmon: (lm75) Hide register size differences in regmap access functions")
Suggested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://lore.kernel.org/r/20260502173207.3567876-3-markus.stockhausen@gmx.de
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/hwmon/lm75.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/hwmon/lm75.c
+++ b/drivers/hwmon/lm75.c
@@ -352,7 +352,7 @@ static inline int lm75_write_config(stru
u16 clr_mask)
{
return regmap_update_bits(data->regmap, LM75_REG_CONF,
- clr_mask | LM75_SHUTDOWN, set_mask);
+ clr_mask | set_mask | LM75_SHUTDOWN, set_mask);
}
static irqreturn_t lm75_alarm_handler(int irq, void *private)
target/linux/realtek/patches-6.18/029-v7.2-hwmon-lm75-support-active-high-alert-polarity.patch
+63
View File
@@ -0,0 +1,63 @@
From da96d42a568b98508729abf5c8f05d6e7770443d Mon Sep 17 00:00:00 2001
From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Mon, 4 May 2026 17:10:20 +0200
Subject: hwmon: (lm75) Support active-high alert polarity
LM75 devices supported by this driver support configurable active-high
alert polarity. This is already documented in the devicetree description.
Add support for it to the driver.
Follow documentation and defensively enforce active-low if property is
not set. This avoids possible inconsistencies for future devices with
wrong parametrization. No API breakage as all current devices have
their parameters set to active-low.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://lore.kernel.org/r/20260504151020.462342-3-markus.stockhausen@gmx.de
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/hwmon/lm75.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
--- a/drivers/hwmon/lm75.c
+++ b/drivers/hwmon/lm75.c
@@ -122,7 +122,9 @@ struct lm75_data {
static const u8 lm75_sample_set_masks[] = { 0 << 5, 1 << 5, 2 << 5, 3 << 5 };
-#define LM75_SAMPLE_CLEAR_MASK (3 << 5)
+#define LM75_ALERT_POLARITY_HIGH_8_BIT (BIT(2))
+#define LM75_ALERT_POLARITY_HIGH_16_BIT (BIT(2) << 8)
+#define LM75_SAMPLE_CLEAR_MASK (3 << 5)
/* The structure below stores the configuration values of the supported devices.
* In case of being supported multiple configurations, the default one must
@@ -710,6 +712,7 @@ static void lm75_remove(void *data)
static int lm75_generic_probe(struct device *dev, const char *name,
enum lm75_type kind, int irq, struct regmap *regmap)
{
+ u16 clr_mask, pol_mask, set_mask;
struct device *hwmon_dev;
struct lm75_data *data;
int status, err;
@@ -744,8 +747,18 @@ static int lm75_generic_probe(struct dev
return err;
data->orig_conf = status;
- err = lm75_write_config(data, data->params->set_mask,
- data->params->clr_mask);
+ /* Enforce polarity active-low (default) or active-high (devicetree) */
+ if (!data->params->config_reg_16bits)
+ pol_mask = LM75_ALERT_POLARITY_HIGH_8_BIT;
+ else
+ pol_mask = LM75_ALERT_POLARITY_HIGH_16_BIT;
+
+ clr_mask = data->params->clr_mask | pol_mask;
+ set_mask = data->params->set_mask & ~pol_mask;
+ if (device_property_read_bool(dev, "ti,alert-polarity-active-high"))
+ set_mask |= pol_mask;
+
+ err = lm75_write_config(data, set_mask, clr_mask);
if (err)
return err;
target/linux/realtek/patches-6.18/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch
+6 -84
View File
@@ -3,10 +3,10 @@ From: John Crispin <john@phrozen.org>
Date: Thu, 26 Nov 2020 12:02:21 +0100
Subject: realtek dsa/phy: Increase max ports for RTL839X/RTL931X
Linux standard can only support up to 32 devices per mdio bus and up to
12 ports per DSA switch. This is not enough for the large RTL839X and
RTL931X devices. Increase the max values accordingly. Additionally take
care about the functions that work on bit masks.
Linux standard can only support up to 12 ports per DSA switch. This is
not enough for the large RTL839X and RTL931X devices. Increase the max
values accordingly. Additionally take care about the DSA functions that
work on port bit masks. For this enhance the mask type from u32 to u64.
Submitted-by: Bert Vermeulen <bert@biot.com>
Submitted-by: Birger Koblitz <mail@birger-koblitz.de>
@@ -15,48 +15,10 @@ Submitted-by: Bjørn Mork <bjorn@mork.no>
Submitted-by: John Crispin <john@phrozen.org>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
---
drivers/net/mdio/fwnode_mdio.c | 2 +-
include/linux/phy.h | 6 +++---
include/linux/platform_data/dsa.h | 2 +-
include/net/dsa.h | 14 +++++++-------
net/dsa/slave.c | 4 ++--
5 files changed, 14 insertions(+), 14 deletions(-)
2 files changed, 8 insertions(+), 8 deletions(-)
--- a/drivers/net/mdio/fwnode_mdio.c
+++ b/drivers/net/mdio/fwnode_mdio.c
@@ -90,7 +90,7 @@ int fwnode_mdiobus_phy_device_register(s
}
if (fwnode_property_read_bool(child, "broken-turn-around"))
- mdio->phy_ignore_ta_mask |= 1 << addr;
+ mdio->phy_ignore_ta_mask |= BIT_ULL(addr);
fwnode_property_read_u32(child, "reset-assert-us",
&phy->mdio.reset_assert_delay);
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -316,7 +316,7 @@ static inline long rgmii_clock(int speed
}
}
-#define PHY_MAX_ADDR 32
+#define PHY_MAX_ADDR 64
/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
#define PHY_ID_FMT "%s:%02x"
@@ -402,10 +402,10 @@ struct mii_bus {
struct mdio_device *mdio_map[PHY_MAX_ADDR];
/** @phy_mask: PHY addresses to be ignored when probing */
- u32 phy_mask;
+ u64 phy_mask;
/** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */
- u32 phy_ignore_ta_mask;
+ u64 phy_ignore_ta_mask;
/**
* @irq: An array of interrupts, each PHY's interrupt at the index
--- a/include/linux/platform_data/dsa.h
+++ b/include/linux/platform_data/dsa.h
@@ -6,7 +6,7 @@ struct device;
@@ -64,7 +26,7 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
#define DSA_MAX_SWITCHES 4
-#define DSA_MAX_PORTS 12
+#define DSA_MAX_PORTS 54
+#define DSA_MAX_PORTS 56
#define DSA_RTABLE_NONE -1
struct dsa_chip_data {
@@ -110,43 +72,3 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
return mask;
}
--- a/net/dsa/user.c
+++ b/net/dsa/user.c
@@ -320,7 +320,7 @@ static int dsa_user_phy_read(struct mii_
{
struct dsa_switch *ds = bus->priv;
- if (ds->phys_mii_mask & (1 << addr))
+ if (ds->phys_mii_mask & BIT_ULL(addr))
return ds->ops->phy_read(ds, addr, reg);
return 0xffff;
@@ -330,7 +330,7 @@ static int dsa_user_phy_write(struct mii
{
struct dsa_switch *ds = bus->priv;
- if (ds->phys_mii_mask & (1 << addr))
+ if (ds->phys_mii_mask & BIT_ULL(addr))
return ds->ops->phy_write(ds, addr, reg, val);
return 0;
--- a/drivers/net/phy/mdio_bus_provider.c
+++ b/drivers/net/phy/mdio_bus_provider.c
@@ -209,7 +209,7 @@ static int mdiobus_scan_bus_c22(struct m
int i;
for (i = 0; i < PHY_MAX_ADDR; i++) {
- if ((bus->phy_mask & BIT(i)) == 0) {
+ if ((bus->phy_mask & BIT_ULL(i)) == 0) {
struct phy_device *phydev;
phydev = mdiobus_scan_c22(bus, i);
@@ -225,7 +225,7 @@ static int mdiobus_scan_bus_c45(struct m
int i;
for (i = 0; i < PHY_MAX_ADDR; i++) {
- if ((bus->phy_mask & BIT(i)) == 0) {
+ if ((bus->phy_mask & BIT_ULL(i)) == 0) {
struct phy_device *phydev;
/* Don't scan C45 if we already have a C22 device */
target/linux/realtek/patches-6.18/810-lm75-alert-polarity-swap.patch
-58
View File
@@ -1,58 +0,0 @@
From 92ea53e058d40ebda7326016494e3c21dc536c53 Mon Sep 17 00:00:00 2001
From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Mon, 23 Mar 2026 22:12:01 +0200
Subject: [PATCH] hwmon: lm75 alert polarity swap
The LM75 can steer the alert polarity. In default mode the alert
output pin is active-low. This can not be configured with the
existing LM75 driver.
There are hardware designs that use this alert output for an automatic
fan speed control. E.g. the D-Link DGS-1250. This works as follows
- temperature below Tmax threshold -> alert pin low -> fan slow speed
- temperature above Tmax threshold -> alert pin high -> fan high speed
As one can see the hardware design requires the alert pin to be
configured in mode active-high to work as described. Add a LM75 DTS
property "alert-polarity-active-high" that allows to swap the alert
pin behaviour during initialization to active-high.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
--- a/drivers/hwmon/lm75.c
+++ b/drivers/hwmon/lm75.c
@@ -122,7 +122,8 @@ struct lm75_data {
static const u8 lm75_sample_set_masks[] = { 0 << 5, 1 << 5, 2 << 5, 3 << 5 };
-#define LM75_SAMPLE_CLEAR_MASK (3 << 5)
+#define LM75_SAMPLE_CLEAR_MASK (3 << 5)
+#define LM75_ALERT_POLARITY_HIGH BIT(2)
/* The structure below stores the configuration values of the supported devices.
* In case of being supported multiple configurations, the default one must
@@ -713,6 +714,7 @@ static int lm75_generic_probe(struct dev
struct device *hwmon_dev;
struct lm75_data *data;
int status, err;
+ u16 set_mask;
data = devm_kzalloc(dev, sizeof(struct lm75_data), GFP_KERNEL);
if (!data)
@@ -744,8 +746,13 @@ static int lm75_generic_probe(struct dev
return err;
data->orig_conf = status;
- err = lm75_write_config(data, data->params->set_mask,
- data->params->clr_mask);
+ set_mask = data->params->set_mask;
+ if (of_property_read_bool(dev->of_node, "alert-polarity-active-high")) {
+ pr_info("set lm75 alert to active high\n");
+ set_mask |= LM75_ALERT_POLARITY_HIGH;
+ }
+
+ err = lm75_write_config(data, set_mask, data->params->clr_mask);
if (err)
return err;
target/linux/starfive/config-6.12
-6
View File
@@ -112,12 +112,6 @@ CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_XXHASH=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
target/linux/starfive/config-6.18
-6
View File
@@ -113,12 +113,6 @@ CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SIG=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_XXHASH=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
target/linux/starfive/patches-6.18/1023-riscv-dts-starfive-visionfive2-add-SYSLED-support.patch
-34
View File
@@ -1,34 +0,0 @@
From 3a92ee5a97f030bdb1e88272a5d277ecb76836d6 Mon Sep 17 00:00:00 2001
From: Zoltan HERPAI <wigyori@uid0.hu>
Date: Sun, 1 Jun 2025 14:03:30 +0000
Subject: [PATCH 7/8] riscv: dts: starfive: visionfive2: add SYSLED support
A SYS LED is available at aongpio-3. Add standard heartbeat
support for it.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
---
.../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -21,6 +21,18 @@
reg = <0x0 0x6ce00000 0x0 0x1600000>;
};
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-ack {
+ gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ label = "ack";
+ };
+ };
};
&gmac0 {
target/linux/starfive/patches-6.18/1024-riscv-dts-starfive-visionfive2-add-LED-aliases-and-s.patch
+17 -19
View File
@@ -1,8 +1,7 @@
From d930d3d22dcca6946dbdc822d7b8681f0d6372e5 Mon Sep 17 00:00:00 2001
From: Zoltan HERPAI <wigyori@uid0.hu>
Date: Sun, 1 Jun 2025 14:06:04 +0000
Subject: [PATCH 8/8] riscv: dts: starfive: visionfive2: add LED aliases and
stop heartbeat
Subject: [PATCH 8/8] riscv: dts: starfive: visionfive2: add LED aliases
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
---
@@ -20,24 +19,23 @@ Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
/ {
aliases {
ethernet1 = &gmac1;
+ led-boot = &led_ack;
+ led-failsafe = &led_ack;
+ led-running = &led_ack;
+ led-upgrade = &led_ack;
+ led-boot = &led_status_power;
+ led-failsafe = &led_status_power;
+ led-running = &led_status_power;
+ led-upgrade = &led_status_power;
};
reserved-memory {
@@ -25,11 +30,11 @@
leds {
compatible = "gpio-leds";
@@ -65,6 +70,12 @@
status = "okay";
};
- led-ack {
+ led_ack: led-ack {
gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
- linux,default-trigger = "heartbeat";
+ default-state = "on";
label = "ack";
};
};
+&led_status_power {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ label = "status_power";
+};
+
&mmc0 {
non-removable;
};
target/linux/starfive/patches-6.18/1025-riscv-dts-starfive-visionfive2-add-dma-pool-entry.patch
+1 -1
View File
@@ -27,5 +27,5 @@ Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+ linux,cma-default;
+ };
};
};
leds {