The RTL8231 LED driver is using the .brightness_set op, which according
to the documentation should not sleep. Since the RTL8231 is controlled
via an MDIO bus, this is not the case.
When using a non-offloaded LED driver such as netdev, this may currently
trigger kernel warnings:
WARNING: CPU: 0 PID: 14 at kernel/time/timer.c:1754 call_timer_fn.isra.0+0x84/0x8c
timer: led_timer_function+0x0/0x1d8 preempt leak: 00000100 -> 00000000
Switch to the .brightness_set_blocking op to indicate the operation
might sleep.
Fixes: 6ef6014887 ("realtek: Add pinctrl support for RTL8231")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add the RTL8231 controlling the port LEDs to the devicetree, so users
can enable them. Using the appropriate link name, the netdev trigger can
be used to reflect the port status. As no hardware port status
offloading is supported, blinking on traffic could result in increased
load due to the numerous LED updates.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
To enable the use of the RTL8231 to control (port) LEDs, the driver
needs to be enabled in the build. Incorporate it into the kernel, so any
LED consumers also work in failsafe mode.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a pinctrl-single node to the switch GPIO/LED control register that
disables the port LED peripheral when selected. When an RTL8231 is
instantiated, this is required to prevent the user config from being
overwritten by the peripheral.
As this is technically not a pin mux operation, but rather a peripheral
disable, using pinctrl-single for this purpose is bit of a hack, but it
does the job.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
It may be possible that the bootloader has left an RTL8231 expander
configured for synchronous operation, which requires the user to signal
that the new GPIO/LED states should be latched.
As drivers typically perform one operation at a time for the higher
level kernel framework, this would require a latch on every update,
which is not very useful. Disable synchronous operation to keeps things
simple.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The allocated regmap_field object is not stored as a const reference, so
the helper function allocating the object should not return it as such.
Drop 'const' so the build doesn't complain about discarding the
qualifier.
Fixes: 6ef6014887 ("realtek: Add pinctrl support for RTL8231")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The loop scanning the available toggle rates would stop when the
requested interval exceeded the tested interval. Since the intervals are
searched from small to large, this would always trigger on the shortest
interval, or skip to the largest interval for small requested values.
To correctly clamp (ceil) the toggle rate, the loop needs to continue
until the condition is met, instead of breaking the loop.
Fixes: 6ef6014887 ("realtek: Add pinctrl support for RTL8231")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The code in 800-gpio-regmap-Bypass-cache-for-shadowed-outputs.patch
was accepted upstream as commit 897396b418d1 ("gpio: regmap: Bypass
cache for aliased inputs"). Update the filename to reflect the first
release containing this change.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GPIO line connecting to the reset signals of the GS1900-24E(A1)'s
external ICs (RTL8218B phys and RTL8231 expander) cannot be asserted by
the MDIO subsystem, as the reset is shared between busses.
To prevent users from accidentally asserting the reset line, a GPIO hog
is created to permanently de-assert the signal, reliably keeping the
phys and GPIO expanders on.
Tested-by: Simon Fischer <simi.fischa@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The reset line wired to the RTL8231 on the GS1900 series may also
connect to other external ICs on the board. On the GS1900-24E, the
reset line is wired (via buffers) to the board's RTL8231 expanders and
the RTL8218 phys. As these external devices (phys) are on different
busses, the reset line shouldn't be specified on one bus or the other.
Drop the reset specification from the generic GPIO description, so it
can be added back on a per-device basis after confirming the behavior.
Link: https://github.com/openwrt/openwrt/issues/18620
Fixes: fd978c2e80 ("realtek: Enable Zyxel GS1900's RTL8231 reset line")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Some devices have both the color/function and label property defined.
The label can be constructed from the former properties, making it
redundant.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
By switching to the new RTL8231 driver in commit b7af54d5c1 ("realtek:
Simple conversions to RTL8231 MFD driver"), the bootloader state of the
RTL8231's pins is now maintained. As the bootloader de-asserts the PoE
enable signal, this means PoE output is no longer available.
Add a gpio-hog with high output, restoring the line value from when the
pin was configured (by default) as an input with a pull-up resistor.
This will hard-enable the PoE output, but the individual ports can still
be administratively disabled by realtek-poe or a similar tool.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The old RTL8231 driver integrated the MDIO bus access with the GPIO
control ops, making this driver not very portable to newer platforms.
It depended on the SoC ID instead of the compatible to determine the
MDIO access register, further complicating portability.
A new MFD driver is now available, which offers proper pin config as
well as optional LED support, which can work on any (bitbanged) MDIO
bus. Now that all devices have been migrated, we can drop the old code.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
By switching to the new RTL8231 driver in commit b7af54d5c1 ("realtek:
Simple conversions to RTL8231 MFD driver"), the bootloader state of the
RTL8231's pins is now maintained. As the bootloader de-asserts the PoE
enable signal, this means PoE output is no longer available.
Add a gpio-hog with high output, restoring the line value from when the
pin was configured (by default) as an input with a pull-up resistor.
This will hard-enable the PoE output, but the individual ports can still
be administratively disabled by realtek-poe or a similar tool.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Switch the implementation for the RTL8231 GPIO expander to the new
driver.
This allows specifying the GPIO driving the RTL8231's reset as a proper
MDIO reset line, so the gpio-hog can be dropped. Since it was pinned at
a high level, the reset line is actually active-low (i.e. high when not
in reset).
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the common external GPIO DTSI file for the DGS-1210 devices to
use an MDIO device on the auxilairy MDIO bus, as the original driver was
doing behind the screen.
Switching to the new driver will allow for full pin-control and will no
longer reset pin config set by the bootloader.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The DTS file for the DGS-1210-10P is slightly different from the other
DGS-1210 devices, in that it didn't specify a gpio-restart node when it
was added. The gpio-restart has been found to work on the DGS-1210-10P
as well, so switch it over to the common definitions.
This converts the last device from the product family to the common
definition for the (external) GPIOs.
Tested-by: Michel Thill <jmthill@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The 'indirect-access-id' property on gpio0 is a remnant from the
original GPIO driver. This property has not been relevant on the SoC's
embedded GPIO controller for a long time, so just drop it.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Change devices with RTL8231 GPIO expander definition that can easily be
translated to the new RTL8231 binding and carry over any gpio-hogs. This
will let them use the new RTL8231 MFD driver, without any functional
changes.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Zyxel GS1900-8 v2 devices have been produced more recently than v1
devices. As there are v1 boards with RTL8380M rev. C SoCs, it can likely
safely be assumed that all v2 devices will also have a recent SoC
revision, supporting the hardware auxiliary MDIO controller.
Make the GS1900-8 v1 use an emulated auxiliary MDIO bus, for backward
compatibility with devices containing an RTL8380M rev. A.
Since the devicetrees are otherwise identical, GS1900-8 v1 devices with
an RTL8380M rev. B or C will also be able to use the (more efficient) v2
image. This includes any currently functioning device with OpenWrt, so
include the old compatible as a supported device for the GS1900-8 v2.
Link: https://github.com/openwrt/openwrt/issues/9534
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The mdio-gpio driver is required to support early revision of RTL8380M
slicon (rev A) where the auxilairy MDIO controller does not function
correctly. Add this driver to the rtl838x kernel so devices with old
SoCs are also able to function correctly.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
In order to be able to define the external GPIO controller on an
emulated MDIO bus, move the controller definition outside of the main
GS1900 include for RTL838x-based devices.
Additionally, a new DTSI is provided defining the RTL8231 on the
emulated MDIO bus.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Some RTL8380M-based devices have been around for a long time and use an
early A revision of the RTL8380M SoC. This revision has an issue with
the auxiliary MDIO controller, causing it to malfunction. This may lead
to device reboots when the controller is used.
Provide a bit-banged MDIO bus, which muxes the auxiliary MDIO pins to
their GPIO function. Although this will result in lower performance,
there should otherwise be no functional differences.
Link: https://github.com/openwrt/openwrt/issues/9534
Signed-off-by: Sander Vanheule <sander@svanheule.net>
As the bootloader is reconfiguring the RTL8231 on these devices anyway,
no pin state can be maintained over warm reboots. This results in for
example the PoE disable pin always being asserted by the bootloader.
Define the GPIO line linked to the RTL8231's reset so the MDIO subsystem
will also reset the expander on boot and ensure the line in the correct
state.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Supported devices are listed in the metadata as the first part of the
DTS compatible. This normally follows the format "vendor,device".
When updating the device name of the 180W 1920-8G PoE an underscore was
used, instead of a comma, to join the vendor and device name. This will
lead to warnings for users wanting to sysupgrade a device with an older
compatible, as the device's info does not match the one the metadata.
Fixes: 987c96e889 ("realtek: rename hpe,1920-8g-poe to match hardware")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enable the RTL8231 MFD core driver, as well as the pinctrl/gpio driver
to allow RTL839x devices to use it.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enable the driver for the Realtek Otto auxiliary MDIO driver so RTL839x
devices can use it. The related node is added to the base devicetree for
rtl839x-based devices, so they can enabled and use it when required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
For RTL839x, the driver was producing frequent timeouts on bus accesses.
Increasing the timeout to the one from a recent Realtek SDK resolves
these timeouts. To minimize overhead on different SoCs, each controller
can specify their own timeout.
This also add support for the register format as used on RTL93xx.
Support is added for the RTL930x "ext gpio" controller.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
regmap_read_poll_timeout() relies on usleep_range() to time the polling
loop. With the current, rather large, scheduling interval, a short
usleep_range() may take a lot longer than expected, causing performance
issues.
Switch the driver over to using regmap_read_poll_timeout_atomic(), which
uses udelay() to time the polling loop.
For comparision, the 'ethtool -m <dev>' command is about 10 times faster
with the atomic variant.
Using 'perf -r10 ethtool -m lan25':
- Driver using regmap_read_poll_timeout():
2.0117 +- 0.0118 seconds time elapsed ( +- 0.58% )
- Driver using regmap_read_poll_timeout_atomic():
0.1674 +- 0.0250 seconds time elapsed ( +- 14.95% )
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the base DTS file for the 16 and 24 port HPE 1920 devices
(JG923A, JG924A, JG925A, JG926A), causing the new RTL8231 MFD driver to
be loaded at start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the base DTS file for the 8 port HPE 1920 devices (JG920A,
JG921A, JG922A), causing the new RTL8231 MFD driver to be loaded at
start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the devicetree files to switch the GS1900 devices over to the new
pinctrl and GPIO driver. Enable the drivers to ensure the nodes can be
used.
This may fix issues caused by bad RMW behaviour on the GPIO data lines,
or glitches due to setting the pin direction before the pin level.
Although the driver supports retaining GPIO state after a warm boot,
some bootloaders appear to apply a default configuration on boot, which
may cause an interrupt in PoE-PSE support.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add pending patches to add RTL8231 support as a MDIO-bus attached
multi-functional device. This includes subdrivers for the pincontrol and
GPIO features, as well as the LED matrix support.
Leave the drivers disabled until required by a device.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a disabled node for the auxiliary MDIO bus, used to manage the
RTL8231 expanders. A simple-mfd parent node is added, at the same
(implied) address as the switch@1b000000 node, as the switch drivers
should anyway transistion to MFD subdivices at some point.
Additionally, two pinctrl-single node are added to allow the MDX pins to
be muxed correctly, in case the bootloader leaves these unconfigured.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a driver that exposes the auxiliary busses, used for the RTL8231
expanders, as a proper MDIO controller. The device must be instantiated
under an MFD device, so the driver should also be compatible with SoC
managed by an external CPU via SPI.
Leave the driver disabled in builds until required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Run 'make kernel_oldconfig' to get an up-to-date config.
"# CONFIG_I2C_MUX_RTL9300 is not set" is retained, as the kernel module
build will selects CONFIG_I2C_MUX=m, on which this symbol depends.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Images for certain devices are staring to become too large, as some
device only have 6MB available in their vendor partition layout for the
initial install. This is especially pressing for bootloaders only
supporting gzip compression.
Drop some packages from DEFAULT_PACKAGES that aren't strictly required
for a factory install. The user can always install more packages later
using opkg/apk, or via a sysupgrade to a custom build.
firewall4 is kept to ensure the most recent firewall package is selected
in builds including LuCI.
ethtool is kept as a frequently used diagnostics tool.
Link: https://github.com/openwrt/openwrt/pull/17450
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The extraneous closing parenthesis inside the case matching breaks
syntax of the network initialization script 02_network.
/bin/board_detect: /etc/board.d/02_network:
line 40: syntax error: unexpected newline (expecting ")")
Remove this character so board init is functional again.
Fixes: c8ea1aa970 ("realtek: add support for HPE 1920-24G-PoE-370w")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The debounce-interval of a gpio-keys node should be placed in the key
node itself, not in the main node. Move the properties added earlier and
fix the key node name while we're here.
Fixes: 4357f32d41 ("realtek: debounce reset key for Zyxel GS1900")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
When the reset button is next to the SFP cages, I2C operations on the
modules might cause interference on the button's GPIO line. Add a
debounce-interval of 5 times the poll-interval to ensure the line is
actually stable for some time and not just glitching.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GS1900 images have been updated to have a larger firmware partition,
bumping the compatibility version to 2.0. However, since this version is
generated on first boot and the default was used, these images still
advertised 1.0 after a fresh install.
Add a new uci-defaults script that will generate the correct version for
all affected Zyxel GS1900 devices.
Fixes: 35acdbe909 ("realtek: merge Zyxel GS1900 firmware partitions")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The dual-boot partition layout for the Zyxel GS1900 switches results in
6.9MB for both kernel and rootfs. Depending on the package selection,
this may already leave no space for the user overlay.
Merge the two firmware partitions, effectively dropping dual boot
support with OpenWrt. This results in a firmware partition of 13.9MB,
which should leave some room for the future.
To maintain install capabilites on new devices, an image is required
that still fits inside the original partition. The initramfs is used as
factory install image, so ensure this meets the old size constraints.
The factory image can be flashed via the same procedure as vendor images
when reverting to stock, can be installed from stock, or can be launched
via tftpboot.
Link: https://github.com/openwrt/openwrt/issues/16439
Link: https://github.com/openwrt/openwrt/pull/16442
Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
GPIO 5 on the RTL8231 is defined reset the system, but fails to actually
do so. This triggers a kernel a number of warnings and backtrace for
GPIO pins that can sleep, such as the RTL8231's. Two warnings are
emitted by libgpiod, and a third warning by gpio-restart itself after it
fails to restart the system:
[ 106.654008] ------------[ cut here ]------------
[ 106.659240] WARNING: CPU: 0 PID: 4279 at drivers/gpio/gpiolib.c:3098 gpiod_set_value+0x7c/0x108
[ Stack dump and call trace ]
[ 106.826218] ---[ end trace d1de50b401f5a153 ]---
[ 106.962992] ------------[ cut here ]------------
[ 106.968208] WARNING: CPU: 0 PID: 4279 at drivers/gpio/gpiolib.c:3098 gpiod_set_value+0x7c/0x108
[ Stack dump and call trace ]
[ 107.136718] ---[ end trace d1de50b401f5a154 ]---
[ 111.087092] ------------[ cut here ]------------
[ 111.092271] WARNING: CPU: 0 PID: 4279 at drivers/power/reset/gpio-restart.c:46 gpio_restart_notify+0xc0/0xdc
[ Stack dump and call trace ]
[ 111.256629] ---[ end trace d1de50b401f5a155 ]---
By removing gpio-restart from this device, we skip the restart-by-GPIO
attempt and rely only on the watchdog for restarts, which is already the
de facto behaviour.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add the new 'zycast' tool for remote flashing of Zyxel devices, support
for factory image generation for two new TP-Link devices, and improved
compatibility with two other devices.
17de36575f1e zycast: disable build on non-Linux OS
a5dfb5fb5e6e tplink-safeloader: add TP-Link RE205 v3 support
c1e06daf4622 tplink-safeloader: bump EAP225-V3 compat_level
335d063cff23 tplink-safeloader: bump EAP225-Outdoor v1 compat
c1e69e6f9c0d tplink-safeloader: show compat_level with FW info
e87f23849790 zycast: new tool for ZyXEL bootloader flashing
9067281d17da tplink-safeloader: add RE365 v1
Signed-off-by: Sander Vanheule <sander@svanheule.net>
PoE devices in the realtek target have the possibility to add PSE info
to the board description via 02_network. Make this available for all
targets, by moving the uci_set_poe() function to the globally available
uci-default.sh script.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
uci_set_poe() now performs two duties: filtering the list of device
ports to exclude non-PoE ports, and generating the PoE related device
config.
Extract the port filtering to an external function, which is made a bit
more readable by the use of 'sort -V [-r] | uniq -u' to filter duplicate
entries out of a (reverse) version sorted list.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Flash layouts for GS108Tv3, GS110TPPv1, GS308Tv1 and GS310TPv1 are
almost identical, except for the uimage header magic.
Move the flash layout to the common dtsi, and only place the magic value
in the device dts files.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The TP-Link EAP613 v1 is a ceiling-mount 802.11ax access point. It can
be powered via PoE or a DC barrel connector (12V). Connecting to the
UART requires fine soldering and careful manipulation of any soldered
wires.
Device details:
* SoC: MT7621AT
* Flash: 16 MiB SPI NOR
* RAM: 256 MiB DDR3L
* Wi-Fi:
* MT7905DA + MT7975D: 2.4 GHz + 5 GHz (DBDC), 2x2:2
* Two stamped metal antennas (ANT1, ANT2)
* One PCB antenna (ANT3)
* One unpopulated antenna (ANT4)
* Ethernet:
* 1× 10/100/1000 Mbps port with PoE
* LEDs:
* Array of four blue LEDs with one control line
* Buttons:
* Reset
* Board test points:
* UART: next to CPU RF-shield and power circuits
* JTAG: under CPU RF-shield (untested)
* Watchdog: 3PEAK TPV706 (not implemented)
Althought three antennas are populated, the MT7905DA does not support
the additional Rx chain for background DFS detection (or Bluetooth)
according to commit 6cbcc34f50 ("ramips: disable unsupported
background radar detection").
MAC addresses:
* LAN: 48:22:54:xx:xx:a2 (device label)
* WLAN 2.4 GHz: 48:22:54:xx:xx:a2
* WLAN 5 GHz: 48:22:54:xx:xx:a3
The radio calibration blob stored in flash also contains valid MAC
addresses for both radio bands (OUI 00:0c:43).
Factory install:
1. Enable SSH on the device via web interface
2. Log in with SSH, and run `cliclientd stopcs`
3. Upload -factory.bin image via web interface. It may be necessary to
shorten the filename of the image to e.g. 'factory.bin'.
Recovery:
1. Open the device by unscrewing four screws from the backside
2. Carefully remove board from the housing
3. Connect to UART (3.3V):
* Find test points labelled "VCC", "GND", "UART_TX", "UART_RX"
* Solder wires to test points or connect otherwise. Be careful not
to damage the PCB e.g. by pulling on soldered wires.
* Open console with 115200n8 settings
4. Interrupt bootloader and use tftpboot to start an initramfs:
setenv ipaddr $DEVICE_IP
setenv serverip $SERVER_IP
tftpboot 84000000 openwrt-initramfs-kernel.bin
bootm
DO NOT use saveenv to store modified u-boot environment variables. The
environment is saved at flash offset 0x30000, which erases part of the
(secondary) bootloader.
The device uses two bootloader stages. The first stage will load the
second stage from a uImage stored at flash offset 0x10000. In case of
a damaged second stage, the first stage should allow uploading a new
image via y-modem (untested).
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add support for a number of new TP-Link devices.
9e2de8515be1 tplink-safeloader: add EAP610 v3 and EAP613 v1
bb12cf5c3fa9 tplink-safeloader: Add support for TP-Link Deco M5
a2d49fb1e188 tplink-safeloader: add RU support-list entry for Archer C6U v1
Signed-off-by: Sander Vanheule <sander@svanheule.net>
On the realtek target, the subtarget makefiles include a KERNEL_PATCHVER
setting, shadowing KERNEL_PATCHVER from target/linux/realtek/Makefile.
This makes the realtek target an exception in this regard, and makes
switching kernel version a bit bothersome. Remove the overrides so all
subtargets use the same kernel version.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before calling sched_clock_register(), the timer used to drive the
scheduling clock should already be enabled. Otherwise the kernel log
will show strange time jumps during, and the watchdog might not be
pinged in a timely fashion, resulting in reboots.
[ 0.160281] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 78.104319] clocksource: Switched to clocksource realtek_otto_timer
Fixes: 3cc8011171 ("realtek: resurrect timer driver")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
RTL931x kernel builds were patched to bypass the LINKER_LOAD_ADDRESS
parameter, and hardcode it to 0x80220000. This doesn't make much sense,
since value of LINKER_LOAD_ADDRESS, load-ld, only appears to be a copy
of load-y, adjusted to the linker's taste.
Dropping the hacks for bypassing LINKER_LOAD_ADDRESS results in a kernel
that actually starts booting on an RTL9313 (Netgear MS510TXM), but
currently still hangs when the kernel switches timers.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
On RTL931x builds, CONFIG_RTL931X was used as a stand-in for
CONFIG_NO_EXCEPT_FILL. Now that the latter is always selected for
devices in the realtek target, this hack can be removed. Resulting
device images are binary identical.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
FACTORY_SIZE is used as a device recipe variable on both the D-Link
DIR-825-B1 and Trendnet TEW-673GRU, but is not listed as a device
variable, neither globally, nor for ath79. Being assigned the same
value, this probably hasn't caused any issues.
Add FACTORY_SIZE to the global list DEFAULT_DEVICE_VARS, to ensure the
variable is reset for every device, and to allow it to be used outside
of the ath79 target.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
ZyXEL GS1900 devices with SoCs from both the RTL838x and RTL839x
families share the same image structure and size of the firmware
partition. Additionally, the GS1900-48 recipe provided a parameter for
the zyxel-vers command, but this parameter is not used. Deduplicate the
recipes by moving it to target/linux/realtek/image/common.mk.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The listed partition size doesn't match the original partition size, and
actually overlaps with the following partition. The partition node name
for the "firmware" partition also has an extra 'b' compared to the
partition offset.
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GS1900-48 firmware image is identified by the 'AAHN' ID, while the
GS1900-48HP is identified by 'AAHO' [1]. The latter was used, resulting
in the following error message when upgrading via the stock web UI:
Device only can support firmware from V1.00(AAHN.0) and later version
Fix image generation by using the correct ID.
[1] https://download.zyxel.com/GS1900-48/firmware/GS1900-48_2.70(AAHN.3)C0_2.pdf
Link: https://forum.openwrt.org/t/146533
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Suggested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
While cleaning up the makefiles for the realtek target, the order of the
default image generating commands was accidentally changed. This caused
the image signature to end up somewhere in the middle, misaligning the
rootfs. As a result, sysupgrade couldn't verify upgrade images anymore,
and devices end up in a boot loop due to the unaligned (and not found)
rootfs.
Fixes: 94d8b4852b ("realtek: Cleanup Makefiles")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
PKG_SOURCE_DATE was modified after updating PKG_MIRROR_HASH, causing the
latter to change. This results in a warning during builds and rejected
downloads.
Fixes: 232879a7b7 ("firmware-utils: bump to git HEAD")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Adds support for building TP-Link CPE605v1 factory images
bd856eff4850 tplink-safeloader: add TP-Link CPE605 v1 Support
Signed-off-by: Sander Vanheule <sander@svanheule.net>
After replacing the R4K event timer and clock source with the new
Realtek Otto timer, performance for RTL839x devices was severely
impacted, as reported by Hiroshi.
Research by Markus showed that after commit 4657a5301e ("realtek:
avoid busy waiting for RTL839x PHY read/write"), the ethernet driver
could only update a phy once per timer interval, which also heavily
impacted boot time. On e.g. a Zyxel GS1900-48, this added around a
minute to the time to fully initialise the switch.
By marking the otto clocksource as continuous, the kernel enables it to
be used for high resolution timers. This allows readx_poll_timeout() to
sleep for less than one system timer interval, reducing system dead
time.
Link: https://github.com/openwrt/openwrt/issues/11117
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Cc: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> # Panasonic Switch-M48eG PN28480K
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
The switches support different actions for incoming ethernet multicast
frames with Reserved Multicast Addresses (01-80-C2-00-00-{01-2F}). The
current code will set the 2-bit action field to FLOOD (0x3) for most
classes, but the highest bit is always unset for the relevant control
registers. This means the DROP (0x1) action being used for these
classes; whatever class the MSB happens to be in.
For RTL838x, this results in {20,23-2F} frames being dropped, instead of
flooding all ports. On other switch generations, {0F,1F,2F} frames are
dropped. This is inconsistent, and appears to be a mistake. Remove this
inconsistency by flooding all multicast frames with RMA addresses.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The multicast setup function rtl838x_eth_set_multicast_list() checks if
the current SoC is a RTL839x family device. However, the function is
only included in the RTL838x ops table, so this path should never be
taken, making this dead code. rtl839x_eth_set_multicast_list() is
already present in the RTL839x ops table, so it should be safe to remove
this branch.
While touching the code, also re-sort the functions to match sorting
elsewhere, with rtl838x coming before rtl839x.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The workaround for an already-enabled R4K timer used a non-existent
macro CAUSE_DC. Fix compiling by using the actual macro CAUSEF_DC.
Fixes: b7aab19585 ("realtek: SMP handling of R4K timer interrupts")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The Build prefix is used for image build commands, while the Device
prefix should be used for base recipes for devices. Apply the same
naming convention here.
While touching the file, also fix the mixed indentation.
Suggested-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Currently supported HPE 1920 devices all have an RTL838x SoC, but there
are larger switches with RTL839x SoCs, although currently not supported.
Move the build recipe to common.mk so the larger devices can also make
use of the recipe, while moving it out of the main Makefile.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The D-Link DGS-1210 device series currently has supported devices with
both RTL838x and RTL839x SoCs. An image build recipe has been defined in
both subtarget makefiles, but these are mostly identical, save for the
SOC variable.
Move the SOC variable from the DGS-1210 build recipes to the applicable
devices, and put the remaining duplicate code in a shared Makefile.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
8 and 16 bit writes to the GPIO peripheral are apparently not supported,
and only worked most of the time. This resulted in garbabe writes to the
interrupt mask registers, causing spurious unhandled interrupts, which
could lead to CPU lock-ups as these kept retriggering.
Instead of clearing these spurious interrupt when they occur, the
upstream patch will just make sure all register writes have the intended
result, so these don't happen at all.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
When marking a switch port as disabled in the device tree, by using
'status = "disabled";', the switch driver fails on boot, causing a
restart:
CPU 0 Unable to handle kernel paging request at virtual address
00000000, epc == 802c3064, ra == 8022b4b4
[ ... ]
Call Trace:
[<802c3064>] strlen+0x0/0x2c
[<8022b4b4>] start_creating.part.0+0x78/0x194
[<8022bd3c>] debugfs_create_dir+0x44/0x1c0
[<80396dfc>] rtl838x_dbgfs_port_init+0x54/0x258
[<80397508>] rtl838x_dbgfs_init+0xe0/0x56c
This is caused by the DSA subsystem (mostly) ignoring the port, while
rtl83xx_mdio_probe() still extracts some details on this disabled port
from the device tree, resulting in the usage of a NULL pointer where a
port name is expected.
By not probing ignoring disabled ports, no attempt is made to create a
debugfs directory later. The device then boots as expected without the
disabled port.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The original commit for the GS110TP was missing ports 9 and 10. These
are provided by an external RTL8214C phy, for which no support was
available at the time. Now that this phy is supported, add the missing
entries to enable all device ports.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Version 22.00 of 7z causes build failures on systems using GCC 12 with
the following error:
../../../../C/LzmaEnc.c: In function 'LzmaEnc_CodeOneMemBlock':
../../../../C/LzmaEnc.c:2996:19: error: storing the address of local
variable 'outStream' in '*p.rc.outStream' [-Werror=dangling-pointer=]
2996 | p->rc.outStream = &outStream.vt;
| ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
../../../../C/LzmaEnc.c:2979:28: note: 'outStream' declared here
2979 | CLzmaEnc_SeqOutStreamBuf outStream;
| ^~~~~~~~~
../../../../C/LzmaEnc.c:2979:28: note: 'pp' declared here
Upgrade to version 22.01 which contains the required fix.
Fixes: 5fcc6f0f19 ("tools: add 7z host package")
Suggested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Support for HPE 1920 images depends on two non-existent tools (mkh3cimg
and mkh3cvfs) from the in the firmware-utils package. Revert commit
f2f09bc002 ("realtek: add support for HPE 1920 series") until support
for these tools is merged and made available in OpenWrt.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The interrupt controller in the internal GPIO peripheral will sometimes
generate spurious interrupts. If these are not properly acknowledged, the
system will be held busy until reboot. These spurious interrupts are identified
by the fact that there is no system IRQ number associated, since the interrupt
line was never allocated. Although most prevalent on RTL839x, RTL838x SoCs have
also displayed this behaviour.
Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> # DGS-1210-52
Reported-by: Birger Koblitz <mail@birger-koblitz.de> # Netgear GS724TP v2
Reported-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-16G
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Destination switch ports for outgoing frame can range from 0 to
CPU_PORT-1.
Refactor the code to only generate egress frame CPU headers when a valid
destination port number is available, and make the code a bit more
consistent between different switch generations. Change the dest_port
argument's type to 'unsigned int', since only positive values are valid.
This fixes the issue where egress frames on switch port 0 did not
receive a VLAN tag, because they are sent out without a CPU header.
Also fixes a potential issue with invalid (negative) egress port numbers
on RTL93xx switches.
Reported-by: Arınç ÜNAL <arinc.unal@xeront.com>
Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Priority values passed to the egress (TX) frame header initialiser are
invalid when smaller than 0, and should not be assigned to the frame.
Queue assignment is then left to the switch core logic.
Current code for RTL83xx forces the passed priority value to be
positive, by always masking it to the lower bits, resulting in the
priority always being set and enabled. RTL93xx code doesn't even check
the value and unconditionally assigns the (32 bit) value to the (5 bit)
QID field without masking.
Fix priority assignment by only setting the AS_QID/AS_PRI flag when a
valid value is passed, and properly mask the value to not overflow the
QID/PRI field.
For RTL839x, also assign the priority to the right part of the frame
header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36
and 37-39. The means they should be assigned to the third 16 bit value,
containing bits 32-47.
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The flag to enable L2 address learning on egress frames is in CPU header
bit 40, with bit 0 being the leftmost bit of the header. This
corresponds to BIT(7) in the third 16-bit value of the header.
Correctly set L2LEARNING by fixing the off-by-one error.
Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The flag to enable the outgoing port mask is in CPU header bit 43, with
bit 0 being the leftmost bit of the header. This corresponds to BIT(4)
in the third 16-bit value of the header.
Correctly set AS_DPM by fixing the off-by-one error.
Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
setup.c unconditionally sets the sys-led mode (blinking rate) to a
permanent high output. This may cause issues when a board expects this
pin to toggle periodically, e.g. when hooked up to an external watchdog.
If the sys-led peripheral is used to control an LED, the mux should be
configured to use the pin as GPIO0, allowing for better control as a
GPIO LED.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The devicetree for the ZyXEL XGS1250-12 was missing the description of
the front panel LED labeled "PWR SYS". Let's add it so it can be
controlled by the user.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Like for RTL838x devices, add a pinctrl-single node to manage the
sys-led/gpio0 mux, and allow using the pin as GPIO.
Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Not all devices using the gpio0/sys-led pin as a GPIO, configure the
pinmux. Add the necessary pinctrl properties to these devices to ensure
the pin is set up for use as GPIO.
Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Bjørn Mork <bjorn@mork.no>
What should have been only cosmetic changes, ended up in breaking the
script. Rename UIMAGE_CRC_SLICE back to (the original) UIMAGE_CRC_OFF.
Fixes issue #10204 "cameo-tag.py broken"
Reported-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Fixes: f9e840b657 ("scripts: add CAMEO tag generator")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
In Linux v5.14 an extra feature was introduced for the RTL8211F phy,
allowing to disable a clock output from the phy. Part of that patch is to
always (soft) reset the phy upon initialisation.
This phy reset is required to have a working ethernet on the TP-Link
EAP225-Outdoor v3 and EAP225 v4 after a reboot. Otherwise the ethernet
port will only function properly on cold boots.
Tested-by: Andre Klärner <kandre@ak-online.be> # EAP225-Outdoor v3
Tested-by: Sven Hauer <sven.hauer+github@uniku.de> # EAP225 v4
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The support-list partition for the EAP225-V3 board ID became larger than
the allocated size, resulting in factory image generation for the
EAP225-Outdoor v3 and EAP225 v3 to fail. The make directive
Build/tplink-safeloader ignores this failure however, resulting in a
seemingly successful build with empty factory images.
Included changes:
e609c5d75186 tplink-safeloader: drop unqualified EAP225-V3 IDs
Signed-off-by: Sander Vanheule <sander@svanheule.net>
ath10k Wave-2 hardware requires an nvmem-cell called "pre-calibration"
to load the device specific caldata, not "calibration". Rename the nvmem
cell node and label to match the updated cell name.
Fixes: eca0d73011 ("ath79: TP-Link EAP225 v3: convert ath10k to nvmem-cells")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
ath10k Wave-2 hardware requires an nvmem-cell called "pre-calibration"
to load the device specific caldata, not "calibration". Rename the nvmem
cell node and label to match the updated cell name.
Fixes: 48625a0445 ("ath79: TP-Link EAP225-Wall v1: convert radios to nvmem-cells")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Convert the calibration data reference for the ath9k radio to an
nvmem-cell, replacing the downstream mtd-cal-data property.
Since the 'art' label is no longer used, it can be dropped.
Cc: Sebastian Schaper <openwrt@sebastianschaper.net>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The art partition containing the radio calibration data is in the same
location for all supported devices. Move the definition to the base file
so the reference from the wmac node can reference the same file.
Cc: Sebastian Schaper <openwrt@sebastianschaper.net>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add the PCIe node for the ath10k radio to the devicetree, and refer to
the art partition for the calibration data using nvmem-cells.
MAC address assignment is moved to '10_fix_wifi_mac', so the device can
then be removed from the caldata extraction script '11-ath10k-caldata'.
Cc: Sebastian Schaper <openwrt@sebastianschaper.net>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add the PCIe node for the ath10k radio to the devicetree, and refer to
the art partition for the calibration data using nvmem-cells.
MAC address assignment is moved to '10_fix_wifi_mac', so the device can
then be removed from the caldata extraction script '11-ath10k-caldata'.
Cc: Sebastian Schaper <openwrt@sebastianschaper.net>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Sander Vanheule