video/libs/wpewebkit/patches/123-JavaScriptCore-RISCV64-LLInt-in-place-interpreter.patch

From: Daniel Golle <daniel@makrotopia.org>
Subject: [PATCH] JavaScriptCore: support the LLInt in-place interpreter on RISCV64

The WebAssembly in-place interpreter (IPInt, llint/InPlaceInterpreter.asm)
does not build for RISCV64: offlineasm's RISCV64 backend has not been
updated since the IPInt code landed. Two gaps:

 * LowLevelInterpreter.asm aliases the WebAssembly scratch registers
   ws0..ws3 to t9..t12 in the catch-all 'else' branch (written for
   ARM64). The RISCV64 offlineasm backend only provides t0..t7, so
   lowering fails with "Bad register name t9". RISCV64 also has no
   register budget for four WebAssembly scratch registers.

   Add an explicit RISCV64 branch that uses t8/t9 for ws0/ws1 and
   leaves ws2/ws3 unavailable, matching the X86_64 configuration.

 * offlineasm/riscv64.rb does not implement the 'transferp' opcode
   (a memory-to-memory pointer move) used by InPlaceInterpreter.asm,
   so lowering fails with "Unhandled opcode transferp".

   Map the previously unused physical registers x5/x6 to offlineasm
   t8/t9 and f6/f7 to ft6/ft7, and rewrite the transferi/transferp/
   transferq pseudo-instructions to a load into a temporary followed
   by a store, before the address-lowering passes run.

With both changes offlineasm emits LLIntAssembly.h for RISCV64 with
WebAssembly enabled.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- a/Source/JavaScriptCore/offlineasm/riscv64.rb
+++ b/Source/JavaScriptCore/offlineasm/riscv64.rb
@@ -34,9 +34,9 @@
 # x2  => sp (through alias sp) (RISC-V stack pointer register)
 # x3  => not used (RISC-V global pointer register)
 # x4  => not used (RISC-V thread pointer register)
-# x5  => not used
-# x6  => ws0
-# x7  => ws1
+# x5  => t8
+# x6  => t9
+# x7  => not used
 # x8  => cfr (through alias fp) (RISC-V frame pointer register)
 # x9  => csr0
 # x10 => t0, a0, wa0, r0
@@ -70,8 +70,8 @@
 # f3  => ft3
 # f4  => ft4
 # f5  => ft5
-# f6  => not used
-# f7  => not used
+# f6  => ft6
+# f7  => ft7
 # f8  => csfr0
 # f9  => csfr1
 # f10 => fa0, wfa0
@@ -170,10 +170,10 @@ class RegisterID
             'x16'
         when 't7', 'a7', 'wa7'
             'x17'
-        when 'ws0'
+        when 't8'
+            'x5'
+        when 't9'
             'x6'
-        when 'ws1'
-            'x7'
         when 'csr0'
             'x9'
         when 'csr1'
@@ -223,6 +223,10 @@ class FPRegisterID
             'f4'
         when 'ft5'
             'f5'
+        when 'ft6'
+            'f6'
+        when 'ft7'
+            'f7'
         when 'csfr0'
             'f8'
         when 'csfr1'
@@ -394,6 +398,22 @@ def riscv64LowerOperandIntoRegisterAndSi
     destination
 end
 
+def riscv64LowerTransfer(list)
+    newList = []
+    list.each {
+        | node |
+        if node.is_a?(Instruction) and ["transferi", "transferp", "transferq"].include?(node.opcode)
+            size = node.opcode[-1, 1]
+            tmp = Tmp.new(node.codeOrigin, :gpr)
+            newList << Instruction.new(node.codeOrigin, "load#{size}", [node.operands[0], tmp])
+            newList << Instruction.new(node.codeOrigin, "store#{size}", [tmp, node.operands[1]])
+        else
+            newList << node
+        end
+    }
+    newList
+end
+
 def riscv64LowerMisplacedAddresses(list)
     newList = []
     list.each {
@@ -1541,6 +1561,7 @@ class Sequence
         result = @list
 
         result = riscDropTags(result)
+        result = riscv64LowerTransfer(result)
         result = riscLowerMalformedAddresses(result) {
             | node, address |
             if address.is_a? Address
--- a/Source/JavaScriptCore/llint/LowLevelInterpreter.asm
+++ b/Source/JavaScriptCore/llint/LowLevelInterpreter.asm
@@ -365,6 +365,52 @@ elsif X86_64
     const wfa7 = ft7
 
     const fr = fa0
+elsif RISCV64
+    const a0 = t0
+    const a1 = t1
+    const a2 = t2
+    const a3 = t3
+    const a4 = t4
+    const a5 = t5
+    const a6 = t6
+    const a7 = t7
+
+    const wa0 = a0
+    const wa1 = a1
+    const wa2 = a2
+    const wa3 = a3
+    const wa4 = a4
+    const wa5 = a5
+    const wa6 = a6
+    const wa7 = a7
+
+    # RISCV64 uses all eight argument GPRs (a0-a7 == t0-t7); the only
+    # non-argument temporaries left for the WebAssembly scratch
+    # registers are t8 and t9. ws2/ws3 are unavailable, matching the
+    # X86_64 configuration above.
+    const ws0 = t8
+    const ws1 = t9
+    const ws2 = invalidGPR
+    const ws3 = invalidGPR
+
+    const r0 = a0
+    const r1 = a1
+
+    const fa0 = ft0
+    const fa1 = ft1
+    const fa2 = ft2
+    const fa3 = ft3
+
+    const wfa0 = fa0
+    const wfa1 = fa1
+    const wfa2 = fa2
+    const wfa3 = fa3
+    const wfa4 = ft4
+    const wfa5 = ft5
+    const wfa6 = ft6
+    const wfa7 = ft7
+
+    const fr = fa0
 else
     const a0 = t0
     const a1 = t1