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Daniel Golle
df0b899123
Update WPEWebKit to the 2.52 stable major release branch. Includes a pending patchset to get WASM BBQJIT working on RISCV64, upstream PR https://github.com/WebKit/WebKit/pull/65621 Alltogether this brings acceptable performance (even with LLVMPipe Mesa software renderer) on RISCV64. Link: https://wpewebkit.org/release/wpewebkit-2.52.0.html Link: https://wpewebkit.org/release/wpewebkit-2.52.1.html Link: https://wpewebkit.org/release/wpewebkit-2.52.2.html Link: https://wpewebkit.org/release/wpewebkit-2.52.3.html Signed-off-by: Daniel Golle <daniel@makrotopia.org>
44 lines
1.4 KiB
Diff
44 lines
1.4 KiB
Diff
--- a/Source/JavaScriptCore/offlineasm/riscv64.rb
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+++ b/Source/JavaScriptCore/offlineasm/riscv64.rb
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@@ -217,22 +217,32 @@ end
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class FPRegisterID
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def riscv64Operand
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case @name
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+ # The LLInt convention assumes that ft0..ft7 are the platform's
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+ # FP argument registers (used as scratches between calls). On X86
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+ # and ARM64 the FP temp and FP arg registers happen to coincide
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+ # (xmm0-7 / q0-7). RISC-V's ABI splits them: ft0..ft7 = f0..f7 are
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+ # temps, fa0..fa7 = f10..f17 are args. To keep LLInt's wfa* aliases
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+ # (which chain wfa0 -> fa0 -> ft0) resolving to the wasm arg FPRs,
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+ # we map offlineasm's ft0..ft7 directly to physical f10..f17 here.
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+ # Physical f0..f7 become unreachable from offlineasm, but JSC's
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+ # C++-side FPRInfo still uses them as fpRegT8..fpRegT15 (the JIT
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+ # and offlineasm don't share register state across call boundaries).
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when 'ft0'
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- 'f0'
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+ 'f10'
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when 'ft1'
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- 'f1'
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+ 'f11'
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when 'ft2'
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- 'f2'
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+ 'f12'
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when 'ft3'
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- 'f3'
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+ 'f13'
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when 'ft4'
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- 'f4'
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+ 'f14'
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when 'ft5'
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- 'f5'
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+ 'f15'
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when 'ft6'
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- 'f6'
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+ 'f16'
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when 'ft7'
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- 'f7'
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+ 'f17'
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when 'csfr0'
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'f8'
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when 'csfr1'
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