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uboot: sync dosilicon/fmsh/gsto code from linux-rockchip

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2025-03-09 19:50:16 +08:00
committed by hanwckf
parent b5bc2b2dfb
commit 46adcea5d3
6 changed files with 346 additions and 28 deletions
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59
uboot-mtk-20220606/drivers/mtd/nand/spi/dosilicon.c
View File

@@ -1,9 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd
*
* Authors:
* Dingqiang Lin <jon.lin@rock-chips.com>
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
#ifndef __UBOOT__
@@ -22,10 +19,7 @@
#define DOSICON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
@@ -34,8 +28,8 @@ static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static int ds35xxga_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
@@ -228,6 +222,51 @@ static const struct spinand_info dosilicon_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35M4GB-IB",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64),
NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35Q4GB-IB",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB4),
NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35Q12C-IB",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75),
NAND_MEMORG(1, 2048, 128, 64, 512, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35M12C-IB",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
NAND_MEMORG(1, 2048, 128, 64, 512, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35Q2GBS",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
};
static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = {
@@ -239,4 +278,4 @@ const struct spinand_manufacturer dosilicon_spinand_manufacturer = {
.chips = dosilicon_spinand_table,
.nchips = ARRAY_SIZE(dosilicon_spinand_table),
.ops = &dosilicon_spinand_manuf_ops,
};
};

77
uboot-mtk-20220606/drivers/mtd/nand/spi/fmsh.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
*
* Authors:
* Dingqiang Lin <jon.lin@rock-chips.com>
@@ -108,6 +108,61 @@ static int fm25s01bi3_ecc_ecc_get_status(struct spinand_device *spinand,
return -EBADMSG;
}
static int fm25g0xd_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 64;
region->length = 64;
return 0;
}
static int fm25g0xd_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
/* Reserve 2 bytes for the BBM. */
region->offset = 2;
region->length = 62;
return 0;
}
static const struct mtd_ooblayout_ops fm25g0xd_ooblayout = {
.ecc = fm25g0xd_ooblayout_ecc,
.rfree = fm25g0xd_ooblayout_free,
};
/*
* ecc bits: 0xC0[4,6]
* [0x0], No bit errors were detected;
* [0x001, 0x011], Bit errors were detected and corrected. Not
* reach Flipping Bits;
* [0x100], Bit error count equals the bit flip
* detectionthreshold
* [0x101, 0x110], Reserved;
* [0x111], Multiple bit errors were detected and
* not corrected.
*/
static int fm25g0xd_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
struct nand_device *nand = spinand_to_nand(spinand);
u8 eccsr = (status & GENMASK(6, 4)) >> 4;
if (eccsr <= 3)
return 0;
else if (eccsr == 4)
return nand->eccreq.strength;
else
return -EBADMSG;
}
static const struct spinand_info fmsh_spinand_table[] = {
SPINAND_INFO("FM25S01A",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
@@ -154,6 +209,24 @@ static const struct spinand_info fmsh_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
SPINAND_INFO("FM25S02BI3-DND-A-G3",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD6),
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
SPINAND_INFO("FM25G02D",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2),
NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25g0xd_ooblayout, fm25g0xd_ecc_get_status)),
};
static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = {
@@ -165,4 +238,4 @@ const struct spinand_manufacturer fmsh_spinand_manufacturer = {
.chips = fmsh_spinand_table,
.nchips = ARRAY_SIZE(fmsh_spinand_table),
.ops = &fmsh_spinand_manuf_ops,
};
};

51
uboot-mtk-20220606/drivers/mtd/nand/spi/gsto.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*
* Authors:
* Dingqiang Lin <jon.lin@rock-chips.com>
@@ -61,6 +61,35 @@ static const struct mtd_ooblayout_ops gss0xgsak1_ooblayout = {
.rfree = gss0xgsak1_ooblayout_free,
};
static int gss0xgsax1_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 64;
region->length = 64;
return 0;
}
static int gss0xgsax1_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 2;
region->length = 62;
return 0;
}
static const struct mtd_ooblayout_ops gss0xgsax1_ooblayout = {
.ecc = gss0xgsax1_ooblayout_ecc,
.rfree = gss0xgsax1_ooblayout_free,
};
static const struct spinand_info gsto_spinand_table[] = {
SPINAND_INFO("GSS01GSAK1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x13),
@@ -79,7 +108,25 @@ static const struct spinand_info gsto_spinand_table[] = {
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)),
SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
SPINAND_INFO("GSS02GSAX1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA, 0x23),
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
SPINAND_INFO("GSS01GSAX1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA, 0x13),
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
};
static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = {

59
uboot-mtk-20230718-09eda825/drivers/mtd/nand/spi/dosilicon.c
View File

@@ -1,9 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd
*
* Authors:
* Dingqiang Lin <jon.lin@rock-chips.com>
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
#ifndef __UBOOT__
@@ -22,10 +19,7 @@
#define DOSICON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
@@ -34,8 +28,8 @@ static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static int ds35xxga_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
@@ -228,6 +222,51 @@ static const struct spinand_info dosilicon_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35M4GB-IB",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64),
NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35Q4GB-IB",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB4),
NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35Q12C-IB",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75),
NAND_MEMORG(1, 2048, 128, 64, 512, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35M12C-IB",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
NAND_MEMORG(1, 2048, 128, 64, 512, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35Q2GBS",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
};
static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = {
@@ -239,4 +278,4 @@ const struct spinand_manufacturer dosilicon_spinand_manufacturer = {
.chips = dosilicon_spinand_table,
.nchips = ARRAY_SIZE(dosilicon_spinand_table),
.ops = &dosilicon_spinand_manuf_ops,
};
};

77
uboot-mtk-20230718-09eda825/drivers/mtd/nand/spi/fmsh.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
*
* Authors:
* Dingqiang Lin <jon.lin@rock-chips.com>
@@ -108,6 +108,61 @@ static int fm25s01bi3_ecc_ecc_get_status(struct spinand_device *spinand,
return -EBADMSG;
}
static int fm25g0xd_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 64;
region->length = 64;
return 0;
}
static int fm25g0xd_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
/* Reserve 2 bytes for the BBM. */
region->offset = 2;
region->length = 62;
return 0;
}
static const struct mtd_ooblayout_ops fm25g0xd_ooblayout = {
.ecc = fm25g0xd_ooblayout_ecc,
.rfree = fm25g0xd_ooblayout_free,
};
/*
* ecc bits: 0xC0[4,6]
* [0x0], No bit errors were detected;
* [0x001, 0x011], Bit errors were detected and corrected. Not
* reach Flipping Bits;
* [0x100], Bit error count equals the bit flip
* detectionthreshold
* [0x101, 0x110], Reserved;
* [0x111], Multiple bit errors were detected and
* not corrected.
*/
static int fm25g0xd_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
struct nand_device *nand = spinand_to_nand(spinand);
u8 eccsr = (status & GENMASK(6, 4)) >> 4;
if (eccsr <= 3)
return 0;
else if (eccsr == 4)
return nand->eccreq.strength;
else
return -EBADMSG;
}
static const struct spinand_info fmsh_spinand_table[] = {
SPINAND_INFO("FM25S01A",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
@@ -154,6 +209,24 @@ static const struct spinand_info fmsh_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
SPINAND_INFO("FM25S02BI3-DND-A-G3",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD6),
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
SPINAND_INFO("FM25G02D",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2),
NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25g0xd_ooblayout, fm25g0xd_ecc_get_status)),
};
static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = {
@@ -165,4 +238,4 @@ const struct spinand_manufacturer fmsh_spinand_manufacturer = {
.chips = fmsh_spinand_table,
.nchips = ARRAY_SIZE(fmsh_spinand_table),
.ops = &fmsh_spinand_manuf_ops,
};
};

51
uboot-mtk-20230718-09eda825/drivers/mtd/nand/spi/gsto.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*
* Authors:
* Dingqiang Lin <jon.lin@rock-chips.com>
@@ -61,6 +61,35 @@ static const struct mtd_ooblayout_ops gss0xgsak1_ooblayout = {
.rfree = gss0xgsak1_ooblayout_free,
};
static int gss0xgsax1_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 64;
region->length = 64;
return 0;
}
static int gss0xgsax1_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 2;
region->length = 62;
return 0;
}
static const struct mtd_ooblayout_ops gss0xgsax1_ooblayout = {
.ecc = gss0xgsax1_ooblayout_ecc,
.rfree = gss0xgsax1_ooblayout_free,
};
static const struct spinand_info gsto_spinand_table[] = {
SPINAND_INFO("GSS01GSAK1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x13),
@@ -79,7 +108,25 @@ static const struct spinand_info gsto_spinand_table[] = {
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)),
SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
SPINAND_INFO("GSS02GSAX1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA, 0x23),
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
SPINAND_INFO("GSS01GSAX1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA, 0x13),
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
};
static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = {