uboot: add etron spi-nand support
This commit is contained in:
@@ -1,4 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
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spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o etron.o
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obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
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@@ -824,6 +824,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
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µn_spinand_manufacturer,
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&toshiba_spinand_manufacturer,
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&winbond_spinand_manufacturer,
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&etron_spinand_manufacturer,
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};
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static int spinand_manufacturer_match(struct spinand_device *spinand,
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178
uboot-mtk-20220606/drivers/mtd/nand/spi/etron.c
Normal file
178
uboot-mtk-20220606/drivers/mtd/nand/spi/etron.c
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@@ -0,0 +1,178 @@
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// SPDX-License-Identifier: GPL-2.0
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#ifndef __UBOOT__
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#include <malloc.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#endif
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_ETRON 0xD5
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#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4)
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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static int etron_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (14 * section) + 72;
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region->length = 14;
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return 0;
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}
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static int etron_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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if (section) {
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region->offset = 18 * section;
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region->length = 18;
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} else {
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/* section 0 has one byte reserved for bad block mark */
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region->offset = 2;
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region->length = 16;
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}
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return 0;
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}
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static const struct mtd_ooblayout_ops etron_ooblayout = {
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.ecc = etron_ooblayout_ecc,
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.rfree = etron_ooblayout_free,
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};
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static int etron_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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switch (status & STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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case STATUS_ECC_HAS_BITFLIPS:
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return nand->eccreq.strength >> 1;
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case STATUS_ECC_LIMIT_BITFLIPS:
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return nand->eccreq.strength;
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default:
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break;
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}
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return -EINVAL;
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}
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static const struct spinand_info etron_spinand_table[] = {
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/* EM73C 1Gb 3.3V */
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SPINAND_INFO("EM73C044VCF",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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/* EM7xD 2Gb */
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SPINAND_INFO("EM73D044VCR",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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SPINAND_INFO("EM73D044VCO",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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SPINAND_INFO("EM78D044VCM",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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/* EM7xE 4Gb */
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SPINAND_INFO("EM73E044VCE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
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NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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SPINAND_INFO("EM78E044VCD",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
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NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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/* EM7xF044VCA 8Gb */
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SPINAND_INFO("EM73F044VCA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
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NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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SPINAND_INFO("EM78F044VCA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
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NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
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};
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const struct spinand_manufacturer etron_spinand_manufacturer = {
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.id = SPINAND_MFR_ETRON,
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.name = "Etron",
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.chips = etron_spinand_table,
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.nchips = ARRAY_SIZE(etron_spinand_table),
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.ops = &etron_spinand_manuf_ops,
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};
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@@ -238,6 +238,7 @@ extern const struct spinand_manufacturer macronix_spinand_manufacturer;
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extern const struct spinand_manufacturer micron_spinand_manufacturer;
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extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
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extern const struct spinand_manufacturer winbond_spinand_manufacturer;
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extern const struct spinand_manufacturer etron_spinand_manufacturer;
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/**
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* struct spinand_op_variants - SPI NAND operation variants
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