uboot: add support for xiaomi ax3000t an8855 variant
This commit is contained in:
hanwckf
1
atf-20220606-637ba581b/configs/mt7981_ax3000t_an8855_defconfig
Symbolic link
1
atf-20220606-637ba581b/configs/mt7981_ax3000t_an8855_defconfig
Symbolic link
@@ -0,0 +1 @@
|
||||
mt7981_ax3000t_defconfig
|
||||
12
uboot-mtk-20220606/arch/arm/dts/mt7981-ax3000t-an8855.dts
Normal file
12
uboot-mtk-20220606/arch/arm/dts/mt7981-ax3000t-an8855.dts
Normal file
@@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7981-ax3000t.dts"
|
||||
|
||||
/ {
|
||||
model = "mt7981-xiaomi-ax3000t-an8855";
|
||||
};
|
||||
|
||||
ð {
|
||||
mediatek,switch = "an8855";
|
||||
};
|
||||
94
uboot-mtk-20220606/configs/mt7981_ax3000t_an8855_defconfig
Normal file
94
uboot-mtk-20220606/configs/mt7981_ax3000t_an8855_defconfig
Normal file
@@ -0,0 +1,94 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-ax3000t-an8855"
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_ENABLE_NAND_NMBM=y
|
||||
CONFIG_MEDIATEK_BOOTMENU=y
|
||||
CONFIG_MEDIATEK_BOOTMENU_DELAY=3
|
||||
CONFIG_MEDIATEK_LOAD_FROM_RAM=y
|
||||
CONFIG_MT7981_BOOTMENU_UBI=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_AUTOBOOT_MENU_SHOW=y
|
||||
CONFIG_AUTOBOOT_MENU_MTK_SHOW=y
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-spim-nand-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_POLLER=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPIO_READ=y
|
||||
CONFIG_CMD_MTD=y
|
||||
# CONFIG_CMD_NAND_EXT is not set
|
||||
CONFIG_CMD_NMBM=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_LED_BLINK=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nmbm0=nmbm0"
|
||||
CONFIG_MTDPARTS_DEFAULT="nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),112m(ubi),256k(KF)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_CMD_GL_BTN=y
|
||||
CONFIG_CMD_SHOW_MTD_LAYOUT=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MTD=y
|
||||
CONFIG_ENV_MTD_NAME="nmbm0"
|
||||
CONFIG_ENV_SIZE_REDUND=0x80000
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NET_FORCE_IPADDR=y
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BUTTON=y
|
||||
CONFIG_BUTTON_GPIO=y
|
||||
CONFIG_CLK=y
|
||||
# CONFIG_I2C is not set
|
||||
# CONFIG_INPUT is not set
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MTK_SPIM=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_MTK_TIMER=y
|
||||
CONFIG_HEXDUMP=y
|
||||
CONFIG_WEBUI_FAILSAFE=y
|
||||
CONFIG_WEBUI_FAILSAFE_ON_AUTOBOOT_FAIL=y
|
||||
@@ -0,0 +1,93 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-ax3000t-an8855"
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_ENABLE_NAND_NMBM=y
|
||||
CONFIG_MEDIATEK_BOOTMENU=y
|
||||
CONFIG_MEDIATEK_BOOTMENU_DELAY=3
|
||||
CONFIG_MEDIATEK_MULTI_MTD_LAYOUT=y
|
||||
CONFIG_MEDIATEK_LOAD_FROM_RAM=y
|
||||
CONFIG_MT7981_BOOTMENU_UBI=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_AUTOBOOT_MENU_SHOW=y
|
||||
CONFIG_AUTOBOOT_MENU_MTK_SHOW=y
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-spim-nand-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_POLLER=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPIO_READ=y
|
||||
CONFIG_CMD_MTD=y
|
||||
# CONFIG_CMD_NAND_EXT is not set
|
||||
CONFIG_CMD_NMBM=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_LED_BLINK=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_CMD_GL_BTN=y
|
||||
CONFIG_CMD_SHOW_MTD_LAYOUT=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MTD=y
|
||||
CONFIG_ENV_MTD_NAME="nmbm0"
|
||||
CONFIG_ENV_SIZE_REDUND=0x80000
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NET_FORCE_IPADDR=y
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BUTTON=y
|
||||
CONFIG_BUTTON_GPIO=y
|
||||
CONFIG_CLK=y
|
||||
# CONFIG_I2C is not set
|
||||
# CONFIG_INPUT is not set
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MTK_SPIM=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_MTK_TIMER=y
|
||||
CONFIG_HEXDUMP=y
|
||||
CONFIG_WEBUI_FAILSAFE=y
|
||||
CONFIG_WEBUI_FAILSAFE_ON_AUTOBOOT_FAIL=y
|
||||
File diff suppressed because it is too large
Load Diff
@@ -172,6 +172,7 @@
|
||||
#define SPEED_10M 0
|
||||
#define SPEED_100M 1
|
||||
#define SPEED_1000M 2
|
||||
#define SPEED_2500M 3
|
||||
|
||||
#define GMAC_TRGMII_RCK_CTRL 0x300
|
||||
#define RX_RST BIT(31)
|
||||
@@ -195,6 +196,150 @@
|
||||
#define VLAN_ATTR_S 6
|
||||
#define VLAN_ATTR_M 0xc0
|
||||
|
||||
/* AN8855 regs */
|
||||
#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
|
||||
|
||||
#define AN8855_CHIP_ID 0x10005000
|
||||
#define AN8855_CHIP_REV 0x10005004
|
||||
#define AN8855_EFUSE_DATA0 0x1000a500
|
||||
|
||||
#define AN8855_WORD_SIZE 4
|
||||
#define AN8855_PORT_CTRL_BASE 0x10208000
|
||||
#define AN8855_PORT_CTRL_PORT_OFFSET 0x200
|
||||
#define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + \
|
||||
(p) * AN8855_PORT_CTRL_PORT_OFFSET + (r))
|
||||
#define AN8855_PCR(p) AN8855_PORT_CTRL_REG(p, 0x04)
|
||||
#define AN8855_PVC(p) AN8855_PORT_CTRL_REG(p, 0x10)
|
||||
#define AN8855_PORTMATRIX(p) AN8855_PORT_CTRL_REG(p, 0x44)
|
||||
#define AN8855_PVID(p) AN8855_PORT_CTRL_REG(p, 0x48)
|
||||
|
||||
#define AN8855_PORT_MAC_CTRL_BASE 0x10210000
|
||||
#define AN8855_PORT_MAC_CTRL_PORT_OFFSET 0x200
|
||||
#define AN8855_PORT_MAC_CTRL_REG(p, r) (AN8855_PORT_MAC_CTRL_BASE + \
|
||||
(p) * AN8855_PORT_MAC_CTRL_PORT_OFFSET + (r))
|
||||
#define AN8855_PMCR(p) AN8855_PORT_MAC_CTRL_REG(p, 0x00)
|
||||
#define AN8855_PMSR(p) AN8855_PORT_MAC_CTRL_REG(p, 0x10)
|
||||
|
||||
#define AN8855_GMACCR (AN8855_PORT_MAC_CTRL_BASE + 0x3e00)
|
||||
|
||||
#define AN8855_FORCE_TX_FC BIT(4)
|
||||
#define AN8855_FORCE_RX_FC BIT(5)
|
||||
#define AN8855_FORCE_DPX BIT(25)
|
||||
#define AN8855_FORCE_SPD BITS(28, 30)
|
||||
#define AN8855_FORCE_LNK BIT(24)
|
||||
#define AN8855_FORCE_MODE BIT(31)
|
||||
|
||||
#define AN8855_PMCR_DEFAULT (AN8855_FORCE_MODE | \
|
||||
AN8855_FORCE_DPX | AN8855_FORCE_LNK | AN8855_FORCE_TX_FC | AN8855_FORCE_RX_FC)
|
||||
|
||||
#define AN8855_SYS_CTRL 0x100050C0
|
||||
#define AN8855_SW_SYS_RST BIT(31)
|
||||
|
||||
#define SCU_BASE 0x10000000
|
||||
#define RG_RGMII_TXCK_C (SCU_BASE + 0x1d0)
|
||||
#define RG_GPIO_LED_MODE (SCU_BASE + 0x0054)
|
||||
#define RG_GPIO_LED_SEL(i) (SCU_BASE + (0x0058 + ((i) * 4)))
|
||||
#define RG_INTB_MODE (SCU_BASE + 0x0080)
|
||||
#define RG_GDMP_RAM (SCU_BASE + 0x10000)
|
||||
#define RG_GPIO_L_INV (SCU_BASE + 0x0010)
|
||||
#define RG_GPIO_CTRL (SCU_BASE + 0xa300)
|
||||
#define RG_GPIO_DATA (SCU_BASE + 0xa304)
|
||||
#define RG_GPIO_OE (SCU_BASE + 0xa314)
|
||||
|
||||
#define AN8855_PKG_SEL 0x10000094
|
||||
#define PAG_SEL_AN8855H 0x2
|
||||
|
||||
#define AN8855_CKGCR 0x10213E1C
|
||||
#define CKG_LNKDN_GLB_STOP 0x01
|
||||
#define CKG_LNKDN_PORT_STOP 0x02
|
||||
|
||||
#define QP_PMA_TOP_BASE 0x1022e000
|
||||
#define PON_RXFEDIG_CTRL_0 (QP_PMA_TOP_BASE + 0x100)
|
||||
#define PON_RXFEDIG_CTRL_9 (QP_PMA_TOP_BASE + 0x124)
|
||||
|
||||
#define SS_LCPLL_PWCTL_SETTING_2 (QP_PMA_TOP_BASE + 0x208)
|
||||
#define SS_LCPLL_TDC_FLT_2 (QP_PMA_TOP_BASE + 0x230)
|
||||
#define SS_LCPLL_TDC_FLT_5 (QP_PMA_TOP_BASE + 0x23c)
|
||||
#define SS_LCPLL_TDC_PCW_1 (QP_PMA_TOP_BASE + 0x248)
|
||||
#define INTF_CTRL_8 (QP_PMA_TOP_BASE + 0x320)
|
||||
#define INTF_CTRL_9 (QP_PMA_TOP_BASE + 0x324)
|
||||
#define INTF_CTRL_10 (QP_PMA_TOP_BASE + 0x328)
|
||||
#define INTF_CTRL_11 (QP_PMA_TOP_BASE + 0x32c)
|
||||
#define PLL_CTRL_0 (QP_PMA_TOP_BASE + 0x400)
|
||||
#define PLL_CTRL_2 (QP_PMA_TOP_BASE + 0x408)
|
||||
#define PLL_CTRL_3 (QP_PMA_TOP_BASE + 0x40c)
|
||||
#define PLL_CTRL_4 (QP_PMA_TOP_BASE + 0x410)
|
||||
#define PLL_CK_CTRL_0 (QP_PMA_TOP_BASE + 0x414)
|
||||
#define RX_DLY_0 (QP_PMA_TOP_BASE + 0x614)
|
||||
#define RX_CTRL_2 (QP_PMA_TOP_BASE + 0x630)
|
||||
#define RX_CTRL_5 (QP_PMA_TOP_BASE + 0x63c)
|
||||
#define RX_CTRL_6 (QP_PMA_TOP_BASE + 0x640)
|
||||
#define RX_CTRL_7 (QP_PMA_TOP_BASE + 0x644)
|
||||
#define RX_CTRL_8 (QP_PMA_TOP_BASE + 0x648)
|
||||
#define RX_CTRL_26 (QP_PMA_TOP_BASE + 0x690)
|
||||
#define RX_CTRL_42 (QP_PMA_TOP_BASE + 0x6d0)
|
||||
|
||||
#define QP_ANA_CSR_BASE 0x1022f000
|
||||
#define RG_QP_RX_DAC_EN (QP_ANA_CSR_BASE + 0x00)
|
||||
#define RG_QP_RXAFE_RESERVE (QP_ANA_CSR_BASE + 0x04)
|
||||
#define RG_QP_CDR_LPF_BOT_LIM (QP_ANA_CSR_BASE + 0x08)
|
||||
#define RG_QP_CDR_LPF_MJV_LIM (QP_ANA_CSR_BASE + 0x0c)
|
||||
#define RG_QP_CDR_LPF_SETVALUE (QP_ANA_CSR_BASE + 0x14)
|
||||
#define RG_QP_CDR_PR_CKREF_DIV1 (QP_ANA_CSR_BASE + 0x18)
|
||||
#define RG_QP_CDR_PR_KBAND_DIV_PCIE (QP_ANA_CSR_BASE + 0x1c)
|
||||
#define RG_QP_CDR_FORCE_IBANDLPF_R_OFF (QP_ANA_CSR_BASE + 0x20)
|
||||
#define RG_QP_TX_MODE_16B_EN (QP_ANA_CSR_BASE + 0x28)
|
||||
#define RG_QP_PLL_IPLL_DIG_PWR_SEL (QP_ANA_CSR_BASE + 0x3c)
|
||||
#define RG_QP_PLL_SDM_ORD (QP_ANA_CSR_BASE + 0x40)
|
||||
|
||||
#define HSGMII_AN_CSR_BASE 0x10220000
|
||||
#define SGMII_REG_AN0 (HSGMII_AN_CSR_BASE + 0x000)
|
||||
#define SGMII_REG_AN_13 (HSGMII_AN_CSR_BASE + 0x034)
|
||||
#define SGMII_REG_AN_FORCE_CL37 (HSGMII_AN_CSR_BASE + 0x060)
|
||||
|
||||
#define HSGMII_CSR_PCS_BASE 0x10220000
|
||||
#define RG_HSGMII_PCS_CTROL_1 (HSGMII_CSR_PCS_BASE + 0xa00)
|
||||
#define RG_AN_SGMII_MODE_FORCE (HSGMII_CSR_PCS_BASE + 0xa24)
|
||||
|
||||
#define ETHER_SYS_BASE 0x1028c800
|
||||
#define RG_GPHY_AFE_PWD (ETHER_SYS_BASE + 0x40)
|
||||
#define RG_GPHY_SMI_ADDR (ETHER_SYS_BASE + 0x48)
|
||||
#define RG_P5MUX_MODE (ETHER_SYS_BASE + 0x00)
|
||||
#define RG_FORCE_CKDIR_SEL (ETHER_SYS_BASE + 0x04)
|
||||
#define RG_SWITCH_MODE (ETHER_SYS_BASE + 0x08)
|
||||
#define RG_FORCE_MAC5_SB (ETHER_SYS_BASE + 0x2c)
|
||||
#define RG_GPHY_AFE_PWD (ETHER_SYS_BASE + 0x40)
|
||||
#define RG_GPHY_SMI_ADDR (ETHER_SYS_BASE + 0x48)
|
||||
#define CSR_RMII (ETHER_SYS_BASE + 0x70)
|
||||
|
||||
#define QP_DIG_CSR_BASE 0x1022a000
|
||||
#define QP_CK_RST_CTRL_4 (QP_DIG_CSR_BASE + 0x310)
|
||||
#define QP_DIG_MODE_CTRL_0 (QP_DIG_CSR_BASE + 0x324)
|
||||
#define QP_DIG_MODE_CTRL_1 (QP_DIG_CSR_BASE + 0x330)
|
||||
|
||||
#define MULTI_SGMII_CSR_BASE 0x10224000
|
||||
#define SGMII_STS_CTRL_0 (MULTI_SGMII_CSR_BASE + 0x018)
|
||||
#define MSG_RX_CTRL_0 (MULTI_SGMII_CSR_BASE + 0x100)
|
||||
#define MSG_RX_LIK_STS_0 (MULTI_SGMII_CSR_BASE + 0x514)
|
||||
#define MSG_RX_LIK_STS_2 (MULTI_SGMII_CSR_BASE + 0x51c)
|
||||
#define PHY_RX_FORCE_CTRL_0 (MULTI_SGMII_CSR_BASE + 0x520)
|
||||
|
||||
#define MULTI_PHY_RA_CSR_BASE 0x10226000
|
||||
#define RG_RATE_ADAPT_CTRL_0 (MULTI_PHY_RA_CSR_BASE + 0x000)
|
||||
#define RATE_ADP_P0_CTRL_0 (MULTI_PHY_RA_CSR_BASE + 0x100)
|
||||
#define MII_RA_AN_ENABLE (MULTI_PHY_RA_CSR_BASE + 0x300)
|
||||
|
||||
#define RG_CLK_CPU_ICG 0x10005034
|
||||
#define MCU_ENABLE BIT(3)
|
||||
|
||||
#define RG_TIMER_CTL 0x1000a100
|
||||
#define WDOG_ENABLE BIT(25)
|
||||
|
||||
#define PHY_TX_PAIR_DLY_SEL_GBE 0x013
|
||||
#define PHY_RXADC_CTRL 0x0d8
|
||||
#define PHY_RXADC_REV_0 0x0d9
|
||||
#define PHY_RXADC_REV_1 0x0da
|
||||
|
||||
/* VLAN_ATTR: VLAN attributes */
|
||||
#define VLAN_ATTR_USER 0
|
||||
#define VLAN_ATTR_STACK 1
|
||||
@@ -406,6 +551,9 @@
|
||||
#define REG_GSWCK_EN BIT(0)
|
||||
#define REG_TRGMIICK_EN BIT(1)
|
||||
|
||||
#define PHY_DEV07 0x07
|
||||
#define PHY_DEV07_REG_03C 0x3c
|
||||
|
||||
/* Extend PHY Control Register 3 */
|
||||
#define PHY_EXT_REG_14 0x14
|
||||
|
||||
@@ -421,6 +569,8 @@
|
||||
/* PHY RXADC Control Register 7 */
|
||||
#define PHY_DEV1E_REG_0C6 0x0c6
|
||||
|
||||
#define PHY_DEV1E 0x1e
|
||||
|
||||
/* Fields of PHY_DEV1E_REG_0C6 */
|
||||
#define PHY_POWER_SAVING_S 8
|
||||
#define PHY_POWER_SAVING_M 0x300
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7981-ax3000t.dts"
|
||||
|
||||
/ {
|
||||
model = "mt7981-xiaomi-ax3000t-an8855";
|
||||
};
|
||||
|
||||
ð {
|
||||
mediatek,switch = "an8855";
|
||||
};
|
||||
@@ -0,0 +1,103 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-ax3000t-an8855"
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_MEDIATEK_BOOTMENU=y
|
||||
CONFIG_MEDIATEK_BOOTMENU_DELAY=3
|
||||
CONFIG_MTK_WEB_FAILSAFE=y
|
||||
CONFIG_MTK_WEB_FAILSAFE_AFTER_BOOT_FAILURE=y
|
||||
CONFIG_MTK_UBI_SUPPORT=y
|
||||
CONFIG_MTK_UPGRADE_BL2_VERIFY=y
|
||||
# CONFIG_MTK_UPGRADE_IMAGE_VERIFY is not set
|
||||
CONFIG_ENABLE_NAND_NMBM=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_AUTOBOOT_MENU_SHOW=y
|
||||
CONFIG_AUTOBOOT_MENU_MTK_SHOW=y
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-spim-nand-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_PBSIZE=1049
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPIO_READ=y
|
||||
CONFIG_CMD_PWM=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_NMBM=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nmbm0=nmbm0"
|
||||
CONFIG_MTDPARTS_DEFAULT="nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),112m(ubi),256k(KF)"
|
||||
CONFIG_CMD_GL_BTN=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MTD=y
|
||||
CONFIG_ENV_MTD_NAME="Nvram"
|
||||
CONFIG_ENV_SIZE_REDUND=0x80000
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NET_FORCE_IPADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_USE_IPADDR=y
|
||||
CONFIG_IPADDR="192.168.1.1"
|
||||
CONFIG_USE_NETMASK=y
|
||||
CONFIG_NETMASK="255.255.255.0"
|
||||
CONFIG_USE_SERVERIP=y
|
||||
CONFIG_SERVERIP="192.168.1.2"
|
||||
CONFIG_PROT_TCP=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BUTTON=y
|
||||
CONFIG_BUTTON_GPIO=y
|
||||
CONFIG_CLK=y
|
||||
# CONFIG_I2C is not set
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_PWM=y
|
||||
CONFIG_PWM_MTK=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MTK_SPIM=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_MTK_TIMER=y
|
||||
CONFIG_HEXDUMP=y
|
||||
@@ -0,0 +1,102 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-ax3000t-an8855"
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_MEDIATEK_BOOTMENU=y
|
||||
CONFIG_MEDIATEK_BOOTMENU_DELAY=3
|
||||
CONFIG_MTK_WEB_FAILSAFE=y
|
||||
CONFIG_MTK_WEB_FAILSAFE_AFTER_BOOT_FAILURE=y
|
||||
CONFIG_MTK_UBI_SUPPORT=y
|
||||
CONFIG_MEDIATEK_MULTI_MTD_LAYOUT=y
|
||||
CONFIG_MTK_UPGRADE_BL2_VERIFY=y
|
||||
# CONFIG_MTK_UPGRADE_IMAGE_VERIFY is not set
|
||||
CONFIG_ENABLE_NAND_NMBM=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_AUTOBOOT_MENU_SHOW=y
|
||||
CONFIG_AUTOBOOT_MENU_MTK_SHOW=y
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-spim-nand-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_PBSIZE=1049
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPIO_READ=y
|
||||
CONFIG_CMD_PWM=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_NMBM=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_CMD_GL_BTN=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MTD=y
|
||||
CONFIG_ENV_MTD_NAME="Nvram"
|
||||
CONFIG_ENV_SIZE_REDUND=0x80000
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NET_FORCE_IPADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_USE_IPADDR=y
|
||||
CONFIG_IPADDR="192.168.1.1"
|
||||
CONFIG_USE_NETMASK=y
|
||||
CONFIG_NETMASK="255.255.255.0"
|
||||
CONFIG_USE_SERVERIP=y
|
||||
CONFIG_SERVERIP="192.168.1.2"
|
||||
CONFIG_PROT_TCP=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BUTTON=y
|
||||
CONFIG_BUTTON_GPIO=y
|
||||
CONFIG_CLK=y
|
||||
# CONFIG_I2C is not set
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_PWM=y
|
||||
CONFIG_PWM_MTK=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MTK_SPIM=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_MTK_TIMER=y
|
||||
CONFIG_HEXDUMP=y
|
||||
File diff suppressed because it is too large
Load Diff
@@ -248,6 +248,7 @@ enum mkt_eth_capabilities {
|
||||
#define SPEED_10M 0
|
||||
#define SPEED_100M 1
|
||||
#define SPEED_1000M 2
|
||||
#define SPEED_2500M 3
|
||||
|
||||
#define GMAC_TRGMII_RCK_CTRL 0x300
|
||||
#define RX_RST BIT(31)
|
||||
@@ -281,6 +282,150 @@ enum mkt_eth_capabilities {
|
||||
#define VLAN_ATTR_S 6
|
||||
#define VLAN_ATTR_M 0xc0
|
||||
|
||||
/* AN8855 regs */
|
||||
#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
|
||||
|
||||
#define AN8855_CHIP_ID 0x10005000
|
||||
#define AN8855_CHIP_REV 0x10005004
|
||||
#define AN8855_EFUSE_DATA0 0x1000a500
|
||||
#define AN8855_WORD_SIZE 4
|
||||
|
||||
#define AN8855_PORT_CTRL_BASE 0x10208000
|
||||
#define AN8855_PORT_CTRL_PORT_OFFSET 0x200
|
||||
#define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + \
|
||||
(p) * AN8855_PORT_CTRL_PORT_OFFSET + (r))
|
||||
#define AN8855_PCR(p) AN8855_PORT_CTRL_REG(p, 0x04)
|
||||
#define AN8855_PVC(p) AN8855_PORT_CTRL_REG(p, 0x10)
|
||||
#define AN8855_PORTMATRIX(p) AN8855_PORT_CTRL_REG(p, 0x44)
|
||||
#define AN8855_PVID(p) AN8855_PORT_CTRL_REG(p, 0x48)
|
||||
|
||||
#define AN8855_PORT_MAC_CTRL_BASE 0x10210000
|
||||
#define AN8855_PORT_MAC_CTRL_PORT_OFFSET 0x200
|
||||
#define AN8855_PORT_MAC_CTRL_REG(p, r) (AN8855_PORT_MAC_CTRL_BASE + \
|
||||
(p) * AN8855_PORT_MAC_CTRL_PORT_OFFSET + (r))
|
||||
#define AN8855_PMCR(p) AN8855_PORT_MAC_CTRL_REG(p, 0x00)
|
||||
#define AN8855_PMSR(p) AN8855_PORT_MAC_CTRL_REG(p, 0x10)
|
||||
|
||||
#define AN8855_GMACCR (AN8855_PORT_MAC_CTRL_BASE + 0x3e00)
|
||||
|
||||
#define AN8855_FORCE_TX_FC BIT(4)
|
||||
#define AN8855_FORCE_RX_FC BIT(5)
|
||||
#define AN8855_FORCE_DPX BIT(25)
|
||||
#define AN8855_FORCE_SPD BITS(28, 30)
|
||||
#define AN8855_FORCE_LNK BIT(24)
|
||||
#define AN8855_FORCE_MODE BIT(31)
|
||||
|
||||
#define AN8855_PMCR_DEFAULT (AN8855_FORCE_MODE | \
|
||||
AN8855_FORCE_DPX | AN8855_FORCE_LNK | AN8855_FORCE_TX_FC | AN8855_FORCE_RX_FC)
|
||||
|
||||
#define AN8855_SYS_CTRL 0x100050C0
|
||||
#define AN8855_SW_SYS_RST BIT(31)
|
||||
|
||||
#define SCU_BASE 0x10000000
|
||||
#define RG_RGMII_TXCK_C (SCU_BASE + 0x1d0)
|
||||
#define RG_GPIO_LED_MODE (SCU_BASE + 0x0054)
|
||||
#define RG_GPIO_LED_SEL(i) (SCU_BASE + (0x0058 + ((i) * 4)))
|
||||
#define RG_INTB_MODE (SCU_BASE + 0x0080)
|
||||
#define RG_GDMP_RAM (SCU_BASE + 0x10000)
|
||||
#define RG_GPIO_L_INV (SCU_BASE + 0x0010)
|
||||
#define RG_GPIO_CTRL (SCU_BASE + 0xa300)
|
||||
#define RG_GPIO_DATA (SCU_BASE + 0xa304)
|
||||
#define RG_GPIO_OE (SCU_BASE + 0xa314)
|
||||
|
||||
#define AN8855_PKG_SEL 0x10000094
|
||||
#define PAG_SEL_AN8855H 0x2
|
||||
|
||||
#define AN8855_CKGCR 0x10213E1C
|
||||
#define CKG_LNKDN_GLB_STOP 0x01
|
||||
#define CKG_LNKDN_PORT_STOP 0x02
|
||||
|
||||
#define QP_PMA_TOP_BASE 0x1022e000
|
||||
#define PON_RXFEDIG_CTRL_0 (QP_PMA_TOP_BASE + 0x100)
|
||||
#define PON_RXFEDIG_CTRL_9 (QP_PMA_TOP_BASE + 0x124)
|
||||
|
||||
#define SS_LCPLL_PWCTL_SETTING_2 (QP_PMA_TOP_BASE + 0x208)
|
||||
#define SS_LCPLL_TDC_FLT_2 (QP_PMA_TOP_BASE + 0x230)
|
||||
#define SS_LCPLL_TDC_FLT_5 (QP_PMA_TOP_BASE + 0x23c)
|
||||
#define SS_LCPLL_TDC_PCW_1 (QP_PMA_TOP_BASE + 0x248)
|
||||
#define INTF_CTRL_8 (QP_PMA_TOP_BASE + 0x320)
|
||||
#define INTF_CTRL_9 (QP_PMA_TOP_BASE + 0x324)
|
||||
#define INTF_CTRL_10 (QP_PMA_TOP_BASE + 0x328)
|
||||
#define INTF_CTRL_11 (QP_PMA_TOP_BASE + 0x32c)
|
||||
#define PLL_CTRL_0 (QP_PMA_TOP_BASE + 0x400)
|
||||
#define PLL_CTRL_2 (QP_PMA_TOP_BASE + 0x408)
|
||||
#define PLL_CTRL_3 (QP_PMA_TOP_BASE + 0x40c)
|
||||
#define PLL_CTRL_4 (QP_PMA_TOP_BASE + 0x410)
|
||||
#define PLL_CK_CTRL_0 (QP_PMA_TOP_BASE + 0x414)
|
||||
#define RX_DLY_0 (QP_PMA_TOP_BASE + 0x614)
|
||||
#define RX_CTRL_2 (QP_PMA_TOP_BASE + 0x630)
|
||||
#define RX_CTRL_5 (QP_PMA_TOP_BASE + 0x63c)
|
||||
#define RX_CTRL_6 (QP_PMA_TOP_BASE + 0x640)
|
||||
#define RX_CTRL_7 (QP_PMA_TOP_BASE + 0x644)
|
||||
#define RX_CTRL_8 (QP_PMA_TOP_BASE + 0x648)
|
||||
#define RX_CTRL_26 (QP_PMA_TOP_BASE + 0x690)
|
||||
#define RX_CTRL_42 (QP_PMA_TOP_BASE + 0x6d0)
|
||||
|
||||
#define QP_ANA_CSR_BASE 0x1022f000
|
||||
#define RG_QP_RX_DAC_EN (QP_ANA_CSR_BASE + 0x00)
|
||||
#define RG_QP_RXAFE_RESERVE (QP_ANA_CSR_BASE + 0x04)
|
||||
#define RG_QP_CDR_LPF_BOT_LIM (QP_ANA_CSR_BASE + 0x08)
|
||||
#define RG_QP_CDR_LPF_MJV_LIM (QP_ANA_CSR_BASE + 0x0c)
|
||||
#define RG_QP_CDR_LPF_SETVALUE (QP_ANA_CSR_BASE + 0x14)
|
||||
#define RG_QP_CDR_PR_CKREF_DIV1 (QP_ANA_CSR_BASE + 0x18)
|
||||
#define RG_QP_CDR_PR_KBAND_DIV_PCIE (QP_ANA_CSR_BASE + 0x1c)
|
||||
#define RG_QP_CDR_FORCE_IBANDLPF_R_OFF (QP_ANA_CSR_BASE + 0x20)
|
||||
#define RG_QP_TX_MODE_16B_EN (QP_ANA_CSR_BASE + 0x28)
|
||||
#define RG_QP_PLL_IPLL_DIG_PWR_SEL (QP_ANA_CSR_BASE + 0x3c)
|
||||
#define RG_QP_PLL_SDM_ORD (QP_ANA_CSR_BASE + 0x40)
|
||||
|
||||
#define HSGMII_AN_CSR_BASE 0x10220000
|
||||
#define SGMII_REG_AN0 (HSGMII_AN_CSR_BASE + 0x000)
|
||||
#define SGMII_REG_AN_13 (HSGMII_AN_CSR_BASE + 0x034)
|
||||
#define SGMII_REG_AN_FORCE_CL37 (HSGMII_AN_CSR_BASE + 0x060)
|
||||
|
||||
#define HSGMII_CSR_PCS_BASE 0x10220000
|
||||
#define RG_HSGMII_PCS_CTROL_1 (HSGMII_CSR_PCS_BASE + 0xa00)
|
||||
#define RG_AN_SGMII_MODE_FORCE (HSGMII_CSR_PCS_BASE + 0xa24)
|
||||
|
||||
#define ETHER_SYS_BASE 0x1028c800
|
||||
#define RG_GPHY_AFE_PWD (ETHER_SYS_BASE + 0x40)
|
||||
#define RG_GPHY_SMI_ADDR (ETHER_SYS_BASE + 0x48)
|
||||
#define RG_P5MUX_MODE (ETHER_SYS_BASE + 0x00)
|
||||
#define RG_FORCE_CKDIR_SEL (ETHER_SYS_BASE + 0x04)
|
||||
#define RG_SWITCH_MODE (ETHER_SYS_BASE + 0x08)
|
||||
#define RG_FORCE_MAC5_SB (ETHER_SYS_BASE + 0x2c)
|
||||
#define RG_GPHY_AFE_PWD (ETHER_SYS_BASE + 0x40)
|
||||
#define RG_GPHY_SMI_ADDR (ETHER_SYS_BASE + 0x48)
|
||||
#define CSR_RMII (ETHER_SYS_BASE + 0x70)
|
||||
|
||||
#define QP_DIG_CSR_BASE 0x1022a000
|
||||
#define QP_CK_RST_CTRL_4 (QP_DIG_CSR_BASE + 0x310)
|
||||
#define QP_DIG_MODE_CTRL_0 (QP_DIG_CSR_BASE + 0x324)
|
||||
#define QP_DIG_MODE_CTRL_1 (QP_DIG_CSR_BASE + 0x330)
|
||||
|
||||
#define MULTI_SGMII_CSR_BASE 0x10224000
|
||||
#define SGMII_STS_CTRL_0 (MULTI_SGMII_CSR_BASE + 0x018)
|
||||
#define MSG_RX_CTRL_0 (MULTI_SGMII_CSR_BASE + 0x100)
|
||||
#define MSG_RX_LIK_STS_0 (MULTI_SGMII_CSR_BASE + 0x514)
|
||||
#define MSG_RX_LIK_STS_2 (MULTI_SGMII_CSR_BASE + 0x51c)
|
||||
#define PHY_RX_FORCE_CTRL_0 (MULTI_SGMII_CSR_BASE + 0x520)
|
||||
|
||||
#define MULTI_PHY_RA_CSR_BASE 0x10226000
|
||||
#define RG_RATE_ADAPT_CTRL_0 (MULTI_PHY_RA_CSR_BASE + 0x000)
|
||||
#define RATE_ADP_P0_CTRL_0 (MULTI_PHY_RA_CSR_BASE + 0x100)
|
||||
#define MII_RA_AN_ENABLE (MULTI_PHY_RA_CSR_BASE + 0x300)
|
||||
|
||||
#define RG_CLK_CPU_ICG 0x10005034
|
||||
#define MCU_ENABLE BIT(3)
|
||||
|
||||
#define RG_TIMER_CTL 0x1000a100
|
||||
#define WDOG_ENABLE BIT(25)
|
||||
|
||||
#define PHY_TX_PAIR_DLY_SEL_GBE 0x013
|
||||
#define PHY_RXADC_CTRL 0x0d8
|
||||
#define PHY_RXADC_REV_0 0x0d9
|
||||
#define PHY_RXADC_REV_1 0x0da
|
||||
|
||||
/* VLAN_ATTR: VLAN attributes */
|
||||
#define VLAN_ATTR_USER 0
|
||||
#define VLAN_ATTR_STACK 1
|
||||
@@ -495,9 +640,14 @@ enum mkt_eth_capabilities {
|
||||
#define REG_GSWCK_EN BIT(0)
|
||||
#define REG_TRGMIICK_EN BIT(1)
|
||||
|
||||
#define PHY_DEV07 0x07
|
||||
#define PHY_DEV07_REG_03C 0x3c
|
||||
|
||||
/* Extend PHY Control Register 3 */
|
||||
#define PHY_EXT_REG_14 0x14
|
||||
|
||||
#define PHY_DEV1E 0x1e
|
||||
|
||||
/* Fields of PHY_EXT_REG_14 */
|
||||
#define PHY_EN_DOWN_SHFIT BIT(4)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user