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atf-20250711: apply openwrt patches (#136)

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* atf-20250711: apply openwrt patches

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>

* atf-20250711: use shared configs with atf-20240117-bacca82a8

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>

---------

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2025-08-22 19:22:15 +08:00
committed by GitHub
parent e1d742f164
commit be684fbca4
14 changed files with 86 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

0
atf-20250711/configs/mt7987_airpi_h5000m_defconfig → atf-20240117-bacca82a8/configs/mt7987_airpi_h5000m_defconfig
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0
atf-20250711/configs/mt7987_emmc_ddr4_defconfig → atf-20240117-bacca82a8/configs/mt7987_emmc_ddr4_defconfig
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1
atf-20250711/configs Symbolic link
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@@ -0,0 +1 @@
../atf-20240117-bacca82a8/configs

0
atf-20250711/configs/mt7622_rfb_snfi_nand_defconfig
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1
atf-20250711/configs/mt7629_rfb_snfi_nand_defconfig
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@@ -1 +0,0 @@
_PLAT_MT7629=y

3
atf-20250711/configs/mt7981_rfb_spim_nand_defconfig
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@@ -1,3 +0,0 @@
_PLAT_MT7981=y
_MT7981_BOARD_BGA=y
_ENABLE_EMERG_MEM_DUMP=y

3
atf-20250711/configs/mt7986_rfb_spim_nand_defconfig
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@@ -1,3 +0,0 @@
_PLAT_MT7986=y
_DRAM_DDR4=y
_ENABLE_EMERG_MEM_DUMP=y

2
atf-20250711/configs/mt7987_spim_nand_ddr3_defconfig
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@@ -1,2 +0,0 @@
_PLAT_MT7987=y
_DRAM_DEBUG_LOG=y

4
atf-20250711/configs/mt7987_spim_nand_ddr4_2800_defconfig
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@@ -1,4 +0,0 @@
_PLAT_MT7987=y
_DRAM_DDR4=y
_DDR4_SOCKET_BOARD=y
_DRAM_DEBUG_LOG=y

3
atf-20250711/configs/mt7987_spim_nand_ddr4_3200_defconfig
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@@ -1,3 +0,0 @@
_PLAT_MT7987=y
_DRAM_DDR4=y
_DRAM_DEBUG_LOG=y

3
atf-20250711/configs/mt7988_rfb_spim_nand_defconfig
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@@ -1,3 +0,0 @@
_PLAT_MT7988=y
_DRAM_DDR_COMB=y
_ENABLE_EMERG_MEM_DUMP=y

7
atf-20250711/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
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@@ -86,6 +86,12 @@ struct snand_mem_org {
typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);
enum snand_drv {
SNAND_DRV_NO_CHANGE = 0,
SNAND_DRV_8mA = 8,
SNAND_DRV_12mA = 12,
};
struct snand_flash_info {
const char *model;
struct snand_id id;
@@ -93,6 +99,7 @@ struct snand_flash_info {
const struct snand_io_cap *cap_rd;
const struct snand_io_cap *cap_pl;
snand_select_die_t select_die;
enum snand_drv drv;
};
#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \

65
atf-20250711/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
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@@ -80,65 +80,94 @@ static const struct snand_flash_info snand_flash_ids[] = {
SNAND_INFO("W25N512GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20),
SNAND_MEMORG_512M_2K_64,
&snand_cap_read_from_cache_quad,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("W25N01GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("W25M02GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21),
SNAND_MEMORG_2G_2K_64_2D,
&snand_cap_read_from_cache_quad,
&snand_cap_program_load_x4,
mtk_snand_winbond_select_die),
mtk_snand_winbond_select_die,
SNAND_DRV_12mA),
SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22),
SNAND_MEMORG_2G_2K_128,
&snand_cap_read_from_cache_quad,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F1GQ4UAWxx", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F1GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1),
SNAND_MEMORG_1G_2K_128,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F1GQ4UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F1GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
SNAND_MEMORG_2G_2K_128,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F2GQ5UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32),
SNAND_MEMORG_2G_2K_64,
&snand_cap_read_from_cache_quad_a8d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F2GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2),
SNAND_MEMORG_2G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F4GQ4UBxIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4),
SNAND_MEMORG_4G_4K_256,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F4GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4),
SNAND_MEMORG_4G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52),
SNAND_MEMORG_2G_2K_128,
&snand_cap_read_from_cache_quad_a8d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4),
SNAND_MEMORG_4G_4K_256,
&snand_cap_read_from_cache_quad_q2d,
&snand_cap_program_load_x4),
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("MX35LF1GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12),
SNAND_MEMORG_1G_2K_64,
@@ -423,8 +452,10 @@ static const struct snand_flash_info snand_flash_ids[] = {
SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_x4,
&snand_cap_program_load_x4),
&snand_cap_read_from_cache_x4_only,
&snand_cap_program_load_x4,
NULL,
SNAND_DRV_12mA),
SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
SNAND_MEMORG_1G_2K_128,

30
atf-20250711/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
View File

@@ -1845,6 +1845,33 @@ static int mtk_snand_id_probe(struct mtk_snand *snf,
return -EINVAL;
}
#define MT7622_GPIO_BASE (void *)0x10211000
#define MT7622_GPIO_DRIV(x) (MT7622_GPIO_BASE + 0x900 + 0x10 * x)
void mtk_mt7622_snand_adjust_drive(void *dev, enum snand_drv drv)
{
uint32_t e4, e8;
e4 = readl(MT7622_GPIO_DRIV(6)) & ~(0x3f00);
e8 = readl(MT7622_GPIO_DRIV(7)) & ~(0x3f00);
switch (drv) {
case SNAND_DRV_8mA:
e4 |= 0x3f00;
break;
case SNAND_DRV_12mA:
e8 |= 0x3f00;
break;
default:
return;
}
snand_log_chip(dev, "adjusting SPI-NAND pin drive strength to %umA\n", drv);
writel(e4, MT7622_GPIO_DRIV(6));
writel(e8, MT7622_GPIO_DRIV(7));
}
int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
struct mtk_snand **psnf)
{
@@ -1888,6 +1915,9 @@ int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
if (ret)
return ret;
if (pdata->soc == SNAND_SOC_MT7622 && snand_info->drv)
mtk_mt7622_snand_adjust_drive(dev, snand_info->drv);
rawpage_size = snand_info->memorg.pagesize +
snand_info->memorg.sparesize;