Merge Official Source

2020-09-16 11:50:57 +08:00
parent c8a01a8c21 4a3230683b
commit 2d8b04cc95
110 changed files with 9167 additions and 21722 deletions
--- a/include/toplevel.mk
+++ b/include/toplevel.mk
@@ -91,6 +91,7 @@ prepare-tmpinfo: FORCE
 	[ tmp/.config-feeds.in -nt tmp/.packageauxvars ] || ./scripts/feeds feed_config > tmp/.config-feeds.in
 	./scripts/package-metadata.pl mk tmp/.packageinfo > tmp/.packagedeps || { rm -f tmp/.packagedeps; false; }
 	./scripts/package-metadata.pl pkgaux tmp/.packageinfo > tmp/.packageauxvars || { rm -f tmp/.packageauxvars; false; }
+	./scripts/package-metadata.pl usergroup tmp/.packageinfo > tmp/.packageusergroup || { rm -f tmp/.packageusergroup; false; }
 	touch $(TOPDIR)/tmp/.build

 .config: ./scripts/config/conf $(if $(CONFIG_HAVE_DOT_CONFIG),,prepare-tmpinfo)
--- a/package/boot/uboot-envtools/Makefile
+++ b/package/boot/uboot-envtools/Makefile
@@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk
 PKG_NAME:=uboot-envtools
 PKG_DISTNAME:=u-boot
 PKG_VERSION:=2020.04
-PKG_RELEASE:=3
+PKG_RELEASE:=4

 PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:= \
--- a/package/boot/uboot-envtools/files/mvebu
+++ b/package/boot/uboot-envtools/files/mvebu
@@ -15,7 +15,11 @@ board=$(board_name)

 case "$board" in
 cznic,turris-omnia)
-	ubootenv_add_uci_config "/dev/mtd0" "0xC0000" "0x10000" "0x40000"
+	if grep -q 'U-Boot 2015.10-rc2' /dev/mtd0; then
+		ubootenv_add_uci_config "/dev/mtd0" "0xc0000" "0x10000" "0x40000"
+	else
+		ubootenv_add_uci_config "/dev/mtd0" "0xf0000" "0x10000" "0x10000"
+	fi
 	;;
 glinet,gl-mv1000)
 	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x8000" "0x8000" "1"
--- a/package/kernel/hwmon-gsc/Makefile
+++ b/package/kernel/hwmon-gsc/Makefile
@@ -8,7 +8,7 @@ include $(INCLUDE_DIR)/package.mk

 define KernelPackage/hwmon-gsc
  SUBMENU:=Hardware Monitoring Support
-  DEPENDS:=@TARGET_imx6||TARGET_cns3xxx +kmod-hwmon-core +kmod-i2c-core
+  DEPENDS:=@TARGET_imx6 +kmod-hwmon-core +kmod-i2c-core
  TITLE:=Driver for the Gateworks System Controller
  AUTOLOAD:=$(call AutoLoad,60,gsc)
  FILES:=$(PKG_BUILD_DIR)/gsc.ko
--- a/package/network/services/uhttpd/Makefile
+++ b/package/network/services/uhttpd/Makefile
@@ -12,9 +12,9 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/uhttpd.git
-PKG_SOURCE_DATE:=2020-08-05
-PKG_SOURCE_VERSION:=212f8364d49c1bc27dd8bdc394fc3615ea9b7ba3
-PKG_MIRROR_HASH:=c717924cd075951846cb8ad271f4754db56af53a271ed0afbdc5a2f482e15f97
+PKG_SOURCE_DATE:=2020-09-15
+PKG_SOURCE_VERSION:=11723570af9cb7bd87842e79c85ee99530be9902
+PKG_MIRROR_HASH:=39aa6d700689419db8e8f9bf59a4b9c9539c3ee636e0befebf38476bc883cc18
 PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
 PKG_LICENSE:=ISC

--- a/scripts/ipkg-build
+++ b/scripts/ipkg-build
@@ -68,6 +68,26 @@ pkg_appears_sane() {
 	return $PKG_ERROR
 }

+resolve_file_mode_id() {
+	local var=$1 type=$2 name=$3 id
+
+	case "$name" in
+		root)
+			id=0
+		;;
+		*[!0-9]*)
+			id=$(sed -ne "s#^$type $name \\([0-9]\\+\\)\\b.*\$#\\1#p" "$TOPDIR/tmp/.packageusergroup" 2>/dev/null)
+		;;
+		*)
+			id=$name
+		;;
+	esac
+
+	export "$var=$id"
+
+	[ -n "$id" ]
+}
+
 ###
 # ipkg-build "main"
 ###
@@ -101,7 +121,7 @@ case $# in
 	;;
 *)
 	echo $usage >&2
-	exit 1 
+	exit 1
 	;;
 esac

@@ -141,11 +161,22 @@ for file_mode in $file_modes; do
 	    exit 1
 	    ;;
 	esac
-	path=$(echo "$file_mode" | cut -d ':' -f 1)
-	user_group=$(echo "$file_mode" | cut -d ':' -f 2-3)
-	mode=$(echo "$file_mode" | cut -d ':' -f 4)

-	chown "$user_group" "$pkg_dir/$path"
+	mode=${file_mode##*:}; path=${file_mode%:*}
+	group=${path##*:};     path=${path%:*}
+	user=${path##*:};      path=${path%:*}
+
+	if ! resolve_file_mode_id uid user "$user"; then
+		echo "ERROR: unable to resolve uid of $user" >&2
+		exit 1
+	fi
+
+	if ! resolve_file_mode_id gid group "$group"; then
+		echo "ERROR: unable to resolve gid of $group" >&2
+		exit 1
+	fi
+
+	chown "$uid:$gid" "$pkg_dir/$path"
 	chmod  "$mode" "$pkg_dir/$path"
 done
 $TAR -X $tmp_dir/tarX --format=gnu --sort=name -cpf - --mtime="$TIMESTAMP" . | $GZIP -n - > $tmp_dir/data.tar.gz
--- a/target/linux/cns3xxx/Makefile
+++ b/target/linux/cns3xxx/Makefile
@@ -1,28 +0,0 @@
-#
-# Copyright (C) 2010-2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=cns3xxx
-BOARDNAME:=Cavium Networks Econa CNS3xxx
-FEATURES:=squashfs fpu gpio pcie usb usbgadget
-CPU_TYPE:=mpcore
-CPU_SUBTYPE:=vfp
-KERNEL_PATCHVER:=4.19
-
-define Target/Description
-	Build images for Cavium Networks Econa CNS3xxx based boards,
-	eg. the Gateworks Laguna family
-endef
-
-include $(INCLUDE_DIR)/target.mk
-
-KERNELNAME:=zImage
-
-DEFAULT_PACKAGES += kmod-ath9k kmod-usb2 wpad-basic-wolfssl
-
-$(eval $(call BuildTarget))
--- a/target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu
+++ b/target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu
@@ -1,21 +0,0 @@
-#!/bin/sh /etc/rc.common
-
-START=99
-
-get_irq() {
-	local name="$1"
-	grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,'
-}
-
-set_irq_affinity() {
-	local name="$1"
-	local val="$2"
-	local irq="$(get_irq "$name")"
-	[ -n "$irq" ] || return
-	echo "$val" > "/proc/irq/$irq/smp_affinity"
-}
-
-start() {
-	set_irq_affinity gig_switch 2
-	set_irq_affinity gig_stat 2
-}
--- a/target/linux/cns3xxx/base-files/lib/cns3xxx.sh
+++ b/target/linux/cns3xxx/base-files/lib/cns3xxx.sh
@@ -1,26 +0,0 @@
-CNS3XXX_BOARD_NAME=
-CNS3XXX_MODEL=
-
-cns3xxx_board_detect() {
-	local machine
-	local name
-
-	machine=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /Hardware/ {print $2}' /proc/cpuinfo)
-
-	case "$machine" in
-		"Gateworks Corporation Laguna"*)
-			name="laguna"
-			;;
-		*)
-			name="generic";
-			;;
-	esac
-
-	[ -z "$CNS3XXX_BOARD_NAME" ] && CNS3XXX_BOARD_NAME="$name"
-	[ -z "$CNS3XXX_MODEL" ] && CNS3XXX_MODEL="$machine"
-
-	[ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
-
-	echo "$CNS3XXX_BOARD_NAME" > /tmp/sysinfo/board_name
-	echo "$CNS3XXX_MODEL" > /tmp/sysinfo/model
-}
--- a/target/linux/cns3xxx/base-files/lib/preinit/01_sysinfo
+++ b/target/linux/cns3xxx/base-files/lib/preinit/01_sysinfo
@@ -1,7 +0,0 @@
-do_sysinfo_cns3xxx() {
-	. /lib/cns3xxx.sh
-
-	cns3xxx_board_detect
-}
-
-boot_hook_add preinit_main do_sysinfo_cns3xxx
--- a/target/linux/cns3xxx/base-files/lib/upgrade/platform.sh
+++ b/target/linux/cns3xxx/base-files/lib/upgrade/platform.sh
@@ -1,19 +0,0 @@
-PART_NAME=firmware
-
-CI_BLKSZ=65536
-
-platform_check_image() {
-	local magic="$(get_magic_long "$1")"
-
-	[ "$#" -gt 1 ] && return 1
-
-	[ "$magic" != "27051956" ] && {
-		echo "Invalid image type."
-		return 1
-	}
-	return 0
-}
-
-platform_do_upgrade() {
-	default_do_upgrade "$1"
-}
--- a/target/linux/cns3xxx/config-4.19
+++ b/target/linux/cns3xxx/config-4.19
@@ -1,368 +0,0 @@
-# CONFIG_AIO is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_CNS3XXX=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_ARCH_HAS_PHYS_TO_DMA=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BCM_NET_PHYLIB=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_CNS3XXX_ETH=y
-CONFIG_COMMON_CLK=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_CRASH_DUMP=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_USER is not set
-CONFIG_DMA_CACHE_FIQ_BROADCAST=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_ELF_CORE=y
-CONFIG_FIQ=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HWMON=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_CNS3XXX=y
-# CONFIG_INITRAMFS_FORCE is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IPV6=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-# CONFIG_IPV6_PIMSM_V2 is not set
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_UNCOMPRESSED=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_TRIGGER_NETDEV is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-# CONFIG_MACH_CNS3420VB is not set
-CONFIG_MACH_GW2388=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_CNS3XXX=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MPCORE_WATCHDOG=y
-CONFIG_MTD_M25P80=y
-# CONFIG_MTD_OF_PARTS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CONNTRACK_RTCACHE=m
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_DEFRAG_IPV6=m
-CONFIG_NF_LOG_COMMON=m
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_IPV4=m
-CONFIG_NF_NAT_NEEDED=y
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NR_CPUS=2
-CONFIG_NTP_PPS=y
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-# CONFIG_PCI_V3_SEMI is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_PPP=m
-CONFIG_PPPOE=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPS=y
-CONFIG_PPS_CLIENT_GPIO=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_VMCORE=y
-CONFIG_RAID_ATTRS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REFCOUNT_FULL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SPI=y
-CONFIG_RELAY=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1672=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SCSI=y
-CONFIG_SENSORS_AD7418=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SG_POOL=y
-CONFIG_SLHC=m
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_CNS3XXX=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
-# CONFIG_STAGING is not set
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_CNS3XXX_EHCI=y
-CONFIG_USB_CNS3XXX_OHCI=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_DWC2_HOST=y
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-# CONFIG_USB_ROLE_SWITCH is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
@@ -1,87 +0,0 @@
-/*
- *  Copyright (C) 2012 Gateworks Corporation
- *      Chris Lang <clang@gateworks.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/asm-offsets.h>
-
-#define D_CACHE_LINE_SIZE 32
-
-	.text
-
-/*
- * R8  - DMA Start Address
- * R9  - DMA Length
- * R10 - DMA Direction
- * R11 - DMA type
- * R12 - fiq_buffer Address
-*/
-
-	.global	cns3xxx_fiq_end
-ENTRY(cns3xxx_fiq_start)
-	str	r8, [r13]
-
-	ldmia	r12, {r8, r9, r10}
-	and	r11, r10, #0x3000000
-	and	r10, r10, #0xff
-
-	teq	r11, #0x1000000
-	beq	cns3xxx_dma_map_area
-	teq	r11, #0x2000000
-	beq	cns3xxx_dma_unmap_area
-	/* fall through */
-cns3xxx_dma_flush_range:
-	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
-1:
-	mcr	p15, 0, r8, c7, c14, 1		@ clean & invalidate D line
-	add	r8, r8, #D_CACHE_LINE_SIZE
-	cmp	r8, r9
-	blo	1b
-	/* fall through */
-cns3xxx_fiq_exit:
-	mov	r8, #0
-	str	r8, [r12, #8]
-	mcr	p15, 0, r8, c7, c10, 4		@ drain write buffer
-	subs	pc, lr, #4
-
-cns3xxx_dma_map_area:
-	add	r9, r9, r8
-	teq	r10, #DMA_FROM_DEVICE
-	beq	cns3xxx_dma_inv_range
-	teq	r10, #DMA_TO_DEVICE
-	bne	cns3xxx_dma_flush_range
-	/* fall through */
-cns3xxx_dma_clean_range:
-	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
-1:
-	mcr	p15, 0, r8, c7, c10, 1		@ clean D line
-	add	r8, r8, #D_CACHE_LINE_SIZE
-	cmp	r8, r9
-	blo	1b
-	b	cns3xxx_fiq_exit
-
-cns3xxx_dma_unmap_area:
-	add	r9, r9, r8
-	teq	r10, #DMA_TO_DEVICE
-	beq	cns3xxx_fiq_exit
-	/* fall through */
-cns3xxx_dma_inv_range:
-	tst	r8, #D_CACHE_LINE_SIZE - 1
-	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
-	mcrne	p15, 0, r8, c7, c10, 1		@ clean D line
-	tst	r9, #D_CACHE_LINE_SIZE - 1
-	bic	r9, r9, #D_CACHE_LINE_SIZE - 1
-	mcrne	p15, 0, r9, c7, c14, 1		@ clean & invalidate D line
-1:
-	mcr	p15, 0, r8, c7, c6, 1		@ invalidate D line
-	add	r8, r8, #D_CACHE_LINE_SIZE
-	cmp	r8, r9
-	blo	1b
-	b	cns3xxx_fiq_exit
-
-cns3xxx_fiq_end:
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
@@ -1,292 +0,0 @@
-/*
- * Copyright 2012 Gateworks Corporation
- *     Chris Lang <clang@gateworks.com>
- *     Tim Harvey <tharvey@gateworks.com>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-
-#include <asm/mach/irq.h>
-
-/*
- * Registers
- */
-#define GPIO_INPUT                          0x04
-#define GPIO_DIR                            0x08
-#define GPIO_SET                            0x10
-#define GPIO_CLEAR                          0x14
-#define GPIO_INTERRUPT_ENABLE               0x20
-#define GPIO_INTERRUPT_RAW_STATUS           0x24
-#define GPIO_INTERRUPT_MASKED_STATUS        0x28
-#define GPIO_INTERRUPT_MASK                 0x2C
-#define GPIO_INTERRUPT_CLEAR                0x30
-#define GPIO_INTERRUPT_TRIGGER_METHOD       0x34
-#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES   0x38
-#define GPIO_INTERRUPT_TRIGGER_TYPE         0x3C
-
-#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE  0
-#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
-#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE  0
-#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH    1
-#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING  0
-#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
-#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH    0
-#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW     1
-
-struct cns3xxx_gpio_chip {
-	struct gpio_chip    chip;
-	struct irq_domain   *domain;
-	spinlock_t          lock;
-	void __iomem        *base;
-};
-
-static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
-static int cns3xxx_gpio_chip_count;
-
-static inline void
-__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
-{
-	u32 reg;
-
-	reg = __raw_readl(cchip->base + GPIO_DIR);
-	if (input)
-		reg &= ~(1 << pin);
-	else
-		reg |= (1 << pin);
-	__raw_writel(reg, cchip->base + GPIO_DIR);
-}
-
-/*
- * GENERIC_GPIO primatives
- */
-static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-	unsigned long flags;
-
-	spin_lock_irqsave(&cchip->lock, flags);
-	__set_direction(cchip, pin, 1);
-	spin_unlock_irqrestore(&cchip->lock, flags);
-
-	return 0;
-}
-
-static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-	int val;
-
-	val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
-
-	return val;
-}
-
-static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-	unsigned long flags;
-
-	spin_lock_irqsave(&cchip->lock, flags);
-	if (level)
-		__raw_writel(1 << pin, cchip->base + GPIO_SET);
-	else
-		__raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
-	__set_direction(cchip, pin, 0);
-	spin_unlock_irqrestore(&cchip->lock, flags);
-
-	return 0;
-}
-
-static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
-	int level)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-
-	if (level)
-		__raw_writel(1 << pin, cchip->base + GPIO_SET);
-	else
-		__raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
-}
-
-static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-
-	return irq_find_mapping(cchip->domain, pin);
-}
-
-
-/*
- * IRQ support
- */
-
-/* one interrupt per GPIO controller (GPIOA/GPIOB)
- * this is called in task context, with IRQs enabled
- */
-static void cns3xxx_gpio_irq_handler(struct irq_desc *desc)
-{
-	struct cns3xxx_gpio_chip *cchip = irq_desc_get_handler_data(desc);
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-	u16 i;
-	u32 reg;
-
-	chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
-
-	/* see which pin(s) triggered the interrupt */
-	reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
-	for (i = 0; i < 32; i++) {
-		if (reg & (1 << i)) {
-			/* let the generic IRQ layer handle an interrupt */
-			generic_handle_irq(irq_find_mapping(cchip->domain, i));
-		}
-	}
-
-	chained_irq_exit(chip, desc); /* unmask the base interrupt */
-}
-
-static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
-{
-	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	struct cns3xxx_gpio_chip *cchip = gc->private;
-	u32 gpio = d->hwirq;
-	unsigned long flags;
-	u32 method, edges, type;
-
-	spin_lock_irqsave(&cchip->lock, flags);
-	method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
-	edges  = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
-	type   = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
-	method &= ~(1 << gpio);
-	edges  &= ~(1 << gpio);
-	type   &= ~(1 << gpio);
-
-	switch(irqtype) {
-	case IRQ_TYPE_EDGE_RISING:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-		edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
-		type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-		edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
-		type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
-		break;
-	case IRQ_TYPE_EDGE_BOTH:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-		edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
-		type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
-		type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
-		break;
-	default:
-		printk(KERN_WARNING "No irq type\n");
-		spin_unlock_irqrestore(&cchip->lock, flags);
-		return -EINVAL;
-	}
-
-	__raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
-	__raw_writel(edges,  cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
-	__raw_writel(type,   cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
-	spin_unlock_irqrestore(&cchip->lock, flags);
-
-	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-		irq_set_handler_locked(d, handle_level_irq);
-	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-		irq_set_handler_locked(d, handle_edge_irq);
-
-	return 0;
-}
-
-void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
-	u32 base, int irq, int secondary_irq_base)
-{
-	struct cns3xxx_gpio_chip *cchip;
-	struct irq_chip_generic *gc;
-	struct irq_chip_type *ct;
-	char gc_label[16];
-	int irq_base;
-
-	if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
-		return;
-
-	snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
-		cns3xxx_gpio_chip_count);
-
-	cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
-	cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
-	cchip->chip.direction_input = cns3xxx_gpio_direction_input;
-	cchip->chip.get = cns3xxx_gpio_get;
-	cchip->chip.direction_output = cns3xxx_gpio_direction_output;
-	cchip->chip.set = cns3xxx_gpio_set;
-	cchip->chip.to_irq = cns3xxx_gpio_to_irq;
-	cchip->chip.base = gpio_base;
-	cchip->chip.ngpio = ngpio;
-	cchip->chip.can_sleep = 0;
-	spin_lock_init(&cchip->lock);
-	cchip->base = (void __iomem *)base;
-
-	BUG_ON(gpiochip_add(&cchip->chip) < 0);
-	cns3xxx_gpio_chip_count++;
-
-	/* clear GPIO interrupts */
-	__raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
-
-	irq_base = irq_alloc_descs(-1, secondary_irq_base, ngpio,
-		numa_node_id());
-	if (irq_base < 0)
-		goto out_irqdesc_free;
-
-	cchip->domain = irq_domain_add_legacy(NULL, ngpio, irq_base, 0,
-		&irq_domain_simple_ops, NULL);
-	if (!cchip->domain)
-		goto out_irqdesc_free;
-
-	/*
-	 * IRQ chip init
-	 */
-	gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, irq_base,
-		cchip->base, handle_edge_irq);
-
-	gc->private = cchip;
-
-	ct = gc->chip_types;
-	ct->type = IRQ_TYPE_EDGE_FALLING;
-	ct->regs.ack = GPIO_INTERRUPT_CLEAR;
-	ct->chip.irq_ack = irq_gc_ack_set_bit;
-	ct->regs.mask = GPIO_INTERRUPT_ENABLE;
-	ct->chip.irq_enable = irq_gc_mask_set_bit;
-	ct->chip.irq_disable = irq_gc_mask_clr_bit;
-	ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
-	ct->handler = handle_edge_irq;
-
-	irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
-		IRQ_NOREQUEST, 0);
-	irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
-	irq_set_handler_data(irq, cchip);
-
-	return;
-
-out_irqdesc_free:
-	irq_free_descs(irq_base, ngpio);
-}
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S
@@ -1,41 +0,0 @@
-/*
- *  linux/arch/arm/mach-cns3xxx/headsmp.S
- *
- *  Cloned from linux/arch/arm/plat-versatile/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-/*
- * CNS3XXX specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(cns3xxx_secondary_startup)
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
-pen:	ldr	r7, [r6]
-	cmp	r7, r0
-	bne	pen
-
-	/*
-	 * we've been released from the holding pen: secondary_stack
-	 * should now contain the SVC stack for this core
-	 */
-	b	secondary_startup
-ENDPROC(cns3xxx_secondary_startup)
-
-	.align 2
-1:	.long	.
-	.long	pen_release
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c
@@ -1,130 +0,0 @@
-/* linux arch/arm/mach-cns3xxx/hotplug.c
- *
- *  Cloned from linux/arch/arm/mach-realview/hotplug.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-
-#include <asm/cacheflush.h>
-
-extern volatile int pen_release;
-
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
-
-	flush_cache_all();
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, %3\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-	"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-	/*
-	 * there is no power-control hardware on this platform, so all
-	 * we can do is put the core into WFI; this is safe as the calling
-	 * code will have already disabled interrupts
-	 */
-	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm(".word	0xe320f003\n"
-		    :
-		    :
-		    : "memory", "cc");
-
-		if (pen_release == cpu) {
-			/*
-			 * OK, proper wakeup, we're done
-			 */
-			break;
-		}
-
-		/*
-		 * Getting here, means that we have come out of WFI without
-		 * having been woken up - this shouldn't happen
-		 *
-		 * Just note it happening - when we're woken, we can report
-		 * its occurrence.
-		 */
-		(*spurious)++;
-	}
-}
-
-int platform_cpu_kill(unsigned int cpu)
-{
-	return 1;
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void platform_cpu_die(unsigned int cpu)
-{
-	int spurious = 0;
-
-	/*
-	 * we're ready for shutdown now, so do it
-	 */
-	cpu_enter_lowpower();
-	platform_do_lowpower(cpu, &spurious);
-
-	/*
-	 * bring this CPU back into the world of cache
-	 * coherency, and then restore interrupts
-	 */
-	cpu_leave_lowpower();
-
-	if (spurious)
-		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
-}
-
-int platform_cpu_disable(unsigned int cpu)
-{
-	/*
-	 * we don't allow CPU 0 to be shutdown (it is still too special
-	 * e.g. clock tick interrupts)
-	 */
-	return cpu == 0 ? -EPERM : 0;
-}
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-cns3xxx/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- */
-#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
-#define __ASM_ARCH_CNS3XXX_GPIO_H
-
-#include <linux/kernel.h>
-
-extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
-	u32 base, int irq, int secondary_irq_base);
-
-#endif
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h
@@ -1,8 +0,0 @@
-#ifndef __MACH_SMP_H
-#define __MACH_SMP_H
-
-extern void smp_dma_map_area(const void *, size_t, int);
-extern void smp_dma_unmap_area(const void *, size_t, int);
-extern void smp_dma_flush_range(const void *, const void *);
-
-#endif
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
@@ -1,327 +0,0 @@
-/*
- *  linux/arch/arm/mach-cns3xxx/platsmp.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  Copyright 2012 Gateworks Corporation
- *		   Chris Lang <clang@gateworks.com>
- *         Tim Harvey <tharvey@gateworks.com>
- *
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-
-#include <asm/cacheflush.h>
-#include <asm/smp_scu.h>
-#include <asm/unified.h>
-#include <asm/fiq.h>
-#include <mach/smp.h>
-#include "cns3xxx.h"
-
-static struct fiq_handler fh = {
-	.name = "cns3xxx-fiq"
-};
-
-struct fiq_req {
-	union {
-		struct {
-			const void *addr;
-			size_t size;
-		} map;
-		struct {
-			const void *addr;
-			size_t size;
-		} unmap;
-		struct {
-			const void *start;
-			const void *end;
-		} flush;
-	};
-	volatile uint flags;
-	void __iomem *reg;
-} ____cacheline_aligned;
-
-extern unsigned int fiq_number[2];
-
-DEFINE_PER_CPU(struct fiq_req, fiq_data);
-
-#define FIQ_ENABLED         0x80000000
-#define FIQ_GENERATE        0x00010000
-#define CNS3XXX_MAP_AREA    0x01000000
-#define CNS3XXX_UNMAP_AREA  0x02000000
-#define CNS3XXX_FLUSH_RANGE 0x03000000
-
-extern void cns3xxx_secondary_startup(void);
-extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
-
-#define SCU_CPU_STATUS 0x08
-static void __iomem *scu_base;
-
-static inline void cns3xxx_set_fiq_regs(unsigned int cpu)
-{
-	struct pt_regs FIQ_regs;
-	struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
-
-	FIQ_regs.ARM_r8 = 0;
-	FIQ_regs.ARM_ip = (unsigned int)fiq_req;
-	FIQ_regs.ARM_sp = (int) MISC_FIQ_CPU(!cpu);
-	fiq_req->reg = MISC_FIQ_CPU(!cpu);
-
-	set_fiq_regs(&FIQ_regs);
-}
-
-static void __init cns3xxx_init_fiq(void)
-{
-	void *fiqhandler_start;
-	unsigned int fiqhandler_length;
-	int ret;
-
-	fiqhandler_start = &cns3xxx_fiq_start;
-	fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
-
-	ret = claim_fiq(&fh);
-	if (ret)
-		return;
-
-	set_fiq_handler(fiqhandler_start, fiqhandler_length);
-}
-
-
-/*
- * Write pen_release in a way that is guaranteed to be visible to all
- * observers, irrespective of whether they're taking part in coherency
- * or not.  This is necessary for the hotplug code to work reliably.
- */
-static void write_pen_release(int val)
-{
-	pen_release = val;
-	smp_wmb();
-	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-}
-
-static DEFINE_SPINLOCK(boot_lock);
-
-static void cns3xxx_secondary_init(unsigned int cpu)
-{
-	/*
-	 * Setup Secondary Core FIQ regs
-	 */
-	cns3xxx_set_fiq_regs(1);
-
-	/*
-	 * let the primary processor know we're out of the
-	 * pen, then head off into the C entry point
-	 */
-	write_pen_release(-1);
-
-	/*
-	 * Synchronise with the boot thread.
-	 */
-	spin_lock(&boot_lock);
-	spin_unlock(&boot_lock);
-}
-
-static int cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-	unsigned long timeout;
-
-	/*
-	 * Set synchronisation state between this boot processor
-	 * and the secondary one
-	 */
-	spin_lock(&boot_lock);
-
-	/*
-	 * The secondary processor is waiting to be released from
-	 * the holding pen - release it, then wait for it to flag
-	 * that it has been released by resetting pen_release.
-	 *
-	 * Note that "pen_release" is the hardware CPU ID, whereas
-	 * "cpu" is Linux's internal ID.
-	 */
-	write_pen_release(cpu);
-
-	/*
-	 * Send the secondary CPU a soft interrupt, thereby causing
-	 * the boot monitor to read the system wide flags register,
-	 * and branch to the address found there.
-	 */
-	arch_send_wakeup_ipi_mask(cpumask_of(cpu));;
-
-	timeout = jiffies + (1 * HZ);
-	while (time_before(jiffies, timeout)) {
-		smp_rmb();
-		if (pen_release == -1)
-			break;
-
-		udelay(10);
-	}
-
-	/*
-	 * now the secondary core is starting up let it run its
-	 * calibrations, then wait for it to finish
-	 */
-	spin_unlock(&boot_lock);
-
-	return pen_release != -1 ? -ENOSYS : 0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-static void __init cns3xxx_smp_init_cpus(void)
-{
-	unsigned int i, ncores;
-	unsigned int status;
-
-	scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT;
-
-	/* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
-	 * used in scu_get_core_count
-	 */
-	status = __raw_readl(scu_base + SCU_CPU_STATUS);
-	for (i = 0; i < NR_CPUS+1; i++) {
-		if (((status >> (i*2)) & 0x3) == 0)
-			set_cpu_possible(i, true);
-		else
-			break;
-	}
-	ncores = i;
-}
-
-static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
-{
-	/*
-	 * enable SCU
-	 */
-	scu_enable(scu_base);
-
-	/*
-	 * Write the address of secondary startup into the
-	 * system-wide flags register. The boot monitor waits
-	 * until it receives a soft interrupt, and then the
-	 * secondary CPU branches to this address.
-	 */
-	__raw_writel(virt_to_phys(cns3xxx_secondary_startup),
-			(void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
-
-	/*
-	 * Setup FIQ's for main cpu
-	 */
-	cns3xxx_init_fiq();
-	cns3xxx_set_fiq_regs(0);
-}
-
-extern void v6_dma_map_area(const void *, size_t, int);
-extern void v6_dma_unmap_area(const void *, size_t, int);
-extern void v6_dma_flush_range(const void *, const void *);
-extern void v6_flush_kern_dcache_area(void *, size_t);
-
-void fiq_dma_map_area(const void *addr, size_t size, int dir)
-{
-	unsigned long flags;
-	struct fiq_req *req;
-
-	raw_local_irq_save(flags);
-	/* currently, not possible to take cpu0 down, so only check cpu1 */
-	if (!cpu_online(1)) {
-		raw_local_irq_restore(flags);
-		v6_dma_map_area(addr, size, dir);
-		return;
-	}
-
-	req = this_cpu_ptr(&fiq_data);
-	req->map.addr = addr;
-	req->map.size = size;
-	req->flags = dir | CNS3XXX_MAP_AREA;
-	smp_mb();
-
-	writel_relaxed(FIQ_GENERATE, req->reg);
-
-	v6_dma_map_area(addr, size, dir);
-	while (req->flags)
-		barrier();
-
-	raw_local_irq_restore(flags);
-}
-
-void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
-{
-	unsigned long flags;
-	struct fiq_req *req;
-
-	raw_local_irq_save(flags);
-	/* currently, not possible to take cpu0 down, so only check cpu1 */
-	if (!cpu_online(1)) {
-		raw_local_irq_restore(flags);
-		v6_dma_unmap_area(addr, size, dir);
-		return;
-	}
-
-	req = this_cpu_ptr(&fiq_data);
-	req->unmap.addr = addr;
-	req->unmap.size = size;
-	req->flags = dir | CNS3XXX_UNMAP_AREA;
-	smp_mb();
-
-	writel_relaxed(FIQ_GENERATE, req->reg);
-
-	v6_dma_unmap_area(addr, size, dir);
-	while (req->flags)
-		barrier();
-
-	raw_local_irq_restore(flags);
-}
-
-void fiq_dma_flush_range(const void *start, const void *end)
-{
-	unsigned long flags;
-	struct fiq_req *req;
-
-	raw_local_irq_save(flags);
-	/* currently, not possible to take cpu0 down, so only check cpu1 */
-	if (!cpu_online(1)) {
-		raw_local_irq_restore(flags);
-		v6_dma_flush_range(start, end);
-		return;
-	}
-
-	req = this_cpu_ptr(&fiq_data);
-
-	req->flush.start = start;
-	req->flush.end = end;
-	req->flags = CNS3XXX_FLUSH_RANGE;
-	smp_mb();
-
-	writel_relaxed(FIQ_GENERATE, req->reg);
-
-	v6_dma_flush_range(start, end);
-
-	while (req->flags)
-		barrier();
-
-	raw_local_irq_restore(flags);
-}
-
-void fiq_flush_kern_dcache_area(void *addr, size_t size)
-{
-	fiq_dma_flush_range(addr, addr + size);
-}
-
-struct smp_operations cns3xxx_smp_ops __initdata = {
-	.smp_init_cpus      = cns3xxx_smp_init_cpus,
-	.smp_prepare_cpus   = cns3xxx_smp_prepare_cpus,
-	.smp_secondary_init = cns3xxx_secondary_init,
-	.smp_boot_secondary = cns3xxx_boot_secondary,
-};
--- a/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c
+++ b/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c
@@ -1,374 +0,0 @@
-/*
- * Cavium CNS3xxx I2C Host Controller
- *
- * Copyright 2010 Cavium Network
- * Copyright 2012 Gateworks Corporation
- *		  Chris Lang <clang@gateworks.com>
- *		  Tim Harvey <tharvey@gateworks.com>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <asm/io.h>
-#include <linux/wait.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/slab.h>
-#include <linux/clk.h>
-
-/*
- * We need the memory map
- */
-
-#define I2C_MEM_MAP_ADDR(x)         (i2c->base + x)
-#define I2C_MEM_MAP_VALUE(x)        (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x)))
-
-#define I2C_CONTROLLER_REG                    I2C_MEM_MAP_VALUE(0x00)
-#define I2C_TIME_OUT_REG                      I2C_MEM_MAP_VALUE(0x04)
-#define I2C_SLAVE_ADDRESS_REG                 I2C_MEM_MAP_VALUE(0x08)
-#define I2C_WRITE_DATA_REG                    I2C_MEM_MAP_VALUE(0x0C)
-#define I2C_READ_DATA_REG                     I2C_MEM_MAP_VALUE(0x10)
-#define I2C_INTERRUPT_STATUS_REG              I2C_MEM_MAP_VALUE(0x14)
-#define I2C_INTERRUPT_ENABLE_REG              I2C_MEM_MAP_VALUE(0x18)
-#define I2C_TWI_OUT_DLY_REG			         			I2C_MEM_MAP_VALUE(0x1C)
-
-#define I2C_BUS_ERROR_FLAG     (0x1)
-#define I2C_ACTION_DONE_FLAG   (0x2)
-
-#define CNS3xxx_I2C_ENABLE()          (I2C_CONTROLLER_REG) |= ((unsigned int)0x1 << 31)
-#define CNS3xxx_I2C_DISABLE()         (I2C_CONTROLLER_REG) &= ~((unsigned int)0x1 << 31)
-#define CNS3xxx_I2C_ENABLE_INTR()     (I2C_INTERRUPT_ENABLE_REG) |= 0x03
-#define CNS3xxx_I2C_DISABLE_INTR()    (I2C_INTERRUPT_ENABLE_REG) &= 0xfc
-
-#define TWI_TIMEOUT         (10*HZ)
-#define I2C_100KHZ          100000
-#define I2C_200KHZ          200000
-#define I2C_300KHZ          300000
-#define I2C_400KHZ          400000
-
-#define CNS3xxx_I2C_CLK     I2C_100KHZ
-
-#define STATE_DONE		1
-#define STATE_ERROR		2
-
-struct cns3xxx_i2c {
-	struct device		*dev;
-	void __iomem		*base;		/* virtual */
-	wait_queue_head_t	wait;
-	struct i2c_adapter	adap;
-	struct i2c_msg		*msg;
-	u8			state;		/* see STATE_ */
-	u8			error;		/* see TWI_STATUS register */
-	int			rd_wr_len;
-	u8			*buf;
-};
-
-static u32 cns3xxx_i2c_func(struct i2c_adapter *adap)
-{
-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-static int
-cns3xxx_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg)
-{
-	struct cns3xxx_i2c *i2c = i2c_get_adapdata(adap);
-	int i, j;
-	u8 buf[1] = { 0 };
-
-	if (msg->len == 0) {
-		/*
-		 *	We are probably doing a probe for a device here,
-		 *	so set the length to one, and data to 0
-		 */
-		msg->len = 1;
-		i2c->buf = buf;
-	} else {
-		i2c->buf = msg->buf;
-	}
-
-	if (msg->flags & I2C_M_TEN) {
-		printk
-			("%s:%d: Presently the driver does not handle extended addressing\n",
-				__FUNCTION__, __LINE__);
-		return -EINVAL;
-	}
-	i2c->msg = msg;
-
-	for (i = 0; i < msg->len; i++) {
-		if (msg->len - i >= 4)
-			i2c->rd_wr_len = 3;
-		else
-			i2c->rd_wr_len = msg->len - i - 1;
-
-		// Set Data Width	and TWI_EN
-		I2C_CONTROLLER_REG = 0x80000000 | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
-
-		// Clear Write Reg
-		I2C_WRITE_DATA_REG = 0;
-
-		// Set the slave address
-		I2C_SLAVE_ADDRESS_REG = (msg->addr << 1);
-
-		// Are we Writing
-		if (!(msg->flags & I2C_M_RD)) {
-			I2C_CONTROLLER_REG |= (1 << 4);
-			if (i != 0) {
-				/*
-				 * We need to set the address in the first byte.
-				 * The base address is going to be in buf[0] and then
-				 * it needs to be incremented by i - 1.
-				 */
-				i2c->buf--;
-				*i2c->buf = buf[0] + i - 1;
-
-				if (i2c->rd_wr_len < 3) {
-					i += i2c->rd_wr_len;
-					i2c->rd_wr_len++;
-					I2C_CONTROLLER_REG = 0x80000000 | (1 << 4) | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
-				} else {
-					i += i2c->rd_wr_len - 1;
-				}
-			} else {
-				i += i2c->rd_wr_len;
-				buf[0] = *i2c->buf;
-			}
-			for (j = 0; j <= i2c->rd_wr_len; j++) {
-				I2C_WRITE_DATA_REG |= ((*i2c->buf++) << (8 * j));
-			}
-		} else {
-			i += i2c->rd_wr_len;
-		}
-
-		// Start the Transfer
-		i2c->state = 0;		// Clear out the State
-		i2c->error = 0;
-		I2C_CONTROLLER_REG |= (1 << 6);
-
-		if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
-				(i2c->state == STATE_DONE), TWI_TIMEOUT)) {
-			if (i2c->state == STATE_ERROR) {
-				dev_dbg(i2c->dev, "controller error: 0x%2x", i2c->error);
-				return -EAGAIN; // try again
-			}
-		} else {
-			dev_err(i2c->dev, "controller timed out "
-				"waiting for start condition to finish\n");
-			return -ETIMEDOUT;
-		}
-	}
-	return 0;
-}
-
-static int
-cns3xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
-{
-	int i;
-	int ret;
-	for (i = 0; i < num; i++)
-	{
-		ret = cns3xxx_i2c_xfer_msg(adap, &msgs[i]);
-		if (ret < 0) {
-			return ret;
-		}
-	}
-	return num;
-}
-
-
-static struct i2c_algorithm cns3xxx_i2c_algo = {
-	.master_xfer = cns3xxx_i2c_xfer,
-	.functionality = cns3xxx_i2c_func,
-};
-
-static struct i2c_adapter cns3xxx_i2c_adapter = {
-	.owner = THIS_MODULE,
-	.algo = &cns3xxx_i2c_algo,
-	.algo_data = NULL,
-	.nr = 0,
-	.name = "CNS3xxx I2C 0",
-	.retries = 5,
-};
-
-static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c)
-{
-	struct clk *clk;
-
-	clk = devm_clk_get(i2c->dev, "cpu");
-	if (WARN_ON(!clk))
-		return;
-
-	/* Disable the I2C */
-	I2C_CONTROLLER_REG = 0;	/* Disabled the I2C */
-
-	/* Check the Reg Dump when testing */
-	I2C_TIME_OUT_REG =
-	    (((((clk_get_rate(clk) / (2 * CNS3xxx_I2C_CLK)) -
-		1) & 0x3FF) << 8) | (1 << 7) | 0x7F);
-	I2C_TWI_OUT_DLY_REG |= 0x3;
-
-	/* Enable The Interrupt */
-	CNS3xxx_I2C_ENABLE_INTR();
-
-	/* Clear Interrupt Status (0x2 | 0x1) */
-	I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG);
-
-	/* Enable the I2C Controller */
-	CNS3xxx_I2C_ENABLE();
-}
-
-static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id)
-{
-	struct cns3xxx_i2c *i2c = dev_id;
-	int i;
-	uint32_t stat = I2C_INTERRUPT_STATUS_REG;
-
-	/* Clear Interrupt */
-	I2C_INTERRUPT_STATUS_REG |= 0x1;
-
-	if (stat & I2C_BUS_ERROR_FLAG) {
-		i2c->state = STATE_ERROR;
-		i2c->error = (I2C_INTERRUPT_STATUS_REG & 0xff00)>>8;
-	} else {
-		if (i2c->msg->flags & I2C_M_RD) {
-			for (i = 0; i <= i2c->rd_wr_len; i++)
-			{
-				*i2c->buf++ = ((I2C_READ_DATA_REG >> (8 * i)) & 0xff);
-			}
-		}
-		i2c->state = STATE_DONE;
-	}
-	wake_up(&i2c->wait);
-	return IRQ_HANDLED;
-}
-
-static int cns3xxx_i2c_probe(struct platform_device *pdev)
-{
-	struct cns3xxx_i2c *i2c;
-	struct resource *res, *res2;
-	int ret;
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		printk("%s: IORESOURCE_MEM not defined \n", __FUNCTION__);
-		return -ENODEV;
-	}
-
-	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!res2) {
-		printk("%s: IORESOURCE_IRQ not defined \n", __FUNCTION__);
-		return -ENODEV;
-	}
-
-	i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
-	if (!i2c)
-		return -ENOMEM;
-
-	if (!request_mem_region(res->start, res->end - res->start + 1,
-				pdev->name)) {
-		dev_err(&pdev->dev, "Memory region busy\n");
-		ret = -EBUSY;
-		goto request_mem_failed;
-	}
-
-	i2c->dev = &pdev->dev;
-	i2c->base = ioremap(res->start, res->end - res->start + 1);
-	if (!i2c->base) {
-		dev_err(&pdev->dev, "Unable to map registers\n");
-		ret = -EIO;
-		goto map_failed;
-	}
-
-	cns3xxx_i2c_adapter_init(i2c);
-
-	init_waitqueue_head(&i2c->wait);
-	ret = request_irq(res2->start, cns3xxx_i2c_isr, 0, pdev->name, i2c);
-	if (ret) {
-		dev_err(&pdev->dev, "Cannot claim IRQ\n");
-		goto request_irq_failed;
-	}
-
-	platform_set_drvdata(pdev, i2c);
-	i2c->adap = cns3xxx_i2c_adapter;
-	i2c_set_adapdata(&i2c->adap, i2c);
-	i2c->adap.dev.parent = &pdev->dev;
-
-	/* add i2c adapter to i2c tree */
-	ret = i2c_add_numbered_adapter(&i2c->adap);
-	if (ret) {
-		dev_err(&pdev->dev, "Failed to add adapter\n");
-		goto add_adapter_failed;
-	}
-
-	return 0;
-
-      add_adapter_failed:
-	free_irq(res2->start, i2c);
-      request_irq_failed:
-	iounmap(i2c->base);
-      map_failed:
-	release_mem_region(res->start, res->end - res->start + 1);
-      request_mem_failed:
-	kfree(i2c);
-
-	return ret;
-}
-
-static int cns3xxx_i2c_remove(struct platform_device *pdev)
-{
-	struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev);
-	struct resource *res;
-
-	/* disable i2c logic */
-	CNS3xxx_I2C_DISABLE_INTR();
-	CNS3xxx_I2C_DISABLE();
-	/* remove adapter & data */
-	i2c_del_adapter(&i2c->adap);
-	platform_set_drvdata(pdev, NULL);
-
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (res)
-		free_irq(res->start, i2c);
-
-	iounmap(i2c->base);
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (res)
-		release_mem_region(res->start, res->end - res->start + 1);
-
-	kfree(i2c);
-
-	return 0;
-}
-
-static struct platform_driver cns3xxx_i2c_driver = {
-	.probe = cns3xxx_i2c_probe,
-	.remove = cns3xxx_i2c_remove,
-	.driver = {
-		.owner = THIS_MODULE,
-		.name = "cns3xxx-i2c",
-	},
-};
-
-static int __init cns3xxx_i2c_init(void)
-{
-	return platform_driver_register(&cns3xxx_i2c_driver);
-}
-
-static void __exit cns3xxx_i2c_exit(void)
-{
-	platform_driver_unregister(&cns3xxx_i2c_driver);
-}
-
-module_init(cns3xxx_i2c_init);
-module_exit(cns3xxx_i2c_exit);
-
-MODULE_AUTHOR("Cavium Networks");
-MODULE_DESCRIPTION("Cavium CNS3XXX I2C Controller");
-MODULE_LICENSE("GPL");
--- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig
+++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig
@@ -1,24 +0,0 @@
-config NET_VENDOR_CAVIUM
-	bool "Cavium devices"
-	default y
-	depends on ARCH_CNS3XXX
-	---help---
-	  If you have a network (Ethernet) chipset belonging to this class,
-	  say Y.
-
-	  Note that the answer to this question does not directly affect
-	  the kernel: saying N will just case the configurator to skip all
-	  the questions regarding AMD chipsets. If you say Y, you will be asked
-	  for your specific chipset/driver in the following questions.
-
-if NET_VENDOR_CAVIUM
-
-config CNS3XXX_ETH
-	tristate "Cavium CNS3xxx Ethernet support"
-	depends on ARCH_CNS3XXX
-	select PHYLIB
-	help
-	  Say Y here if you want to use built-in Ethernet ports
-	  on CNS3XXX processor.
-
-endif
--- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile
+++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile
@@ -1,5 +0,0 @@
-#
-# Makefile for the Cavium ethernet device drivers.
-#
-
-obj-$(CONFIG_CNS3XXX_ETH) += cns3xxx_eth.o
--- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
+++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
--- a/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c
+++ b/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c
@@ -1,448 +0,0 @@
-/*******************************************************************************
- *
- *  CNS3XXX SPI controller driver (master mode only)
- *
- *  Copyright (c) 2008 Cavium Networks
- *  Copyright 2011 Gateworks Corporation
- *		   Chris Lang <clang@gateworks.com>
- *
- *  This file is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License, Version 2, as
- *  published by the Free Software Foundation.
- *
- *  This file is distributed in the hope that it will be useful,
- *  but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- *  NONINFRINGEMENT.  See the GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this file; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
- *  visit http://www.gnu.org/licenses/.
- *
- *  This file may also be available under a different license from Cavium.
- *  Contact Cavium Networks for more information
- *
- ******************************************************************************/
-
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/workqueue.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_bitbang.h>
-#include <linux/mtd/partitions.h>
-#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-
-#include <asm/io.h>
-#include <asm/memory.h>
-#include <asm/dma.h>
-#include <asm/delay.h>
-#include <linux/module.h>
-
-/*
- * define access macros
- */
-#define SPI_MEM_MAP_VALUE(reg_offset)		(*((u32 volatile *)(hw->base + reg_offset)))
-
-#define SPI_CONFIGURATION_REG			SPI_MEM_MAP_VALUE(0x00)
-#define SPI_SERVICE_STATUS_REG			SPI_MEM_MAP_VALUE(0x04)
-#define SPI_BIT_RATE_CONTROL_REG		SPI_MEM_MAP_VALUE(0x08)
-#define SPI_TRANSMIT_CONTROL_REG		SPI_MEM_MAP_VALUE(0x0C)
-#define SPI_TRANSMIT_BUFFER_REG			SPI_MEM_MAP_VALUE(0x10)
-#define SPI_RECEIVE_CONTROL_REG			SPI_MEM_MAP_VALUE(0x14)
-#define SPI_RECEIVE_BUFFER_REG			SPI_MEM_MAP_VALUE(0x18)
-#define SPI_FIFO_TRANSMIT_CONFIG_REG		SPI_MEM_MAP_VALUE(0x1C)
-#define SPI_FIFO_TRANSMIT_CONTROL_REG		SPI_MEM_MAP_VALUE(0x20)
-#define SPI_FIFO_RECEIVE_CONFIG_REG		SPI_MEM_MAP_VALUE(0x24)
-#define SPI_INTERRUPT_STATUS_REG		SPI_MEM_MAP_VALUE(0x28)
-#define SPI_INTERRUPT_ENABLE_REG		SPI_MEM_MAP_VALUE(0x2C)
-
-#define SPI_TRANSMIT_BUFFER_REG_ADDR		(CNS3XXX_SSP_BASE +0x10)
-#define SPI_RECEIVE_BUFFER_REG_ADDR		(CNS3XXX_SSP_BASE +0x18)
-
-/* Structure for SPI controller of CNS3XXX SOCs */
-struct cns3xxx_spi {
-	/* bitbang has to be first */
-	struct spi_bitbang bitbang;
-	struct completion done;
-	wait_queue_head_t wait;
-
-	int len;
-	int count;
-	int last_in_message_list;
-
-	/* data buffers */
-	const unsigned char *tx;
-	unsigned char *rx;
-
-	void __iomem *base;
-	struct spi_master *master;
-	struct platform_device *pdev;
-	struct device *dev;
-};
-
-static inline u8 cns3xxx_spi_bus_idle(struct cns3xxx_spi *hw)
-{
-	return ((SPI_SERVICE_STATUS_REG & 0x1) ? 0 : 1);
-}
-
-static inline u8 cns3xxx_spi_tx_buffer_empty(struct cns3xxx_spi *hw)
-{
-	return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 3)) ? 1 : 0);
-}
-
-static inline u8 cns3xxx_spi_rx_buffer_full(struct cns3xxx_spi *hw)
-{
-	return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 2)) ? 1 : 0);
-}
-
-u8 cns3xxx_spi_tx_rx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof,
-		     u32 tx_data, u32 * rx_data)
-{
-	u8 rx_channel;
-	u8 rx_eof;
-
-	while (!cns3xxx_spi_bus_idle(hw)) ;	// do nothing
-
-	while (!cns3xxx_spi_tx_buffer_empty(hw)) ;	// do nothing
-
-	SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
-	SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
-
-	SPI_TRANSMIT_BUFFER_REG = tx_data;
-
-	while (!cns3xxx_spi_rx_buffer_full(hw)) ;	// do nothing
-
-	rx_channel = SPI_RECEIVE_CONTROL_REG & 0x3;
-	rx_eof = (SPI_RECEIVE_CONTROL_REG & (0x1 << 2)) ? 1 : 0;
-
-	*rx_data = SPI_RECEIVE_BUFFER_REG;
-
-	if ((tx_channel != rx_channel) || (tx_eof != rx_eof)) {
-		return 0;
-	} else {
-		return 1;
-	}
-}
-
-u8 cns3xxx_spi_tx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof, u32 tx_data)
-{
-
-        while (!cns3xxx_spi_bus_idle(hw)) ;       // do nothing
-
-        while (!cns3xxx_spi_tx_buffer_empty(hw)) ;        // do nothing
-
-        SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
-        SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
-
-        SPI_TRANSMIT_BUFFER_REG = tx_data;
-
-        return 1;
-}
-
-static inline struct cns3xxx_spi *to_hw(struct spi_device *sdev)
-{
-	return spi_master_get_devdata(sdev->master);
-}
-
-static int cns3xxx_spi_setup_transfer(struct spi_device *spi,
-				      struct spi_transfer *t)
-{
-	return 0;
-}
-
-static void cns3xxx_spi_chipselect(struct spi_device *spi, int value)
-{
-	struct cns3xxx_spi *hw = to_hw(spi);
-	unsigned int spi_config;
-
-	switch (value) {
-	case BITBANG_CS_INACTIVE:
-		break;
-
-	case BITBANG_CS_ACTIVE:
-		spi_config = SPI_CONFIGURATION_REG;
-
-		if (spi->mode & SPI_CPHA)
-			spi_config |= (0x1 << 13);
-		else
-			spi_config &= ~(0x1 << 13);
-
-		if (spi->mode & SPI_CPOL)
-			spi_config |= (0x1 << 14);
-		else
-			spi_config &= ~(0x1 << 14);
-
-		/* write new configration */
-		SPI_CONFIGURATION_REG = spi_config;
-
-		SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
-		SPI_TRANSMIT_CONTROL_REG |= (spi->chip_select & 0x3);
-
-		break;
-	}
-}
-
-static int cns3xxx_spi_setup(struct spi_device *spi)
-{
-	if (!spi->bits_per_word)
-		spi->bits_per_word = 8;
-
-	return 0;
-}
-
-static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
-{
-	struct cns3xxx_spi *hw = to_hw(spi);
-
-	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", t->tx_buf, t->rx_buf,
-		t->len);
-
-	hw->tx = t->tx_buf;
-	hw->rx = t->rx_buf;
-	hw->len = t->len;
-	hw->count = 0;
-	hw->last_in_message_list = t->last_in_message_list;
-
-	init_completion(&hw->done);
-
-	if (hw->tx) {
-		int i;
-		u32 rx_data;
-		for (i = 0; i < (hw->len - 1); i++) {
-			dev_dbg(&spi->dev,
-				"[SPI_CNS3XXX_DEBUG] hw->tx[%02d]: 0x%02x\n", i,
-				hw->tx[i]);
-			cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i],
-					  &rx_data);
-			if (hw->rx) {
-				hw->rx[i] = rx_data;
-				dev_dbg(&spi->dev,
-					"[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
-					i, hw->rx[i]);
-			}
-		}
-
-		if (t->last_in_message_list) {
-			cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, hw->tx[i],
-					  &rx_data);
-			if (hw->rx) {
-				hw->rx[i] = rx_data;
-				dev_dbg(&spi->dev,
-					"[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
-					i, hw->rx[i]);
-			}
-		} else {
-			cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i],
-					  &rx_data);
-		}
-		goto done;
-	}
-
-	if (hw->rx) {
-		int i;
-		u32 rx_data;
-		for (i = 0; i < (hw->len - 1); i++) {
-			cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data);
-			hw->rx[i] = rx_data;
-			dev_dbg(&spi->dev,
-				"[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", i,
-				hw->rx[i]);
-		}
-
-		if (t->last_in_message_list) {
-			cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, 0xff, &rx_data);
-		} else {
-			cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data);
-		}
-		hw->rx[i] = rx_data;
-		dev_dbg(&spi->dev, "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
-			i, hw->rx[i]);
-	}
-done:
-	return hw->len;
-}
-
-static void __init cns3xxx_spi_initial(struct cns3xxx_spi *hw)
-{
-	SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) |	/* 8bits shift length */
-				 (0x0 << 9) |	/* SPI mode */
-				 (0x0 << 10) |	/* disable FIFO */
-				 (0x1 << 11) |	/* SPI master mode */
-				 (0x0 << 12) |	/* disable SPI loopback mode */
-				 (0x1 << 13) |	/* clock phase */
-				 (0x1 << 14) |	/* clock polarity */
-				 (0x0 << 24) |	/* disable - SPI data swap */
-				 (0x1 << 29) |	/* enable - 2IO Read mode */
-				 (0x0 << 30) |	/* disable - SPI high speed read for system boot up */
-				 (0x0 << 31));	/* disable - SPI */
-
-	/* Set SPI bit rate PCLK/2 */
-	SPI_BIT_RATE_CONTROL_REG = 0x1;
-
-	/* Set SPI Tx channel 0 */
-	SPI_TRANSMIT_CONTROL_REG = 0x0;
-
-	/* Set Tx FIFO Threshold, Tx FIFO has 2 words */
-	SPI_FIFO_TRANSMIT_CONFIG_REG &= ~(0x03 << 4);
-	SPI_FIFO_TRANSMIT_CONFIG_REG |= ((0x0 & 0x03) << 4);
-
-	/* Set Rx FIFO Threshold, Rx FIFO has 2 words */
-	SPI_FIFO_RECEIVE_CONFIG_REG &= ~(0x03 << 4);
-	SPI_FIFO_RECEIVE_CONFIG_REG |= ((0x0 & 0x03) << 4);
-
-	/* Disable all interrupt */
-	SPI_INTERRUPT_ENABLE_REG = 0x0;
-
-	/* Clear spurious interrupt sources */
-	SPI_INTERRUPT_STATUS_REG = (0x0F << 4);
-
-	/* Enable SPI */
-	SPI_CONFIGURATION_REG |= (0x1 << 31);
-
-	return;
-}
-
-static int cns3xxx_spi_probe(struct platform_device *pdev)
-{
-	struct spi_master *master;
-	struct cns3xxx_spi *hw;
-	struct resource *res;
-	int err = 0;
-
-	printk("%s: setup CNS3XXX SPI Controller\n", __FUNCTION__);
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res)
-		return -ENODEV;
-
-	/* Allocate master with space for cns3xxx_spi */
-	master = spi_alloc_master(&pdev->dev, sizeof(struct cns3xxx_spi));
-	if (master == NULL) {
-		dev_err(&pdev->dev, "No memory for spi_master\n");
-		err = -ENOMEM;
-		goto err_nomem;
-	}
-
-	hw = spi_master_get_devdata(master);
-	memset(hw, 0, sizeof(struct cns3xxx_spi));
-
-	hw->master = spi_master_get(master);
-	hw->dev = &pdev->dev;
-
-	hw->base = devm_ioremap_resource(hw->dev, res);
-	if (IS_ERR(hw->base)) {
-		dev_err(hw->dev, "Unable to map registers\n");
-		err = PTR_ERR(hw->base);
-		goto err_register;
-	}
-
-	platform_set_drvdata(pdev, hw);
-	init_completion(&hw->done);
-
-	/* setup the master state. */
-
-	master->num_chipselect = 4;
-	master->bus_num = 1;
-
-	/* setup the state for the bitbang driver */
-
-	hw->bitbang.master = hw->master;
-	hw->bitbang.setup_transfer = cns3xxx_spi_setup_transfer;
-	hw->bitbang.chipselect = cns3xxx_spi_chipselect;
-	hw->bitbang.txrx_bufs = cns3xxx_spi_txrx;
-	hw->bitbang.master->setup = cns3xxx_spi_setup;
-
-	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
-
-	/* SPI controller initializations */
-	cns3xxx_spi_initial(hw);
-
-	/* register SPI controller */
-
-	err = spi_bitbang_start(&hw->bitbang);
-	if (err) {
-		dev_err(&pdev->dev, "Failed to register SPI master\n");
-		goto err_register;
-	}
-
-	return 0;
-
-err_register:
-	spi_master_put(hw->master);;
-
-err_nomem:
-	return err;
-}
-
-static int cns3xxx_spi_remove(struct platform_device *dev)
-{
-	struct cns3xxx_spi *hw = platform_get_drvdata(dev);
-
-	platform_set_drvdata(dev, NULL);
-
-	spi_unregister_master(hw->master);
-
-	spi_master_put(hw->master);
-	return 0;
-}
-
-#ifdef CONFIG_PM
-
-static int cns3xxx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
-{
-	struct cns3xxx_spi *hw = platform_get_drvdata(pdev);
-
-	return 0;
-}
-
-static int cns3xxx_spi_resume(struct platform_device *pdev)
-{
-	struct cns3xxx_spi *hw = platform_get_drvdata(pdev);
-
-	return 0;
-}
-
-#else
-#define cns3xxx_spi_suspend	NULL
-#define cns3xxx_spi_resume	NULL
-#endif
-
-static struct platform_driver cns3xxx_spi_driver = {
-	.probe		= cns3xxx_spi_probe,
-	.remove		= cns3xxx_spi_remove,
-	.suspend	= cns3xxx_spi_suspend,
-	.resume		= cns3xxx_spi_resume,
-	.driver		= {
-		.name = "cns3xxx_spi",
-		.owner = THIS_MODULE,
-	},
-};
-
-static int __init cns3xxx_spi_init(void)
-{
-	return platform_driver_register(&cns3xxx_spi_driver);
-}
-
-static void __exit cns3xxx_spi_exit(void)
-{
-	platform_driver_unregister(&cns3xxx_spi_driver);
-}
-
-module_init(cns3xxx_spi_init);
-module_exit(cns3xxx_spi_exit);
-
-MODULE_AUTHOR("Cavium Networks");
-MODULE_DESCRIPTION("CNS3XXX SPI Controller Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:cns3xxx_spi");
-
-EXPORT_SYMBOL_GPL(cns3xxx_spi_tx_rx);
--- a/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h
+++ b/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-cns3xxx/include/mach/platform.h
- *
- * Copyright 2011 Gateworks Corporation
- *		  Chris Lang <clang@gateworks.com
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_PLATFORM_H
-#define __ASM_ARCH_PLATFORM_H
-
-#ifndef __ASSEMBLY__
-
-/* Information about built-in Ethernet MAC interfaces */
-struct cns3xxx_plat_info {
-	u8 ports; /* Bitmap of enabled Ports */
-	u8 hwaddr[4][6];
-	u32 phy[3];
-};
-
-#endif /* __ASM_ARCH_PLATFORM_H */
-#endif
--- a/target/linux/cns3xxx/image/Makefile
+++ b/target/linux/cns3xxx/image/Makefile
@@ -1,44 +0,0 @@
-#
-# Copyright (C) 2010-2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/Prepare
-	mkimage -A arm -O linux -T kernel -C none -a 0x20008000 -e 0x20008000 -n '$(VERSION_DIST) Linux-$(LINUX_VERSION)' -d $(KDIR)/zImage $(KDIR)/uImage
-endef
-
-LEGACY_NOR_KERNEL_SIZE = 2048k
-LEGACY_SPI_KERNEL_SIZE = 1536k
-
-# Build sysupgrade image
-define BuildFirmware/Legacy
-	dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin \
-		of=$(KDIR)/uImage.pad bs=$(3) count=1
-	dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin \
-		of=$(KDIR)/root.$(1).pad bs=$(3) skip=1
-	sh $(TOPDIR)/scripts/combined-image.sh \
-		$(KDIR)/uImage.pad \
-		$(KDIR)/root.$(1).pad \
-		$(BIN_DIR)/$(IMG_PREFIX)-$(1)-$(2)-legacy-sysupgrade.bin
-endef
-
-define Image/BuildKernel/Initramfs
-	mkimage -A arm -O linux -T kernel -C none -a 0x20008000 -e 0x20008000 -n '$(VERSION_DIST) Linux-$(LINUX_VERSION)' -d $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-initramfs-uImage
-endef
-
-define Image/Build
-	cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin
-	$(call Image/Build/$(1),$(1))
-	$(call BuildFirmware/Legacy,$(1),laguna_spi,$(LEGACY_SPI_KERNEL_SIZE))
-	$(call BuildFirmware/Legacy,$(1),laguna_nor,$(LEGACY_NOR_KERNEL_SIZE))
-endef
-
-define Image/Build/squashfs
-	$(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin)
-endef
-
-$(eval $(call BuildImage))
--- a/target/linux/cns3xxx/patches-4.19/000-cns3xxx_arch_include.patch
+++ b/target/linux/cns3xxx/patches-4.19/000-cns3xxx_arch_include.patch
@@ -1,9 +0,0 @@
--- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -1,4 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
-+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-+
- obj-$(CONFIG_ARCH_CNS3XXX)		+= cns3xxx.o
- cns3xxx-y				+= core.o pm.o
- cns3xxx-$(CONFIG_ATAGS)			+= devices.o
--- a/target/linux/cns3xxx/patches-4.19/001-arm_openwrt_machtypes.patch
+++ b/target/linux/cns3xxx/patches-4.19/001-arm_openwrt_machtypes.patch
@@ -1,10 +0,0 @@
--- a/arch/arm/tools/mach-types
-+++ b/arch/arm/tools/mach-types
-@@ -449,6 +449,7 @@ gplugd			MACH_GPLUGD		GPLUGD			2625
- qsd8x50a_st1_5		MACH_QSD8X50A_ST1_5	QSD8X50A_ST1_5		2627
- mx23evk			MACH_MX23EVK		MX23EVK			2629
- ap4evb			MACH_AP4EVB		AP4EVB			2630
-+gw2388			MACH_GW2388		GW2388			2635
- mityomapl138		MACH_MITYOMAPL138	MITYOMAPL138		2650
- guruplug		MACH_GURUPLUG		GURUPLUG		2659
- spear310		MACH_SPEAR310		SPEAR310		2660
--- a/target/linux/cns3xxx/patches-4.19/010-arm_introduce-dma-fiq-irq-broadcast.patch
+++ b/target/linux/cns3xxx/patches-4.19/010-arm_introduce-dma-fiq-irq-broadcast.patch
@@ -1,80 +0,0 @@
--- a/arch/arm/include/asm/glue-cache.h
-+++ b/arch/arm/include/asm/glue-cache.h
-@@ -156,9 +156,15 @@ static inline void nop_dma_unmap_area(co
- #define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
- #define __cpuc_coherent_kern_range	__glue(_CACHE,_coherent_kern_range)
- #define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
-#define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
- 
-#define dmac_flush_range		__glue(_CACHE,_dma_flush_range)
-+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
-+# define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
-+# define dmac_flush_range		__glue(_CACHE,_dma_flush_range)
-+#else
-+# define __cpuc_flush_dcache_area	__glue(fiq,_flush_kern_dcache_area)
-+# define dmac_flush_range		__glue(fiq,_dma_flush_range)
-+#endif
-+
- #endif
- 
- #endif
--- a/arch/arm/mm/Kconfig
-+++ b/arch/arm/mm/Kconfig
-@@ -916,6 +916,17 @@ config DMA_CACHE_RWFO
- 	  in hardware, other workarounds are needed (e.g. cache
- 	  maintenance broadcasting in software via FIQ).
- 
-+config DMA_CACHE_FIQ_BROADCAST
-+	bool "Enable fiq broadcast DMA cache maintenance"
-+	depends on CPU_V6K && SMP
-+	select FIQ
-+	help
-+	  The Snoop Control Unit on ARM11MPCore does not detect the
-+	  cache maintenance operations and the dma_{map,unmap}_area()
-+	  functions may leave stale cache entries on other CPUs. By
-+	  enabling this option, fiq broadcast in the ARMv6
-+	  DMA cache maintenance functions is performed.
-+
- config OUTER_CACHE
- 	bool
- 
--- a/arch/arm/mm/flush.c
-+++ b/arch/arm/mm/flush.c
-@@ -319,6 +319,7 @@ void __sync_icache_dcache(pte_t pteval)
- void flush_dcache_page(struct page *page)
- {
- 	struct address_space *mapping;
-+	bool skip_broadcast = true;
- 
- 	/*
- 	 * The zero page is never written to, so never has any dirty
-@@ -335,7 +336,10 @@ void flush_dcache_page(struct page *page
- 
- 	mapping = page_mapping_file(page);
- 
-	if (!cache_ops_need_broadcast() &&
-+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
-+        skip_broadcast = !cache_ops_need_broadcast();
-+#endif
-+        if (skip_broadcast &&
- 	    mapping && !page_mapcount(page))
- 		clear_bit(PG_dcache_clean, &page->flags);
- 	else {
--- a/arch/arm/mm/dma.h
-+++ b/arch/arm/mm/dma.h
-@@ -5,8 +5,13 @@
- #include <asm/glue-cache.h>
- 
- #ifndef MULTI_CACHE
-#define dmac_map_area			__glue(_CACHE,_dma_map_area)
-#define dmac_unmap_area 		__glue(_CACHE,_dma_unmap_area)
-+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
-+# define dmac_map_area			__glue(_CACHE,_dma_map_area)
-+# define dmac_unmap_area 		__glue(_CACHE,_dma_unmap_area)
-+#else
-+# define dmac_map_area			__glue(fiq,_dma_map_area)
-+# define dmac_unmap_area			__glue(fiq,_dma_unmap_area)
-+#endif
- 
- /*
-  * These are private to the dma-mapping API.  Do not use directly.
--- a/target/linux/cns3xxx/patches-4.19/020-watchdog_support.patch
+++ b/target/linux/cns3xxx/patches-4.19/020-watchdog_support.patch
@@ -1,184 +0,0 @@
-Add a watchdog driver for ARM MPcore processors.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -375,6 +375,13 @@ config KS8695_WATCHDOG
- 	  Watchdog timer embedded into KS8695 processor. This will reboot your
- 	  system when the timeout is reached.
- 
-+config MPCORE_WATCHDOG
-+	tristate "MPcore watchdog"
-+	depends on HAVE_ARM_TWD
-+	select WATCHDOG_CORE
-+	help
-+	  Watchdog timer embedded into the MPcore system
-+
- config HAVE_S3C2410_WATCHDOG
- 	bool
- 	help
--- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -49,6 +49,7 @@ obj-$(CONFIG_977_WATCHDOG) += wdt977.o
- obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
- obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
- obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
-+obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
- obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
- obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
- obj-$(CONFIG_SAMA5D4_WATCHDOG) += sama5d4_wdt.o
--- /dev/null
-+++ b/drivers/watchdog/mpcore_wdt.c
-@@ -0,0 +1,118 @@
-+/*
-+ * Watchdog driver for ARM MPcore
-+ *
-+ * Copyright (C) 2017 Felix Fietkau <nbd@nbd.name>
-+ */
-+
-+#include <linux/export.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/watchdog.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <asm/smp_twd.h>
-+
-+static void __iomem *wdt_base;
-+static int wdt_timeout = 60;
-+
-+static int mpcore_wdt_keepalive(struct watchdog_device *wdd)
-+{
-+	static int perturb;
-+	u32 count;
-+
-+	count = (twd_timer_get_rate() / 256) * wdt_timeout;
-+
-+	/* Reload register needs a different value on each refresh */
-+	count += perturb;
-+	perturb = !perturb;
-+
-+	iowrite32(count, wdt_base + TWD_WDOG_LOAD);
-+
-+	return 0;
-+}
-+
-+static int mpcore_wdt_start(struct watchdog_device *wdd)
-+{
-+	mpcore_wdt_keepalive(wdd);
-+
-+	/* prescale = 256, mode = 1, enable = 1 */
-+	iowrite32(0x0000FF09, wdt_base + TWD_WDOG_CONTROL);
-+
-+	return 0;
-+}
-+
-+static int mpcore_wdt_stop(struct watchdog_device *wdd)
-+{
-+	iowrite32(0x12345678, wdt_base + TWD_WDOG_DISABLE);
-+	iowrite32(0x87654321, wdt_base + TWD_WDOG_DISABLE);
-+	iowrite32(0x0, wdt_base + TWD_WDOG_CONTROL);
-+
-+	return 0;
-+}
-+
-+static int mpcore_wdt_set_timeout(struct watchdog_device *wdd,
-+				 unsigned int timeout)
-+{
-+	mpcore_wdt_stop(wdd);
-+	wdt_timeout = timeout;
-+	mpcore_wdt_start(wdd);
-+
-+	return 0;
-+}
-+
-+static const struct watchdog_info mpcore_wdt_info = {
-+	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
-+	.identity = "MPcore Watchdog",
-+};
-+
-+static const struct watchdog_ops mpcore_wdt_ops = {
-+	.owner = THIS_MODULE,
-+	.start = mpcore_wdt_start,
-+	.stop  = mpcore_wdt_stop,
-+	.ping  = mpcore_wdt_keepalive,
-+	.set_timeout = mpcore_wdt_set_timeout,
-+};
-+
-+static struct watchdog_device mpcore_wdt = {
-+	.info = &mpcore_wdt_info,
-+	.ops = &mpcore_wdt_ops,
-+	.min_timeout = 1,
-+	.max_timeout = 65535,
-+};
-+
-+static int mpcore_wdt_probe(struct platform_device *pdev)
-+{
-+	struct resource *res;
-+	unsigned long rate = twd_timer_get_rate();
-+
-+	pr_info("MPCore WD init. clockrate: %lu prescaler: %u countrate: %lu timeout: %us\n", rate, 256, rate / 256, wdt_timeout);
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res)
-+		return -ENODEV;
-+
-+	wdt_base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(wdt_base))
-+		return PTR_ERR(wdt_base);
-+
-+	watchdog_register_device(&mpcore_wdt);
-+	return 0;
-+}
-+
-+static int mpcore_wdt_remove(struct platform_device *dev)
-+{
-+	watchdog_unregister_device(&mpcore_wdt);
-+	return 0;
-+}
-+
-+static struct platform_driver mpcore_wdt_driver = {
-+	.probe		= mpcore_wdt_probe,
-+	.remove		= mpcore_wdt_remove,
-+	.driver		= {
-+		.name	= "mpcore_wdt",
-+	},
-+};
-+
-+module_platform_driver(mpcore_wdt_driver);
-+MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
-+MODULE_LICENSE("GPL");
--- a/arch/arm/include/asm/smp_twd.h
-+++ b/arch/arm/include/asm/smp_twd.h
-@@ -34,5 +34,6 @@ struct twd_local_timer name __initdata =
- };
- 
- int twd_local_timer_register(struct twd_local_timer *);
-+unsigned long twd_timer_get_rate(void);
- 
- #endif
--- a/arch/arm/kernel/smp_twd.c
-+++ b/arch/arm/kernel/smp_twd.c
-@@ -15,6 +15,7 @@
- #include <linux/delay.h>
- #include <linux/device.h>
- #include <linux/err.h>
-+#include <linux/export.h>
- #include <linux/smp.h>
- #include <linux/jiffies.h>
- #include <linux/clockchips.h>
-@@ -380,6 +381,14 @@ int __init twd_local_timer_register(stru
- 	return twd_local_timer_common_register(NULL);
- }
- 
-+/* Needed by mpcore_wdt */
-+unsigned long twd_timer_get_rate(void)
-+{
-+	return twd_timer_rate;
-+}
-+EXPORT_SYMBOL_GPL(twd_timer_get_rate);
-+
-+
- #ifdef CONFIG_OF
- static int __init twd_local_timer_of_register(struct device_node *np)
- {
--- a/target/linux/cns3xxx/patches-4.19/025-smp_support.patch
+++ b/target/linux/cns3xxx/patches-4.19/025-smp_support.patch
@@ -1,30 +0,0 @@
--- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -6,3 +6,5 @@ cns3xxx-y				+= core.o pm.o
- cns3xxx-$(CONFIG_ATAGS)			+= devices.o
- cns3xxx-$(CONFIG_PCI)			+= pcie.o
- cns3xxx-$(CONFIG_MACH_CNS3420VB)	+= cns3420vb.o
-+cns3xxx-$(CONFIG_SMP)			+= platsmp.o headsmp.o
-+cns3xxx-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
--- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -3,6 +3,9 @@ menuconfig ARCH_CNS3XXX
- 	bool "Cavium Networks CNS3XXX family"
- 	depends on ARCH_MULTI_V6
- 	select ARM_GIC
-+	select HAVE_ARM_SCU if SMP
-+	select HAVE_ARM_TWD
-+	select HAVE_SMP
- 	help
- 	  Support for Cavium Networks CNS3XXX platform.
- 
--- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -13,6 +13,7 @@
- 
- #include <linux/reboot.h>
- 
-+extern struct smp_operations cns3xxx_smp_ops;
- extern void cns3xxx_timer_init(void);
- 
- #ifdef CONFIG_CACHE_L2X0
--- a/target/linux/cns3xxx/patches-4.19/030-pcie_clock.patch
+++ b/target/linux/cns3xxx/patches-4.19/030-pcie_clock.patch
@@ -1,11 +0,0 @@
--- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -281,8 +281,6 @@ void __init cns3xxx_pcie_init_late(void)
- 			"imprecise external abort");
- 
- 	for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
-		cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
-		cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
- 		cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
- 		cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
- 		private_data = &cns3xxx_pcie[i];
--- a/target/linux/cns3xxx/patches-4.19/040-fiq_support.patch
+++ b/target/linux/cns3xxx/patches-4.19/040-fiq_support.patch
@@ -1,40 +0,0 @@
--- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -6,6 +6,7 @@ menuconfig ARCH_CNS3XXX
- 	select HAVE_ARM_SCU if SMP
- 	select HAVE_ARM_TWD
- 	select HAVE_SMP
-+	select FIQ
- 	help
- 	  Support for Cavium Networks CNS3XXX platform.
- 
--- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -6,5 +6,5 @@ cns3xxx-y				+= core.o pm.o
- cns3xxx-$(CONFIG_ATAGS)			+= devices.o
- cns3xxx-$(CONFIG_PCI)			+= pcie.o
- cns3xxx-$(CONFIG_MACH_CNS3420VB)	+= cns3420vb.o
-cns3xxx-$(CONFIG_SMP)			+= platsmp.o headsmp.o
-+cns3xxx-$(CONFIG_SMP)			+= platsmp.o headsmp.o cns3xxx_fiq.o
- cns3xxx-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
-+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
-@@ -261,6 +261,7 @@
- #define MISC_PCIE_INT_MASK(x)			MISC_MEM_MAP(0x978 + (x) * 0x100)
- #define MISC_PCIE_INT_STATUS(x)			MISC_MEM_MAP(0x97C + (x) * 0x100)
- 
-+#define MISC_FIQ_CPU(x)				MISC_MEM_MAP(0xA58 - (x) * 0x4)
- /*
-  * Power management and clock control
-  */
--- a/arch/arm/mm/Kconfig
-+++ b/arch/arm/mm/Kconfig
-@@ -899,7 +899,7 @@ config VDSO
- 
- config DMA_CACHE_RWFO
- 	bool "Enable read/write for ownership DMA cache maintenance"
-	depends on CPU_V6K && SMP
-+	depends on CPU_V6K && SMP && !ARCH_CNS3XXX
- 	default y
- 	help
- 	  The Snoop Control Unit on ARM11MPCore does not detect the
--- a/target/linux/cns3xxx/patches-4.19/045-twd_base.patch
+++ b/target/linux/cns3xxx/patches-4.19/045-twd_base.patch
@@ -1,43 +0,0 @@
--- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -17,6 +17,7 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ehci_pdriver.h>
- #include <linux/usb/ohci_pdriver.h>
-+#include <asm/smp_twd.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/mach/time.h>
-@@ -26,6 +27,8 @@
- #include "core.h"
- #include "pm.h"
- 
-+#define IRQ_LOCALTIMER 29
-+
- static struct map_desc cns3xxx_io_desc[] __initdata = {
- 	{
- 		.virtual	= CNS3XXX_TC11MP_SCU_BASE_VIRT,
-@@ -198,6 +201,15 @@ static struct irqaction cns3xxx_timer_ir
- 	.handler	= cns3xxx_timer_interrupt,
- };
- 
-+static void __init cns3xxx_init_twd(void)
-+{
-+	static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer,
-+		CNS3XXX_TC11MP_TWD_BASE,
-+		IRQ_LOCALTIMER);
-+
-+	twd_local_timer_register(&cns3xx_twd_local_timer);
-+}
-+
- /*
-  * Set up the clock source and clock events devices
-  */
-@@ -251,6 +263,7 @@ static void __init __cns3xxx_timer_init(
- 	setup_irq(timer_irq, &cns3xxx_timer_irq);
- 
- 	cns3xxx_clockevents_init(timer_irq);
-+	cns3xxx_init_twd();
- }
- 
- void __init cns3xxx_timer_init(void)
--- a/target/linux/cns3xxx/patches-4.19/055-pcie_io.patch
+++ b/target/linux/cns3xxx/patches-4.19/055-pcie_io.patch
@@ -1,19 +0,0 @@
--- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -81,6 +81,16 @@ static struct map_desc cns3xxx_io_desc[]
- 		.pfn		= __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
- 		.length		= SZ_16M,
- 		.type		= MT_DEVICE,
-+	}, {
-+		.virtual	= CNS3XXX_PCIE0_IO_BASE_VIRT,
-+		.pfn		= __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
-+		.length		= SZ_16M,
-+		.type		= MT_DEVICE,
-+	}, {
-+		.virtual	= CNS3XXX_PCIE1_IO_BASE_VIRT,
-+		.pfn		= __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
-+		.length		= SZ_16M,
-+		.type		= MT_DEVICE,
- #endif
- 	},
- };
--- a/target/linux/cns3xxx/patches-4.19/060-pcie_abort.patch
+++ b/target/linux/cns3xxx/patches-4.19/060-pcie_abort.patch
@@ -1,109 +0,0 @@
--- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -86,6 +86,79 @@ static void __iomem *cns3xxx_pci_map_bus
- 	return base + where + (devfn << 12);
- }
- 
-+static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
-+{
-+	struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
-+
-+  /* check PCI-compatible status register after access */
-+	if (cnspci->linked) {
-+		void __iomem *host_base;
-+		u32 sreg, ereg;
-+
-+		host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
-+		sreg = __raw_readw(host_base + 0x6) & 0xF900;
-+		ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
-+
-+		if (sreg | ereg) {
-+			/* SREG:
-+			 *  BIT15 - Detected Parity Error
-+			 *  BIT14 - Signaled System Error
-+			 *  BIT13 - Received Master Abort
-+			 *  BIT12 - Received Target Abort
-+			 *  BIT11 - Signaled Target Abort
-+			 *  BIT08 - Master Data Parity Error
-+			 *
-+			 * EREG:
-+			 *  BIT20 - Unsupported Request
-+			 *  BIT19 - ECRC
-+			 *  BIT18 - Malformed TLP
-+			 *  BIT17 - Receiver Overflow
-+			 *  BIT16 - Unexpected Completion
-+			 *  BIT15 - Completer Abort
-+			 *  BIT14 - Completion Timeout
-+			 *  BIT13 - Flow Control Protocol Error
-+			 *  BIT12 - Poisoned TLP
-+			 *  BIT04 - Data Link Protocol Error
-+			 *
-+			 * TODO: see Documentation/pci-error-recovery.txt
-+			 *    implement error_detected handler
-+			 */
-+/*
-+			printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg);
-+			if (sreg & BIT(15)) printk(" <PERR");
-+			if (sreg & BIT(14)) printk(" >SERR");
-+			if (sreg & BIT(13)) printk(" <MABRT");
-+			if (sreg & BIT(12)) printk(" <TABRT");
-+			if (sreg & BIT(11)) printk(" >TABRT");
-+			if (sreg & BIT( 8)) printk(" MPERR");
-+
-+			if (ereg & BIT(20)) printk(" Unsup");
-+			if (ereg & BIT(19)) printk(" ECRC");
-+			if (ereg & BIT(18)) printk(" MTLP");
-+			if (ereg & BIT(17)) printk(" OFLOW");
-+			if (ereg & BIT(16)) printk(" Unex");
-+			if (ereg & BIT(15)) printk(" ABRT");
-+			if (ereg & BIT(14)) printk(" COMPTO");
-+			if (ereg & BIT(13)) printk(" FLOW");
-+			if (ereg & BIT(12)) printk(" PTLP");
-+			if (ereg & BIT( 4)) printk(" DLINK");
-+			printk("\n");
-+*/
-+			pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
-+				pci_domain_nr(bus), sreg);
-+
-+			/* make sure the status bits are reset */
-+			__raw_writew(sreg, host_base + 6);
-+			__raw_writel(ereg, host_base + 0x104);
-+			return 1;
-+		}
-+	}
-+	else
-+		return 1;
-+
-+  return 0;
-+}
-+
- static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
- 				   int where, int size, u32 *val)
- {
-@@ -95,6 +168,11 @@ static int cns3xxx_pci_read_config(struc
- 
- 	ret = pci_generic_config_read(bus, devfn, where, size, val);
- 
-+	if (check_master_abort(bus, devfn, where)) {
-+		printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+	}
-+
- 	if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
- 	    (where & 0xffc) == PCI_CLASS_REVISION)
- 		/*
-@@ -257,8 +335,14 @@ static void __init cns3xxx_pcie_hw_init(
- static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
- 				      struct pt_regs *regs)
- {
-+#if 0
-+/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE
-+ * ignore imprecise aborts and use PCI-compatible Status register to
-+ * determine errors instead
-+ */
- 	if (fsr & (1 << 10))
- 		regs->ARM_pc += 4;
-+#endif
- 	return 0;
- }
- 
--- a/target/linux/cns3xxx/patches-4.19/065-pcie_skip_inactive.patch
+++ b/target/linux/cns3xxx/patches-4.19/065-pcie_skip_inactive.patch
@@ -1,11 +0,0 @@
--- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -366,6 +366,8 @@ void __init cns3xxx_pcie_init_late(void)
- 
- 	for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
- 		cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
-+		if (!cns3xxx_pcie[i].linked)
-+			continue;
- 		cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
- 		private_data = &cns3xxx_pcie[i];
- 		pci_common_init(&hw_pci);
--- a/target/linux/cns3xxx/patches-4.19/070-i2c_support.patch
+++ b/target/linux/cns3xxx/patches-4.19/070-i2c_support.patch
@@ -1,31 +0,0 @@
--- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -460,6 +460,18 @@ config I2C_CBUS_GPIO
- 	  This driver can also be built as a module.  If so, the module
- 	  will be called i2c-cbus-gpio.
- 
-+config I2C_CNS3XXX
-+	tristate "Cavium CNS3xxx I2C driver"
-+	depends on ARCH_CNS3XXX
-+	help
-+	  Support for Cavium CNS3xxx I2C controller driver.
-+
-+	  This driver can also be built as a module.  If so, the module
-+	  will be called i2c-cns3xxx.
-+
-+	  Please note that this driver might be needed to bring up other
-+	  devices such as Cavium CNS3xxx Ethernet.
-+
- config I2C_CPM
- 	tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
- 	depends on CPM1 || CPM2
--- a/drivers/i2c/busses/Makefile
-+++ b/drivers/i2c/busses/Makefile
-@@ -131,6 +131,7 @@ obj-$(CONFIG_I2C_VIPERBOARD)	+= i2c-vipe
- obj-$(CONFIG_I2C_ACORN)		+= i2c-acorn.o
- obj-$(CONFIG_I2C_BCM_KONA)	+= i2c-bcm-kona.o
- obj-$(CONFIG_I2C_BRCMSTB)	+= i2c-brcmstb.o
-+obj-$(CONFIG_I2C_CNS3XXX)	+= i2c-cns3xxx.o
- obj-$(CONFIG_I2C_CROS_EC_TUNNEL)	+= i2c-cros-ec-tunnel.o
- obj-$(CONFIG_I2C_ELEKTOR)	+= i2c-elektor.o
- obj-$(CONFIG_I2C_MLXCPLD)	+= i2c-mlxcpld.o
--- a/target/linux/cns3xxx/patches-4.19/075-spi_support.patch
+++ b/target/linux/cns3xxx/patches-4.19/075-spi_support.patch
@@ -1,51 +0,0 @@
--- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -181,6 +181,13 @@ config SPI_CLPS711X
- 	  This enables dedicated general purpose SPI/Microwire1-compatible
- 	  master mode interface (SSI1) for CLPS711X-based CPUs.
- 
-+config SPI_CNS3XXX
-+	tristate "CNS3XXX SPI controller"
-+	depends on ARCH_CNS3XXX && SPI_MASTER
-+	select SPI_BITBANG
-+	help
-+	  This enables using the CNS3XXX SPI controller in master mode.
-+
- config SPI_COLDFIRE_QSPI
- 	tristate "Freescale Coldfire QSPI controller"
- 	depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
--- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -28,6 +28,7 @@ obj-$(CONFIG_SPI_BITBANG)		+= spi-bitban
- obj-$(CONFIG_SPI_BUTTERFLY)		+= spi-butterfly.o
- obj-$(CONFIG_SPI_CADENCE)		+= spi-cadence.o
- obj-$(CONFIG_SPI_CLPS711X)		+= spi-clps711x.o
-+obj-$(CONFIG_SPI_CNS3XXX)		+= spi-cns3xxx.o
- obj-$(CONFIG_SPI_COLDFIRE_QSPI)		+= spi-coldfire-qspi.o
- obj-$(CONFIG_SPI_DAVINCI)		+= spi-davinci.o
- obj-$(CONFIG_SPI_DLN2)			+= spi-dln2.o
--- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -795,6 +795,10 @@ struct spi_transfer {
- 	u32		speed_hz;
- 
- 	struct list_head transfer_list;
-+
-+#ifdef CONFIG_ARCH_CNS3XXX
-+	unsigned	last_in_message_list;
-+#endif
- };
- 
- /**
--- a/drivers/spi/spi.c
-+++ b/drivers/spi/spi.c
-@@ -1020,6 +1020,9 @@ static int spi_transfer_one_message(stru
- 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
- 		trace_spi_transfer_start(msg, xfer);
- 
-+		xfer->last_in_message_list =
-+			list_is_last(&xfer->transfer_list, &msg->transfers);
-+
- 		spi_statistics_add_transfer_stats(statm, xfer, ctlr);
- 		spi_statistics_add_transfer_stats(stats, xfer, ctlr);
- 
--- a/target/linux/cns3xxx/patches-4.19/080-sata_support.patch
+++ b/target/linux/cns3xxx/patches-4.19/080-sata_support.patch
@@ -1,40 +0,0 @@
--- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -44,11 +44,18 @@ static struct scsi_host_template ahci_pl
- 	AHCI_SHT(DRV_NAME),
- };
- 
-+static const struct ata_port_info cns3xxx_port_info = {
-+	.flags		= AHCI_FLAG_COMMON,
-+	.pio_mask	= ATA_PIO4,
-+	.udma_mask	= ATA_UDMA6,
-+	.port_ops	= &ahci_pmp_retry_srst_ops,
-+};
-+
- static int ahci_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
- 	struct ahci_host_priv *hpriv;
-	const struct ata_port_info *port;
-+	const struct ata_port_info *port = &ahci_port_info;
- 	int rc;
- 
- 	hpriv = ahci_platform_get_resources(pdev,
-@@ -66,9 +73,14 @@ static int ahci_probe(struct platform_de
- 	if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
- 		hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
- 
-	port = acpi_device_get_match_data(dev);
-	if (!port)
-		port = &ahci_port_info;
-+	if (IS_ENABLED(CONFIG_ARCH_CNS3XXX)) {
-+		port = &cns3xxx_port_info;
-+	}
-+	else {
-+		port = acpi_device_get_match_data(dev);
-+		if (!port)
-+			port = &ahci_port_info;
-+	}
- 
- 	rc = ahci_platform_init_host(pdev, hpriv, port,
- 				     &ahci_platform_sht);
--- a/target/linux/cns3xxx/patches-4.19/090-timers.patch
+++ b/target/linux/cns3xxx/patches-4.19/090-timers.patch
@@ -1,105 +0,0 @@
--- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -138,6 +138,7 @@ static int cns3xxx_set_oneshot(struct cl
- 
- 	/* period set, and timer enabled in 'next_event' hook */
- 	ctrl |= (1 << 2) | (1 << 9);
-+	writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
- 	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- 	return 0;
- }
-@@ -148,7 +149,7 @@ static int cns3xxx_set_periodic(struct c
- 	int pclk = cns3xxx_cpu_clock() / 8;
- 	int reload;
- 
-	reload = pclk * 20 / (3 * HZ) * 0x25000;
-+	reload = pclk * 1000000 / HZ;
- 	writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
- 	ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
- 	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-@@ -175,8 +176,8 @@ static struct clock_event_device cns3xxx
- 	.set_state_oneshot	= cns3xxx_set_oneshot,
- 	.tick_resume		= cns3xxx_shutdown,
- 	.set_next_event		= cns3xxx_timer_set_next_event,
-	.rating			= 350,
-	.cpumask		= cpu_all_mask,
-+	.rating			= 300,
-+	.cpumask		= cpu_possible_mask,
- };
- 
- static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
-@@ -220,6 +221,32 @@ static void __init cns3xxx_init_twd(void
- 	twd_local_timer_register(&cns3xx_twd_local_timer);
- }
- 
-+static u64 cns3xxx_get_cycles(struct clocksource *cs)
-+{
-+  u64 val;
-+
-+  val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-+  val &= 0xffff;
-+
-+  return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET));
-+}
-+
-+static struct clocksource clocksource_cns3xxx = {
-+	.name = "freerun",
-+	.rating = 200,
-+	.read = cns3xxx_get_cycles,
-+	.mask = CLOCKSOURCE_MASK(48),
-+	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+static void __init cns3xxx_clocksource_init(void)
-+{
-+	/* Reset the FreeRunning counter */
-+	writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-+
-+	clocksource_register_khz(&clocksource_cns3xxx, 100);
-+}
-+
- /*
-  * Set up the clock source and clock events devices
-  */
-@@ -237,13 +264,12 @@ static void __init __cns3xxx_timer_init(
- 	/* stop free running timer3 */
- 	writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
- 
-	/* timer1 */
-	writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
-	writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
-
- 	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
- 	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
- 
-+	val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
-+	writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
-+
- 	/* mask irq, non-mask timer1 overflow */
- 	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
- 	irq_mask &= ~(1 << 2);
-@@ -255,23 +281,9 @@ static void __init __cns3xxx_timer_init(
- 	val |= (1 << 9);
- 	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- 
-	/* timer2 */
-	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
-	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
-
-	/* mask irq */
-	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
-	irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
-	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
-
-	/* down counter */
-	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-	val |= (1 << 10);
-	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
-	/* Make irqs happen for the system timer */
- 	setup_irq(timer_irq, &cns3xxx_timer_irq);
- 
-+	cns3xxx_clocksource_init();
- 	cns3xxx_clockevents_init(timer_irq);
- 	cns3xxx_init_twd();
- }
--- a/target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch
+++ b/target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch
@@ -1,41 +0,0 @@
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
-+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
-@@ -162,11 +162,13 @@
- #define CNS3XXX_L2C_BASE			0x92000000	/* L2 Cache Control */
- 
- #define CNS3XXX_PCIE0_MEM_BASE			0xA0000000	/* PCIe Port 0 IO/Memory Space */
-+#define CNS3XXX_PCIE0_MEM_BASE_VIRT		0xE0000000
- 
- #define CNS3XXX_PCIE0_HOST_BASE			0xAB000000	/* PCIe Port 0 RC Base */
- #define CNS3XXX_PCIE0_HOST_BASE_VIRT		0xE1000000
- 
- #define CNS3XXX_PCIE0_IO_BASE			0xAC000000	/* PCIe Port 0 */
-+#define CNS3XXX_PCIE0_IO_BASE_VIRT		0xE2000000
- 
- #define CNS3XXX_PCIE0_CFG0_BASE			0xAD000000	/* PCIe Port 0 CFG Type 0 */
- #define CNS3XXX_PCIE0_CFG0_BASE_VIRT		0xE3000000
-@@ -175,13 +177,16 @@
- #define CNS3XXX_PCIE0_CFG1_BASE_VIRT		0xE4000000
- 
- #define CNS3XXX_PCIE0_MSG_BASE			0xAF000000	/* PCIe Port 0 Message Space */
-+#define CNS3XXX_PCIE0_MSG_BASE_VIRT		0xE5000000
- 
- #define CNS3XXX_PCIE1_MEM_BASE			0xB0000000	/* PCIe Port 1 IO/Memory Space */
-+#define CNS3XXX_PCIE1_MEM_BASE_VIRT		0xE8000000
- 
- #define CNS3XXX_PCIE1_HOST_BASE			0xBB000000	/* PCIe Port 1 RC Base */
- #define CNS3XXX_PCIE1_HOST_BASE_VIRT		0xE9000000
- 
- #define CNS3XXX_PCIE1_IO_BASE			0xBC000000	/* PCIe Port 1 */
-+#define CNS3XXX_PCIE1_IO_BASE_VIRT		0xEA000000
- 
- #define CNS3XXX_PCIE1_CFG0_BASE			0xBD000000	/* PCIe Port 1 CFG Type 0 */
- #define CNS3XXX_PCIE1_CFG0_BASE_VIRT		0xEB000000
-@@ -190,6 +195,7 @@
- #define CNS3XXX_PCIE1_CFG1_BASE_VIRT		0xEC000000
- 
- #define CNS3XXX_PCIE1_MSG_BASE			0xBF000000	/* PCIe Port 1 Message Space */
-+#define CNS3XXX_PCIE1_MSG_BASE_VIRT		0xED000000
- 
- /*
-  * Testchip peripheral and fpga gic regions
--- a/target/linux/cns3xxx/patches-4.19/095-gpio_support.patch
+++ b/target/linux/cns3xxx/patches-4.19/095-gpio_support.patch
@@ -1,67 +0,0 @@
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -223,6 +223,10 @@ static void __init cns3420_init(void)
- 
- 	cns3xxx_ahci_init();
- 	cns3xxx_sdhci_init();
-+	cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
-+		NR_IRQS_CNS3XXX);
-+	cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
-+		NR_IRQS_CNS3XXX + 32);
- 
- 	pm_power_off = cns3xxx_power_off;
- }
--- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -3,6 +3,8 @@ menuconfig ARCH_CNS3XXX
- 	bool "Cavium Networks CNS3XXX family"
- 	depends on ARCH_MULTI_V6
- 	select ARM_GIC
-+	select ARCH_REQUIRE_GPIOLIB
-+	select GENERIC_IRQ_CHIP
- 	select HAVE_ARM_SCU if SMP
- 	select HAVE_ARM_TWD
- 	select HAVE_SMP
--- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -2,7 +2,7 @@
- ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
- 
- obj-$(CONFIG_ARCH_CNS3XXX)		+= cns3xxx.o
-cns3xxx-y				+= core.o pm.o
-+cns3xxx-y				+= core.o pm.o gpio.o
- cns3xxx-$(CONFIG_ATAGS)			+= devices.o
- cns3xxx-$(CONFIG_PCI)			+= pcie.o
- cns3xxx-$(CONFIG_MACH_CNS3420VB)	+= cns3420vb.o
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
-+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
-@@ -68,8 +68,10 @@
- #define SMC_PCELL_ID_3_OFFSET			0xFFC
- 
- #define CNS3XXX_GPIOA_BASE			0x74000000	/* GPIO port A */
-+#define CNS3XXX_GPIOA_BASE_VIRT			0xFB006000
- 
- #define CNS3XXX_GPIOB_BASE			0x74800000	/* GPIO port B */
-+#define CNS3XXX_GPIOB_BASE_VIRT			0xFB007000
- 
- #define CNS3XXX_RTC_BASE			0x75000000	/* Real Time Clock */
- 
--- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
- 		.pfn		= __phys_to_pfn(CNS3XXX_PM_BASE),
- 		.length		= SZ_4K,
- 		.type		= MT_DEVICE,
-+	}, {
-+		.virtual	= CNS3XXX_GPIOA_BASE_VIRT,
-+		.pfn		= __phys_to_pfn(CNS3XXX_GPIOA_BASE),
-+		.length		= SZ_4K,
-+		.type		= MT_DEVICE,
-+	}, {
-+		.virtual	= CNS3XXX_GPIOB_BASE_VIRT,
-+		.pfn		= __phys_to_pfn(CNS3XXX_GPIOB_BASE),
-+		.length		= SZ_4K,
-+		.type		= MT_DEVICE,
- #ifdef CONFIG_PCI
- 	}, {
- 		.virtual	= CNS3XXX_PCIE0_HOST_BASE_VIRT,
--- a/target/linux/cns3xxx/patches-4.19/097-l2x0_cmdline_disable.patch
+++ b/target/linux/cns3xxx/patches-4.19/097-l2x0_cmdline_disable.patch
@@ -1,69 +0,0 @@
--- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -307,13 +307,26 @@ void __init cns3xxx_timer_init(void)
- 
- #ifdef CONFIG_CACHE_L2X0
- 
-void __init cns3xxx_l2x0_init(void)
-+static int cns3xxx_l2x0_enable = 1;
-+
-+static int __init cns3xxx_l2x0_disable(char *s)
-+{
-+	cns3xxx_l2x0_enable = 0;
-+	return 1;
-+}
-+__setup("nol2x0", cns3xxx_l2x0_disable);
-+
-+static int __init cns3xxx_l2x0_init(void)
- {
-	void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
-+	void __iomem *base;
- 	u32 val;
- 
-+	if (!cns3xxx_l2x0_enable)
-+		return 0;
-+
-+	base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
- 	if (WARN_ON(!base))
-		return;
-+		return 0;
- 
- 	/*
- 	 * Tag RAM Control register
-@@ -343,7 +356,10 @@ void __init cns3xxx_l2x0_init(void)
- 
- 	/* 32 KiB, 8-way, parity disable */
- 	l2x0_init(base, 0x00500000, 0xfe0f0fff);
-+
-+	return 0;
- }
-+arch_initcall(cns3xxx_l2x0_init);
- 
- #endif /* CONFIG_CACHE_L2X0 */
- 
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -217,8 +217,6 @@ static struct platform_device *cns3420_p
- 
- static void __init cns3420_init(void)
- {
-	cns3xxx_l2x0_init();
-
- 	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
- 
- 	cns3xxx_ahci_init();
--- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -16,12 +16,6 @@
- extern struct smp_operations cns3xxx_smp_ops;
- extern void cns3xxx_timer_init(void);
- 
-#ifdef CONFIG_CACHE_L2X0
-void __init cns3xxx_l2x0_init(void);
-#else
-static inline void cns3xxx_l2x0_init(void) {}
-#endif /* CONFIG_CACHE_L2X0 */
-
- #ifdef CONFIG_PCI
- extern void __init cns3xxx_pcie_init_late(void);
- #else
--- a/target/linux/cns3xxx/patches-4.19/100-laguna_support.patch
+++ b/target/linux/cns3xxx/patches-4.19/100-laguna_support.patch
@@ -1,46 +0,0 @@
--- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -23,4 +23,12 @@ config MACH_CNS3420VB
- 	  This is a platform with an on-board ARM11 MPCore and has support
- 	  for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
- 
-+config MACH_GW2388
-+	bool "Support for Gateworks Laguna Platform"
-+	help
-+	  Include support for the Gateworks Laguna Platform
-+
-+	  This is a platform with an on-board ARM11 MPCore and has support
-+	  for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
-+
- endif
--- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -8,3 +8,5 @@ cns3xxx-$(CONFIG_PCI)			+= pcie.o
- cns3xxx-$(CONFIG_MACH_CNS3420VB)	+= cns3420vb.o
- cns3xxx-$(CONFIG_SMP)			+= platsmp.o headsmp.o cns3xxx_fiq.o
- cns3xxx-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
-+cns3xxx-$(CONFIG_MACH_GW2388)		+= laguna.o
-+
--- a/arch/arm/mach-cns3xxx/devices.c
-+++ b/arch/arm/mach-cns3xxx/devices.c
-@@ -16,6 +16,7 @@
- #include <linux/compiler.h>
- #include <linux/dma-mapping.h>
- #include <linux/platform_device.h>
-+#include <asm/mach-types.h>
- #include "cns3xxx.h"
- #include "pm.h"
- #include "core.h"
-@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void)
- 	u32 gpioa_pins = __raw_readl(gpioa);
- 
- 	/* MMC/SD pins share with GPIOA */
-	gpioa_pins |= 0x1fff0004;
-+	if (machine_is_gw2388()) {
-+		gpioa_pins |= 0x1fff0000;
-+	} else {
-+		gpioa_pins |= 0x1fff0004;
-+	}
- 	__raw_writel(gpioa_pins, gpioa);
- 
- 	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
--- a/target/linux/cns3xxx/patches-4.19/101-laguna_sdhci_card_detect.patch
+++ b/target/linux/cns3xxx/patches-4.19/101-laguna_sdhci_card_detect.patch
@@ -1,14 +0,0 @@
--- a/drivers/mmc/host/sdhci-cns3xxx.c
-+++ b/drivers/mmc/host/sdhci-cns3xxx.c
-@@ -88,9 +88,9 @@ static const struct sdhci_pltfm_data sdh
- 	.ops = &sdhci_cns3xxx_ops,
- 	.quirks = SDHCI_QUIRK_BROKEN_DMA |
- 		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
-		  SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
- 		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
-		  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
-+		  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
-+		  SDHCI_QUIRK_BROKEN_CARD_DETECTION,
- };
- 
- static int sdhci_cns3xxx_probe(struct platform_device *pdev)
--- a/target/linux/cns3xxx/patches-4.19/110-pci_isolated_interrupts.patch
+++ b/target/linux/cns3xxx/patches-4.19/110-pci_isolated_interrupts.patch
@@ -1,95 +0,0 @@
--- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -18,6 +18,7 @@
- #include <linux/io.h>
- #include <linux/ioport.h>
- #include <linux/interrupt.h>
-+#include <linux/irq.h>
- #include <linux/ptrace.h>
- #include <asm/mach/map.h>
- #include "cns3xxx.h"
-@@ -27,7 +28,7 @@ struct cns3xxx_pcie {
- 	void __iomem *host_regs; /* PCI config registers for host bridge */
- 	void __iomem *cfg0_regs; /* PCI Type 0 config registers */
- 	void __iomem *cfg1_regs; /* PCI Type 1 config registers */
-	unsigned int irqs[2];
-+	unsigned int irqs[5];
- 	struct resource res_io;
- 	struct resource res_mem;
- 	int port;
-@@ -95,7 +96,7 @@ static inline int check_master_abort(str
- 		void __iomem *host_base;
- 		u32 sreg, ereg;
- 
-		host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
-+		host_base = (void __iomem *) cnspci->host_regs;
- 		sreg = __raw_readw(host_base + 0x6) & 0xF900;
- 		ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
- 
-@@ -209,7 +210,7 @@ static struct pci_ops cns3xxx_pcie_ops =
- static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
- {
- 	struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
-	int irq = cnspci->irqs[!!dev->bus->number];
-+	int irq = cnspci->irqs[!!dev->bus->number + pin - 1];
- 
- 	pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
- 		pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
-@@ -235,7 +236,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
- 			.end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
- 			.flags = IORESOURCE_MEM,
- 		},
-		.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
-+		.irqs = {
-+			IRQ_CNS3XXX_PCIE0_RC,
-+			IRQ_CNS3XXX_PCIE0_DEVICE,
-+			IRQ_CNS3XXX_PCIE0_DEVICE,
-+			IRQ_CNS3XXX_PCIE0_DEVICE,
-+			IRQ_CNS3XXX_PCIE0_DEVICE,
-+		},
- 		.port = 0,
- 	},
- 	[1] = {
-@@ -254,7 +261,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
- 			.end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
- 			.flags = IORESOURCE_MEM,
- 		},
-		.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
-+		.irqs = {
-+			IRQ_CNS3XXX_PCIE1_RC,
-+			IRQ_CNS3XXX_PCIE1_DEVICE,
-+			IRQ_CNS3XXX_PCIE1_DEVICE,
-+			IRQ_CNS3XXX_PCIE1_DEVICE,
-+			IRQ_CNS3XXX_PCIE1_DEVICE,
-+		},
- 		.port = 1,
- 	},
- };
-@@ -346,6 +359,14 @@ static int cns3xxx_pcie_abort_handler(un
- 	return 0;
- }
- 
-+void __init cns3xxx_pcie_set_irqs(int bus, int *irqs)
-+{
-+	int i;
-+
-+	for (i = 0; i < 4; i++)
-+		cns3xxx_pcie[bus].irqs[i + 1] = irqs[i];
-+}
-+
- void __init cns3xxx_pcie_init_late(void)
- {
- 	int i;
--- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void);
- 
- #ifdef CONFIG_PCI
- extern void __init cns3xxx_pcie_init_late(void);
-+extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs);
- #else
- static inline void __init cns3xxx_pcie_init_late(void) {}
-+static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {}
- #endif
- 
- void __init cns3xxx_map_io(void);
--- a/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch
+++ b/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch
@@ -1,23 +0,0 @@
--- a/drivers/pci/probe.c
-+++ b/drivers/pci/probe.c
-@@ -2655,7 +2655,8 @@ static void pcie_write_mrrs(struct pci_d
- 	 * In the "safe" case, do not configure the MRRS.  There appear to be
- 	 * issues with setting MRRS to 0 on a number of devices.
- 	 */
-	if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
-+	if (pcie_bus_config != PCIE_BUS_PERFORMANCE &&
-+	    pcie_bus_config != PCIE_BUS_PEER2PEER)
- 		return;
- 
- 	/*
--- a/include/linux/pci.h
-+++ b/include/linux/pci.h
-@@ -868,7 +868,7 @@ enum pcie_bus_config_types {
- 	PCIE_BUS_DEFAULT,	/* Ensure MPS matches upstream bridge */
- 	PCIE_BUS_SAFE,		/* Use largest MPS boot-time devices support */
- 	PCIE_BUS_PERFORMANCE,	/* Use MPS and MRRS for best performance */
-	PCIE_BUS_PEER2PEER,	/* Set MPS = 128 for all devices */
-+	PCIE_BUS_PEER2PEER,	/* set MPS and MRSS to 128 for all devices */
- };
- 
- extern enum pcie_bus_config_types pcie_bus_config;
--- a/target/linux/cns3xxx/patches-4.19/200-broadcom_phy_reinit.patch
+++ b/target/linux/cns3xxx/patches-4.19/200-broadcom_phy_reinit.patch
@@ -1,15 +0,0 @@
--- a/drivers/net/phy/broadcom.c
-+++ b/drivers/net/phy/broadcom.c
-@@ -429,7 +429,11 @@ static int bcm5481_config_aneg(struct ph
- 	ret = genphy_config_aneg(phydev);
- 
- 	/* Then we can set up the delay. */
-	bcm5481x_config(phydev);
-+	//bcm5481x_config(phydev);
-+
-+	phy_write(phydev, 0x18, 0xf1e7);
-+	phy_write(phydev, 0x1c, 0x8e00);
-+	phy_write(phydev, 0x1c, 0xa41f);
- 
- 	if (of_property_read_bool(np, "enet-phy-lane-swap")) {
- 		/* Lane Swap - Undocumented register...magic! */
--- a/target/linux/cns3xxx/patches-4.19/210-dwc2_defaults.patch
+++ b/target/linux/cns3xxx/patches-4.19/210-dwc2_defaults.patch
@@ -1,63 +0,0 @@
--- a/drivers/usb/dwc2/params.c
-+++ b/drivers/usb/dwc2/params.c
-@@ -152,6 +152,36 @@ static void dwc2_set_stm32f7_hsotg_param
- 	p->host_perio_tx_fifo_size = 256;
- }
- 
-+static void dwc2_set_cns3xxx_params(struct dwc2_hsotg *hsotg)
-+{
-+	struct dwc2_core_params *p = &hsotg->params;
-+
-+	p->otg_cap			= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;	/* non-HNP/non-SRP capable */
-+	p->host_dma			= 1;
-+	p->dma_desc_enable		= 0;
-+	p->speed			= DWC2_SPEED_PARAM_HIGH;	/* High Speed */
-+	p->enable_dynamic_fifo		= 1;
-+	p->en_multiple_tx_fifo		= 1;
-+	p->host_rx_fifo_size		= 658;	/* 774 DWORDs */
-+	p->host_nperio_tx_fifo_size	= 128;	/* 256 DWORDs */
-+	p->host_perio_tx_fifo_size	= 658;	/* 512 DWORDs */
-+	p->max_transfer_size		= 65535,
-+	p->max_packet_count		= 511;
-+	p->host_channels		= 16;
-+	p->phy_type			= DWC2_PHY_TYPE_PARAM_UTMI;	/* UTMI */
-+	p->phy_utmi_width		= 16;	/* 8 bits */
-+	p->phy_ulpi_ddr			= 0;	/* Single */
-+	p->phy_ulpi_ext_vbus		= 0;
-+	p->i2c_enable			= 0;
-+	p->ulpi_fs_ls			= 0;
-+	p->host_support_fs_ls_low_power	= 0;
-+	p->host_ls_low_power_phy_clk	= 0;	/* 48 MHz */
-+	p->ts_dline			= 0;
-+	p->reload_ctl			= 0;
-+	p->ahbcfg			= 0x10;
-+	p->uframe_sched			= false;
-+}
-+
- const struct of_device_id dwc2_of_match_table[] = {
- 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
- 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
-@@ -820,17 +850,23 @@ int dwc2_get_hwparams(struct dwc2_hsotg
- 
- int dwc2_init_params(struct dwc2_hsotg *hsotg)
- {
-+	/*
- 	const struct of_device_id *match;
- 	void (*set_params)(void *data);
-+	*/
- 
- 	dwc2_set_default_params(hsotg);
- 	dwc2_get_device_properties(hsotg);
- 
-+	/*
- 	match = of_match_device(dwc2_of_match_table, hsotg->dev);
- 	if (match && match->data) {
- 		set_params = match->data;
- 		set_params(hsotg);
- 	}
-+	*/
-+
-+	dwc2_set_cns3xxx_params(hsotg);
- 
- 	dwc2_check_params(hsotg);
- 
--- a/target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch
+++ b/target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch
@@ -1,6 +1,16 @@
+From: MarkLee <Mark-MC.Lee@mediatek.com>
+Date: Wed, 13 Nov 2019 10:38:42 +0800
+Subject: [PATCH] net: ethernet: mediatek: Integrate GDM/PSE setup operations
+
+Integrate GDM/PSE setup operations into single function "mtk_gdm_config"
+
+Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2240,6 +2240,31 @@ static int mtk_start_dma(struct mtk_eth
+@@ -2211,6 +2211,28 @@ static int mtk_start_dma(struct mtk_eth
 	return 0;
 }
 
@@ -8,9 +18,6 @@
 +{
 +	int i;
 +
-+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
-+		return;
-+
 +	for (i = 0; i < MTK_MAC_COUNT; i++) {
 +		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
 +
@@ -32,26 +39,8 @@
 static int mtk_open(struct net_device *dev)
 {
 	struct mtk_mac *mac = netdev_priv(dev);
-@@ -2260,6 +2285,8 @@ static int mtk_open(struct net_device *d
- 		if (err)
- 			return err;
- 
-+		mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
-+
- 		napi_enable(&eth->tx_napi);
- 		napi_enable(&eth->rx_napi);
- 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
-@@ -2315,6 +2342,8 @@ static int mtk_stop(struct net_device *d
- 	if (!refcount_dec_and_test(&eth->dma_refcnt))
- 		return 0;
- 
-+	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
-+
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
- 	mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
- 	napi_disable(&eth->tx_napi);
-@@ -2498,8 +2527,6 @@ static int mtk_hw_init(struct mtk_eth *e
- 	/* disable delay and normal interrupt */
+@@ -2406,8 +2428,6 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
 	mtk_tx_irq_disable(eth, ~0);
 	mtk_rx_irq_disable(eth, ~0);
 -	mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
@@ -59,7 +48,7 @@
 
 	/* FE int grouping */
 	mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
-@@ -2508,19 +2535,6 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2416,18 +2436,7 @@ static int mtk_hw_init(struct mtk_eth *e
 	mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
 
@@ -75,18 +64,17 @@
 -		/* setup the mac dma */
 -		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
 -	}
-
+	mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
+ 
 	return 0;
 
- err_disable_pm:
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -85,6 +85,8 @@
+@@ -84,6 +84,7 @@
 #define MTK_GDMA_ICS_EN		BIT(22)
 #define MTK_GDMA_TCS_EN		BIT(21)
 #define MTK_GDMA_UCS_EN		BIT(20)
 +#define MTK_GDMA_TO_PDMA	0x0
-+#define MTK_GDMA_DROP_ALL	0x7777
 
 /* Unicast Filter MAC Address Register - Low */
 #define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
--- a/target/linux/generic/backport-5.4/761-net-ethernet-mediatek-Refine-the-timing-of-GDM-PSE-s.patch
+++ b/target/linux/generic/backport-5.4/761-net-ethernet-mediatek-Refine-the-timing-of-GDM-PSE-s.patch
@@ -0,0 +1,45 @@
+From: MarkLee <Mark-MC.Lee@mediatek.com>
+Date: Wed, 13 Nov 2019 10:38:43 +0800
+Subject: [PATCH] net: ethernet: mediatek: Refine the timing of GDM/PSE setup
+
+Refine the timing of GDM/PSE setup, move it from mtk_hw_init
+to mtk_open. This is recommended by the mt762x HW design to
+do GDM/PSE setup only after PDMA has been started.
+
+We exclude mt7628 in mtk_gdm_config function since it is a old IP
+and there is no GDM/PSE block on it.
+
+Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -2215,6 +2215,9 @@ static void mtk_gdm_config(struct mtk_et
+ {
+ 	int i;
+ 
+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+		return;
+
+ 	for (i = 0; i < MTK_MAC_COUNT; i++) {
+ 		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
+ 
+@@ -2253,6 +2256,8 @@ static int mtk_open(struct net_device *d
+ 		if (err)
+ 			return err;
+ 
+		mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
+
+ 		napi_enable(&eth->tx_napi);
+ 		napi_enable(&eth->rx_napi);
+ 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
+@@ -2436,8 +2441,6 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
+ 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+ 
+-	mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
+-
+ 	return 0;
+ 
+ err_disable_pm:
--- a/target/linux/generic/backport-5.4/762-net-ethernet-mediatek-Enable-GDM-GDMA_DROP_ALL-mode.patch
+++ b/target/linux/generic/backport-5.4/762-net-ethernet-mediatek-Enable-GDM-GDMA_DROP_ALL-mode.patch
@@ -0,0 +1,33 @@
+From: MarkLee <Mark-MC.Lee@mediatek.com>
+Date: Wed, 13 Nov 2019 10:38:44 +0800
+Subject: [PATCH] net: ethernet: mediatek: Enable GDM GDMA_DROP_ALL mode
+
+Enable GDM GDMA_DROP_ALL mode to drop all packet during the
+stop operation. This is recommended by the mt762x HW design
+to drop all packet from GMAC before stopping PDMA.
+
+Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -2310,6 +2310,8 @@ static int mtk_stop(struct net_device *d
+ 	if (!refcount_dec_and_test(&eth->dma_refcnt))
+ 		return 0;
+ 
+	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
+
+ 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
+ 	mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
+ 	napi_disable(&eth->tx_napi);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -85,6 +85,7 @@
+ #define MTK_GDMA_TCS_EN		BIT(21)
+ #define MTK_GDMA_UCS_EN		BIT(20)
+ #define MTK_GDMA_TO_PDMA	0x0
+#define MTK_GDMA_DROP_ALL       0x7777
+ 
+ /* Unicast Filter MAC Address Register - Low */
+ #define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
--- a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c
+++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c
@@ -319,8 +319,57 @@ static struct mtd_part_parser uimage_netgear_parser = {
 	.of_match_table = mtdsplit_uimage_netgear_of_match_table,
 	.parse_fn = mtdsplit_uimage_parse_netgear,
 	.type = MTD_PARSER_TYPE_FIRMWARE,
+
 };

+
+/**************************************************
+ * ALLNET
+ **************************************************/
+
+#define FW_MAGIC_SG8208M	0x00000006
+#define FW_MAGIC_SG8310PM	0x83000006
+
+static ssize_t uimage_verify_allnet(u_char *buf, size_t len, int *extralen)
+{
+	struct uimage_header *header = (struct uimage_header *)buf;
+
+	switch (be32_to_cpu(header->ih_magic)) {
+	case FW_MAGIC_SG8208M:
+	case FW_MAGIC_SG8310PM:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (header->ih_os != IH_OS_LINUX)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int
+mtdsplit_uimage_parse_allnet(struct mtd_info *master,
+			      const struct mtd_partition **pparts,
+			      struct mtd_part_parser_data *data)
+{
+	return __mtdsplit_parse_uimage(master, pparts, data,
+				      uimage_verify_allnet);
+}
+
+static const struct of_device_id mtdsplit_uimage_allnet_of_match_table[] = {
+	{ .compatible = "allnet,uimage" },
+	{},
+};
+
+static struct mtd_part_parser uimage_allnet_parser = {
+	.owner = THIS_MODULE,
+	.name = "allnet-fw",
+	.of_match_table = mtdsplit_uimage_allnet_of_match_table,
+	.parse_fn = mtdsplit_uimage_parse_allnet,
+};
+
+
 /**************************************************
 * Edimax
 **************************************************/
@@ -505,6 +554,7 @@ static int __init mtdsplit_uimage_init(void)
 {
 	register_mtd_parser(&uimage_generic_parser);
 	register_mtd_parser(&uimage_netgear_parser);
+	register_mtd_parser(&uimage_allnet_parser);
 	register_mtd_parser(&uimage_edimax_parser);
 	register_mtd_parser(&uimage_fonfxc_parser);
 	register_mtd_parser(&uimage_sge_parser);
--- a/target/linux/generic/hack-4.14/952-net-conntrack-events-support-multiple-registrant.patch
+++ b/target/linux/generic/hack-4.14/952-net-conntrack-events-support-multiple-registrant.patch
@@ -1,325 +0,0 @@
-diff --git a/include/net/netfilter/nf_conntrack_ecache.h b/include/net/netfilter/nf_conntrack_ecache.h
-index 12d967b..c2b98b6 100644
--- a/include/net/netfilter/nf_conntrack_ecache.h
-+++ b/include/net/netfilter/nf_conntrack_ecache.h
-@@ -71,6 +71,10 @@ struct nf_ct_event {
- 	int report;
- };
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+extern int nf_conntrack_register_notifier(struct net *net, struct notifier_block *nb);
-+extern int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb);
-+#else
- struct nf_ct_event_notifier {
- 	int (*fcn)(unsigned int events, struct nf_ct_event *item);
- };
-@@ -79,7 +83,7 @@ int nf_conntrack_register_notifier(struc
- 				   struct nf_ct_event_notifier *nb);
- void nf_conntrack_unregister_notifier(struct net *net,
- 				      struct nf_ct_event_notifier *nb);
-
-+#endif
- void nf_ct_deliver_cached_events(struct nf_conn *ct);
- int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
- 				  u32 portid, int report);
-@@ -87,12 +91,15 @@ int nf_conntrack_eventmask_report(unsign
- static inline void
- nf_conntrack_event_cache(enum ip_conntrack_events event, struct nf_conn *ct)
- {
-	struct net *net = nf_ct_net(ct);
- 	struct nf_conntrack_ecache *e;
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	struct net *net = nf_ct_net(ct);
- 
- 	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
- 		return;
- 
-+#endif
-+
- 	e = nf_ct_ecache_find(ct);
- 	if (e == NULL)
- 		return;
-@@ -104,10 +111,12 @@ static inline int
- nf_conntrack_event_report(enum ip_conntrack_events event, struct nf_conn *ct,
- 			  u32 portid, int report)
- {
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
- 	const struct net *net = nf_ct_net(ct);
- 
- 	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
- 		return 0;
-+#endif
- 
- 	return nf_conntrack_eventmask_report(1 << event, ct, portid, report);
- }
-@@ -115,11 +124,14 @@ nf_conntrack_event_report(enum ip_conntr
- static inline int
- nf_conntrack_event(enum ip_conntrack_events event, struct nf_conn *ct)
- {
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
- 	const struct net *net = nf_ct_net(ct);
- 
- 	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
- 		return 0;
- 
-+#endif
-+
- 	return nf_conntrack_eventmask_report(1 << event, ct, 0, 0);
- }
- 
-diff --git a/include/net/netns/conntrack.h b/include/net/netns/conntrack.h
-index e469e85..1d31db8 100644
--- a/include/net/netns/conntrack.h
-+++ b/include/net/netns/conntrack.h
-@@ -114,7 +114,11 @@ struct netns_ct {
- 
- 	struct ct_pcpu __percpu *pcpu_lists;
- 	struct ip_conntrack_stat __percpu *stat;
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	struct atomic_notifier_head nf_conntrack_chain;
-+#else
- 	struct nf_ct_event_notifier __rcu *nf_conntrack_event_cb;
-+#endif
- 	struct nf_exp_event_notifier __rcu *nf_expect_event_cb;
- 	struct nf_ip_net	nf_ct_proto;
- #if defined(CONFIG_NF_CONNTRACK_LABELS)
-diff --git a/net/netfilter/Kconfig b/net/netfilter/Kconfig
-index 63073be..08d7aab 100644
--- a/net/netfilter/Kconfig
-+++ b/net/netfilter/Kconfig
-@@ -118,6 +118,14 @@ config NF_CONNTRACK_EVENTS
- 
- 	  If unsure, say `N'.
- 
-+config NF_CONNTRACK_CHAIN_EVENTS
-+	bool "Register multiple callbacks to ct events"
-+	depends on NF_CONNTRACK_EVENTS
-+	help
-+	  Support multiple registrations.
-+
-+	  If unsure, say `N'.
-+
- config NF_CONNTRACK_TIMEOUT
- 	bool  'Connection tracking timeout'
- 	depends on NETFILTER_ADVANCED
-diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c
-index 6bd1508..9b81c7c 100644
--- a/net/netfilter/nf_conntrack_core.c
-+++ b/net/netfilter/nf_conntrack_core.c
-@@ -2167,6 +2167,10 @@ int nf_conntrack_init_net(struct net *ne
- 	ret = nf_conntrack_proto_pernet_init(net);
- 	if (ret < 0)
- 		goto err_proto;
-+
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	ATOMIC_INIT_NOTIFIER_HEAD(&net->ct.nf_conntrack_chain);
-+#endif
- 	return 0;
- 
- err_proto:
-diff --git a/net/netfilter/nf_conntrack_ecache.c b/net/netfilter/nf_conntrack_ecache.c
-index da9df2d..e0e2a8f 100644
--- a/net/netfilter/nf_conntrack_ecache.c
-+++ b/net/netfilter/nf_conntrack_ecache.c
-@@ -18,6 +18,9 @@
- #include <linux/stddef.h>
- #include <linux/err.h>
- #include <linux/percpu.h>
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+#include <linux/notifier.h>
-+#endif
- #include <linux/kernel.h>
- #include <linux/netdevice.h>
- #include <linux/slab.h>
-@@ -117,6 +120,38 @@ static void ecache_work(struct work_stru
- 		schedule_delayed_work(&ctnet->ecache_dwork, delay);
- }
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+int
-+nf_conntrack_eventmask_report(unsigned int eventmask,
-+			      struct nf_conn *ct,
-+			      u32 portid,
-+			      int report)
-+{
-+	struct nf_conntrack_ecache *e;
-+	struct net *net = nf_ct_net(ct);
-+
-+	e = nf_ct_ecache_find(ct);
-+	if (e == NULL)
-+		return 0;
-+
-+	if (nf_ct_is_confirmed(ct)) {
-+		struct nf_ct_event item = {
-+			.ct = ct,
-+			.portid	= e->portid ? e->portid : portid,
-+			.report = report
-+		};
-+		/* This is a resent of a destroy event? If so, skip missed */
-+		unsigned long missed = e->portid ? 0 : e->missed;
-+
-+		if (!((eventmask | missed) & e->ctmask))
-+			return 0;
-+
-+		atomic_notifier_call_chain(&net->ct.nf_conntrack_chain, eventmask | missed, &item);
-+	}
-+
-+	return 0;
-+}
-+#else
- int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
- 				  u32 portid, int report)
- {
-@@ -171,10 +206,52 @@ out_unlock:
- 	rcu_read_unlock();
- 	return ret;
- }
-+#endif
- EXPORT_SYMBOL_GPL(nf_conntrack_eventmask_report);
- 
- /* deliver cached events and clear cache entry - must be called with locally
-  * disabled softirqs */
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+void nf_ct_deliver_cached_events(struct nf_conn *ct)
-+{
-+	unsigned long events, missed;
-+	struct nf_conntrack_ecache *e;
-+	struct nf_ct_event item;
-+	struct net *net = nf_ct_net(ct);
-+
-+	e = nf_ct_ecache_find(ct);
-+	if (e == NULL)
-+		return;
-+
-+	events = xchg(&e->cache, 0);
-+
-+	if (!nf_ct_is_confirmed(ct) || nf_ct_is_dying(ct) || !events)
-+		return;
-+
-+	/* We make a copy of the missed event cache without taking
-+	 * the lock, thus we may send missed events twice. However,
-+	 * this does not harm and it happens very rarely. */
-+	missed = e->missed;
-+
-+	if (!((events | missed) & e->ctmask))
-+		return;
-+
-+	item.ct = ct;
-+	item.portid = 0;
-+	item.report = 0;
-+
-+	atomic_notifier_call_chain(&net->ct.nf_conntrack_chain,
-+			events | missed,
-+			&item);
-+
-+	if (likely(!missed))
-+		return;
-+
-+	spin_lock_bh(&ct->lock);
-+		e->missed &= ~missed;
-+	spin_unlock_bh(&ct->lock);
-+}
-+#else
- void nf_ct_deliver_cached_events(struct nf_conn *ct)
- {
- 	struct net *net = nf_ct_net(ct);
-@@ -225,6 +302,7 @@ void nf_ct_deliver_cached_events(struct
- out_unlock:
- 	rcu_read_unlock();
- }
-+#endif
- EXPORT_SYMBOL_GPL(nf_ct_deliver_cached_events);
- 
- void nf_ct_expect_event_report(enum ip_conntrack_expect_events event,
-@@ -257,6 +335,12 @@ out_unlock:
- 	rcu_read_unlock();
- }
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+int nf_conntrack_register_notifier(struct net *net, struct notifier_block *nb)
-+{
-+        return atomic_notifier_chain_register(&net->ct.nf_conntrack_chain, nb);
-+}
-+#else
- int nf_conntrack_register_notifier(struct net *net,
- 				   struct nf_ct_event_notifier *new)
- {
-@@ -277,8 +361,15 @@ out_unlock:
- 	mutex_unlock(&nf_ct_ecache_mutex);
- 	return ret;
- }
-+#endif
- EXPORT_SYMBOL_GPL(nf_conntrack_register_notifier);
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb)
-+{
-+	return atomic_notifier_chain_unregister(&net->ct.nf_conntrack_chain, nb);
-+}
-+#else
- void nf_conntrack_unregister_notifier(struct net *net,
- 				      struct nf_ct_event_notifier *new)
- {
-@@ -292,6 +383,7 @@ void nf_conntrack_unregister_notifier(st
- 	mutex_unlock(&nf_ct_ecache_mutex);
- 	/* synchronize_rcu() is called from ctnetlink_exit. */
- }
-+#endif
- EXPORT_SYMBOL_GPL(nf_conntrack_unregister_notifier);
- 
- int nf_ct_expect_register_notifier(struct net *net,
-diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c
-index 04111c1..8c741f7 100644
--- a/net/netfilter/nf_conntrack_netlink.c
-+++ b/net/netfilter/nf_conntrack_netlink.c
-@@ -28,6 +28,11 @@
- #include <linux/netlink.h>
- #include <linux/spinlock.h>
- #include <linux/interrupt.h>
-+
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+#include <linux/notifier.h>
-+#endif
-+
- #include <linux/slab.h>
- 
- #include <linux/netfilter.h>
-@@ -618,14 +623,22 @@ static size_t ctnetlink_nlmsg_size(const
- 	       ;
- }
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+static int ctnetlink_conntrack_event(struct notifier_block *this,
-+                           unsigned long events, void *ptr)
-+#else
- static int
- ctnetlink_conntrack_event(unsigned int events, struct nf_ct_event *item)
-+#endif
- {
- 	const struct nf_conntrack_zone *zone;
- 	struct net *net;
- 	struct nlmsghdr *nlh;
- 	struct nfgenmsg *nfmsg;
- 	struct nlattr *nest_parms;
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	struct nf_ct_event *item = (struct nf_ct_event *)ptr;
-+#endif
- 	struct nf_conn *ct = item->ct;
- 	struct sk_buff *skb;
- 	unsigned int type;
-@@ -3290,9 +3303,15 @@ static int ctnetlink_stat_exp_cpu(struct
- }
- 
- #ifdef CONFIG_NF_CONNTRACK_EVENTS
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+static struct notifier_block ctnl_notifier = {
-+	.notifier_call = ctnetlink_conntrack_event,
-+};
-+#else
- static struct nf_ct_event_notifier ctnl_notifier = {
- 	.fcn = ctnetlink_conntrack_event,
- };
-+#endif
- 
- static struct nf_exp_event_notifier ctnl_notifier_exp = {
- 	.fcn = ctnetlink_expect_event,
--- a/target/linux/generic/hack-4.14/999-net-patch-linux-kernel-to-support-shortcut-fe.patch
+++ b/target/linux/generic/hack-4.14/999-net-patch-linux-kernel-to-support-shortcut-fe.patch
@@ -1,236 +0,0 @@
--- a/include/linux/skbuff.h	2019-01-16 20:16:08.325745306 +0800
-+++ b/include/linux/skbuff.h	2019-01-16 20:31:47.288028493 +0800
-@@ -783,6 +783,9 @@ struct sk_buff {
- 	__u8			tc_from_ingress:1;
- #endif
- 	__u8			gro_skip:1;
-+#ifdef CONFIG_SHORTCUT_FE
-+	__u8			fast_forwarded:1;
-+#endif
- 
- #ifdef CONFIG_NET_SCHED
- 	__u16			tc_index;	/* traffic control index */
--- a/include/linux/if_bridge.h	2019-01-16 20:51:47.871445535 +0800
-+++ b/include/linux/if_bridge.h	2019-01-16 20:52:26.220269649 +0800
-@@ -54,6 +54,8 @@ struct br_ip_list {
- #define BR_DEFAULT_AGEING_TIME	(300 * HZ)
- 
- extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *));
-+extern void br_dev_update_stats(struct net_device *dev,
-+				struct rtnl_link_stats64 *nlstats);
- 
- typedef int br_should_route_hook_t(struct sk_buff *skb);
- extern br_should_route_hook_t __rcu *br_should_route_hook;
--- a/include/linux/timer.h
-+++ b/include/linux/timer.h
-@@ -20,6 +20,9 @@ struct timer_list {
- 	void			(*function)(unsigned long);
- 	unsigned long		data;
- 	u32			flags;
-+#ifdef CONFIG_SHORTCUT_FE
-+	unsigned long		cust_data;
-+#endif
- 
- #ifdef CONFIG_LOCKDEP
- 	struct lockdep_map	lockdep_map;
--- a/net/Kconfig	2019-01-16 20:36:30.266465286 +0800
-+++ b/net/Kconfig	2019-01-16 20:36:41.980609067 +0800
-@@ -463,3 +463,6 @@ config HAVE_CBPF_JIT
- # Extended BPF JIT (eBPF)
- config HAVE_EBPF_JIT
- 	bool
-+
-+config SHORTCUT_FE
-+	bool "Enables kernel network stack path for Shortcut  Forwarding Engine
--- a/net/core/dev.c	2019-01-16 20:38:37.274933833 +0800
-+++ b/net/core/dev.c	2019-01-16 20:44:07.773594898 +0800
-@@ -3005,8 +3005,17 @@ static int xmit_one(struct sk_buff *skb, struct net_device *dev,
- 		!(skb->imq_flags & IMQ_F_ENQUEUE))
- #else
- 	if (!list_empty(&ptype_all) || !list_empty(&dev->ptype_all))
-+#endif
-+#ifdef CONFIG_SHORTCUT_FE
-+	/* If this skb has been fast forwarded then we don't want it to
-+	 * go to any taps (by definition we're trying to bypass them).
-+	 */
-+	if (!skb->fast_forwarded) {
- #endif
- 		dev_queue_xmit_nit(skb, dev);
-+#ifdef CONFIG_SHORTCUT_FE
-+	}
-+#endif
- 
- #ifdef CONFIG_ETHERNET_PACKET_MANGLE
- 	if (!dev->eth_mangle_tx ||
-@@ -4315,6 +4324,11 @@ void netdev_rx_handler_unregister(struct
- }
- EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
- 
-+#ifdef CONFIG_SHORTCUT_FE
-+int (*athrs_fast_nat_recv)(struct sk_buff *skb) __rcu __read_mostly;
-+EXPORT_SYMBOL_GPL(athrs_fast_nat_recv);
-+#endif
-+
- /*
-  * Limit the use of PFMEMALLOC reserves to those protocols that implement
-  * the special handling of PFMEMALLOC skbs.
-@@ -4362,6 +4376,9 @@ static int __netif_receive_skb_core(stru
- 	bool deliver_exact = false;
- 	int ret = NET_RX_DROP;
- 	__be16 type;
-+#ifdef CONFIG_SHORTCUT_FE
-+	int (*fast_recv)(struct sk_buff *skb);
-+#endif
- 
- 	net_timestamp_check(!netdev_tstamp_prequeue, skb);
- 
-@@ -4388,6 +4405,16 @@ another_round:
- 			goto out;
- 	}
- 
-+#ifdef CONFIG_SHORTCUT_FE
-+	fast_recv = rcu_dereference(athrs_fast_nat_recv);
-+	if (fast_recv) {
-+		if (fast_recv(skb)) {
-+			ret = NET_RX_SUCCESS;
-+			goto out;
-+		}
-+	}
-+#endif
-+
- 	if (skb_skip_tc_classify(skb))
- 		goto skip_classify;
- 
--- a/net/netfilter/nf_conntrack_proto_tcp.c	2019-01-16 20:47:40.886993297 +0800
-+++ b/net/netfilter/nf_conntrack_proto_tcp.c	2019-01-16 20:48:57.700570104 +0800
-@@ -35,11 +35,17 @@
- 
- /* Do not check the TCP window for incoming packets  */
- static int nf_ct_tcp_no_window_check __read_mostly = 1;
-+#ifdef CONFIG_SHORTCUT_FE
-+EXPORT_SYMBOL_GPL(nf_ct_tcp_no_window_check);
-+#endif
- 
- /* "Be conservative in what you do,
-     be liberal in what you accept from others."
-     If it's non-zero, we mark only out of window RST segments as INVALID. */
- static int nf_ct_tcp_be_liberal __read_mostly = 0;
-+#ifdef CONFIG_SHORTCUT_FE
-+EXPORT_SYMBOL_GPL(nf_ct_tcp_be_liberal);
-+#endif
- 
- /* If it is set to zero, we disable picking up already established
-    connections. */
--- a/net/bridge/br_if.c	2019-01-16 20:54:51.919367044 +0800
-+++ b/net/bridge/br_if.c	2019-01-16 20:55:53.812401263 +0800
-@@ -653,3 +653,26 @@ void br_port_flags_change(struct net_bri
- 	if (mask & BR_AUTO_MASK)
- 		nbp_update_port_count(br);
- }
-+
-+/* Update bridge statistics for bridge packets processed by offload engines */
-+void br_dev_update_stats(struct net_device *dev,
-+			 struct rtnl_link_stats64 *nlstats)
-+{
-+	struct net_bridge *br;
-+	struct pcpu_sw_netstats *stats;
-+
-+	/* Is this a bridge? */
-+	if (!(dev->priv_flags & IFF_EBRIDGE))
-+		return;
-+
-+	br = netdev_priv(dev);
-+	stats = this_cpu_ptr(br->stats);
-+
-+	u64_stats_update_begin(&stats->syncp);
-+	stats->rx_packets += nlstats->rx_packets;
-+	stats->rx_bytes += nlstats->rx_bytes;
-+	stats->tx_packets += nlstats->tx_packets;
-+	stats->tx_bytes += nlstats->tx_bytes;
-+	u64_stats_update_end(&stats->syncp);
-+}
-+EXPORT_SYMBOL_GPL(br_dev_update_stats);
--- a/net/netfilter/Kconfig	2019-01-16 21:07:34.543460920 +0800
-+++ b/net/netfilter/Kconfig	2019-01-16 21:08:14.739465937 +0800
-@@ -146,6 +146,14 @@ config NF_CONNTRACK_TIMEOUT
- 
- 	  If unsure, say `N'.
- 
-+config NF_CONNTRACK_CHAIN_EVENTS
-+	bool "Register multiple callbacks to ct events"
-+	depends on NF_CONNTRACK_EVENTS
-+	help
-+	  Support multiple registrations.
-+
-+	  If unsure, say `N'.
-+
- config NF_CONNTRACK_TIMESTAMP
- 	bool  'Connection tracking timestamping'
- 	depends on NETFILTER_ADVANCED
--- a/net/netfilter/nf_conntrack_ecache.c	2019-01-16 21:12:22.183462975 +0800
-+++ b/net/netfilter/nf_conntrack_ecache.c	2019-01-16 21:26:10.379462031 +0800
-@@ -122,13 +125,17 @@ int nf_conntrack_eventmask_report(unsign
- {
- 	int ret = 0;
- 	struct net *net = nf_ct_net(ct);
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
- 	struct nf_ct_event_notifier *notify;
-+#endif
- 	struct nf_conntrack_ecache *e;
- 
- 	rcu_read_lock();
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
- 	notify = rcu_dereference(net->ct.nf_conntrack_event_cb);
- 	if (!notify)
- 		goto out_unlock;
-+#endif
- 
- 	e = nf_ct_ecache_find(ct);
- 	if (!e)
-@@ -146,7 +153,12 @@ int nf_conntrack_eventmask_report(unsign
- 		if (!((eventmask | missed) & e->ctmask))
- 			goto out_unlock;
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+		ret = atomic_notifier_call_chain(&net->ct.nf_conntrack_chain,
-+			eventmask | missed, &item);
-+#else
- 		ret = notify->fcn(eventmask | missed, &item);
-+#endif
- 		if (unlikely(ret < 0 || missed)) {
- 			spin_lock_bh(&ct->lock);
- 			if (ret < 0) {
-@@ -179,15 +191,19 @@ void nf_ct_deliver_cached_events(struct
- {
- 	struct net *net = nf_ct_net(ct);
- 	unsigned long events, missed;
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
- 	struct nf_ct_event_notifier *notify;
-+#endif
- 	struct nf_conntrack_ecache *e;
- 	struct nf_ct_event item;
- 	int ret;
- 
- 	rcu_read_lock();
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
- 	notify = rcu_dereference(net->ct.nf_conntrack_event_cb);
- 	if (notify == NULL)
- 		goto out_unlock;
-+#endif
- 
- 	e = nf_ct_ecache_find(ct);
- 	if (e == NULL)
-@@ -210,7 +226,13 @@ void nf_ct_deliver_cached_events(struct
- 	item.portid = 0;
- 	item.report = 0;
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	ret = atomic_notifier_call_chain(&net->ct.nf_conntrack_chain,
-+			events | missed,
-+			&item);
-+#else
- 	ret = notify->fcn(events | missed, &item);
-+#endif
- 
- 	if (likely(ret == 0 && !missed))
- 		goto out_unlock;
--- a/target/linux/generic/hack-4.9/952-net-conntrack-events-support-multiple-registrant.patch
+++ b/target/linux/generic/hack-4.9/952-net-conntrack-events-support-multiple-registrant.patch
@@ -1,345 +0,0 @@
-From 56294a39f14712f868a495f28be6b2e92f0a48c6 Mon Sep 17 00:00:00 2001
-From: Zhi Chen <zhichen@codeaurora.org>
-Date: Tue, 13 Jan 2015 14:28:18 -0800
-Subject: [PATCH 3/3] net: conntrack events, support multiple registrant
-
-Merging this patch from kernel 3.4:
-This was supported by old (.28) kernel versions but removed
-because of it's overhead.
-But we need this feature for NA connection manager. Both ipv4
-and ipv6 modules needs to register themselves to ct events.
-
-Change-Id: Iebfb254590fb594f5baf232f849d1b7ae45ef757
-Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
---
- include/net/netfilter/nf_conntrack_ecache.h | 13 +++-
- include/net/netns/conntrack.h               |  4 ++
- net/netfilter/Kconfig                       |  8 +++
- net/netfilter/nf_conntrack_core.c           |  4 ++
- net/netfilter/nf_conntrack_ecache.c         | 92 +++++++++++++++++++++++++++++
- net/netfilter/nf_conntrack_netlink.c        | 19 ++++++
- 6 files changed, 139 insertions(+), 1 deletion(-)
-
-diff --git a/include/net/netfilter/nf_conntrack_ecache.h b/include/net/netfilter/nf_conntrack_ecache.h
-index 12d967b..c2b98b6 100644
--- a/include/net/netfilter/nf_conntrack_ecache.h
-+++ b/include/net/netfilter/nf_conntrack_ecache.h
-@@ -70,6 +70,10 @@ struct nf_ct_event {
- 	int report;
- };
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+extern int nf_conntrack_register_notifier(struct net *net, struct notifier_block *nb);
-+extern int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb);
-+#else
- struct nf_ct_event_notifier {
- 	int (*fcn)(unsigned int events, struct nf_ct_event *item);
- };
-@@ -78,6 +82,7 @@ int nf_conntrack_register_notifier(struct net *net,
- 				   struct nf_ct_event_notifier *nb);
- void nf_conntrack_unregister_notifier(struct net *net,
- 				      struct nf_ct_event_notifier *nb);
-+#endif
- 
- void nf_ct_deliver_cached_events(struct nf_conn *ct);
- int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
-@@ -86,11 +91,13 @@ int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
- static inline void
- nf_conntrack_event_cache(enum ip_conntrack_events event, struct nf_conn *ct)
- {
-	struct net *net = nf_ct_net(ct);
- 	struct nf_conntrack_ecache *e;
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	struct net *net = nf_ct_net(ct);
- 
- 	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
- 		return;
-+#endif
- 
- 	e = nf_ct_ecache_find(ct);
- 	if (e == NULL)
-@@ -103,10 +110,12 @@ static inline int
- nf_conntrack_event_report(enum ip_conntrack_events event, struct nf_conn *ct,
- 			  u32 portid, int report)
- {
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
- 	const struct net *net = nf_ct_net(ct);
- 
- 	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
- 		return 0;
-+#endif
- 
- 	return nf_conntrack_eventmask_report(1 << event, ct, portid, report);
- }
-@@ -114,10 +123,12 @@ nf_conntrack_event_report(enum ip_conntrack_events event, struct nf_conn *ct,
- static inline int
- nf_conntrack_event(enum ip_conntrack_events event, struct nf_conn *ct)
- {
-+#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
- 	const struct net *net = nf_ct_net(ct);
- 
- 	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
- 		return 0;
-+#endif
- 
- 	return nf_conntrack_eventmask_report(1 << event, ct, 0, 0);
- }
-diff --git a/include/net/netns/conntrack.h b/include/net/netns/conntrack.h
-index e469e85..1d31db8 100644
--- a/include/net/netns/conntrack.h
-+++ b/include/net/netns/conntrack.h
-@@ -86,7 +86,11 @@ struct netns_ct {
- 
- 	struct ct_pcpu __percpu *pcpu_lists;
- 	struct ip_conntrack_stat __percpu *stat;
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	struct atomic_notifier_head nf_conntrack_chain;
-+#else
- 	struct nf_ct_event_notifier __rcu *nf_conntrack_event_cb;
-+#endif
- 	struct nf_exp_event_notifier __rcu *nf_expect_event_cb;
- 	struct nf_ip_net	nf_ct_proto;
- #if defined(CONFIG_NF_CONNTRACK_LABELS)
-diff --git a/net/netfilter/Kconfig b/net/netfilter/Kconfig
-index 63073be..08d7aab 100644
--- a/net/netfilter/Kconfig
-+++ b/net/netfilter/Kconfig
-@@ -136,6 +136,14 @@ config NF_CONNTRACK_TIMEOUT
- 
- 	  If unsure, say `N'.
- 
-+config NF_CONNTRACK_CHAIN_EVENTS
-+	bool "Register multiple callbacks to ct events"
-+	depends on NF_CONNTRACK_EVENTS
-+	help
-+	  Support multiple registrations.
-+
-+	  If unsure, say `N'.
-+
- config NF_CONNTRACK_TIMESTAMP
- 	bool  'Connection tracking timestamping'
- 	depends on NETFILTER_ADVANCED
-diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c
-index 6bd1508..9b81c7c 100644
--- a/net/netfilter/nf_conntrack_core.c
-+++ b/net/netfilter/nf_conntrack_core.c
-@@ -1998,6 +1998,10 @@ int nf_conntrack_init_net(struct net *net)
- 	ret = nf_conntrack_proto_pernet_init(net);
- 	if (ret < 0)
- 		goto err_proto;
-+
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	ATOMIC_INIT_NOTIFIER_HEAD(&net->ct.nf_conntrack_chain);
-+#endif
- 	return 0;
- 
- err_proto:
-diff --git a/net/netfilter/nf_conntrack_ecache.c b/net/netfilter/nf_conntrack_ecache.c
-index da9df2d..e0e2a8f 100644
--- a/net/netfilter/nf_conntrack_ecache.c
-+++ b/net/netfilter/nf_conntrack_ecache.c
-@@ -18,6 +18,9 @@
- #include <linux/stddef.h>
- #include <linux/err.h>
- #include <linux/percpu.h>
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+#include <linux/notifier.h>
-+#endif
- #include <linux/kernel.h>
- #include <linux/netdevice.h>
- #include <linux/slab.h>
-@@ -117,6 +120,38 @@ static void ecache_work(struct work_struct *work)
- 		schedule_delayed_work(&ctnet->ecache_dwork, delay);
- }
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+int
-+nf_conntrack_eventmask_report(unsigned int eventmask,
-+			      struct nf_conn *ct,
-+			      u32 portid,
-+			      int report)
-+{
-+	struct nf_conntrack_ecache *e;
-+	struct net *net = nf_ct_net(ct);
-+
-+	e = nf_ct_ecache_find(ct);
-+	if (e == NULL)
-+		return 0;
-+
-+	if (nf_ct_is_confirmed(ct)) {
-+		struct nf_ct_event item = {
-+			.ct = ct,
-+			.portid	= e->portid ? e->portid : portid,
-+			.report = report
-+		};
-+		/* This is a resent of a destroy event? If so, skip missed */
-+		unsigned long missed = e->portid ? 0 : e->missed;
-+
-+		if (!((eventmask | missed) & e->ctmask))
-+			return 0;
-+
-+		atomic_notifier_call_chain(&net->ct.nf_conntrack_chain, eventmask | missed, &item);
-+	}
-+
-+	return 0;
-+}
-+#else
- int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
- 				  u32 portid, int report)
- {
-@@ -171,10 +206,52 @@ int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
- 	rcu_read_unlock();
- 	return ret;
- }
-+#endif
- EXPORT_SYMBOL_GPL(nf_conntrack_eventmask_report);
- 
- /* deliver cached events and clear cache entry - must be called with locally
-  * disabled softirqs */
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+void nf_ct_deliver_cached_events(struct nf_conn *ct)
-+{
-+	unsigned long events, missed;
-+	struct nf_conntrack_ecache *e;
-+	struct nf_ct_event item;
-+	struct net *net = nf_ct_net(ct);
-+
-+	e = nf_ct_ecache_find(ct);
-+	if (e == NULL)
-+		return;
-+
-+	events = xchg(&e->cache, 0);
-+
-+	if (!nf_ct_is_confirmed(ct) || nf_ct_is_dying(ct) || !events)
-+		return;
-+
-+	/* We make a copy of the missed event cache without taking
-+	 * the lock, thus we may send missed events twice. However,
-+	 * this does not harm and it happens very rarely. */
-+	missed = e->missed;
-+
-+	if (!((events | missed) & e->ctmask))
-+		return;
-+
-+	item.ct = ct;
-+	item.portid = 0;
-+	item.report = 0;
-+
-+	atomic_notifier_call_chain(&net->ct.nf_conntrack_chain,
-+			events | missed,
-+			&item);
-+
-+	if (likely(!missed))
-+		return;
-+
-+	spin_lock_bh(&ct->lock);
-+		e->missed &= ~missed;
-+	spin_unlock_bh(&ct->lock);
-+}
-+#else
- void nf_ct_deliver_cached_events(struct nf_conn *ct)
- {
- 	struct net *net = nf_ct_net(ct);
-@@ -225,6 +302,7 @@ void nf_ct_deliver_cached_events(struct nf_conn *ct)
- out_unlock:
- 	rcu_read_unlock();
- }
-+#endif
- EXPORT_SYMBOL_GPL(nf_ct_deliver_cached_events);
- 
- void nf_ct_expect_event_report(enum ip_conntrack_expect_events event,
-@@ -257,6 +335,12 @@ void nf_ct_expect_event_report(enum ip_conntrack_expect_events event,
- 	rcu_read_unlock();
- }
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+int nf_conntrack_register_notifier(struct net *net, struct notifier_block *nb)
-+{
-+        return atomic_notifier_chain_register(&net->ct.nf_conntrack_chain, nb);
-+}
-+#else
- int nf_conntrack_register_notifier(struct net *net,
- 				   struct nf_ct_event_notifier *new)
- {
-@@ -277,8 +361,15 @@ int nf_conntrack_register_notifier(struct net *net,
- 	mutex_unlock(&nf_ct_ecache_mutex);
- 	return ret;
- }
-+#endif
- EXPORT_SYMBOL_GPL(nf_conntrack_register_notifier);
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb)
-+{
-+	return atomic_notifier_chain_unregister(&net->ct.nf_conntrack_chain, nb);
-+}
-+#else
- void nf_conntrack_unregister_notifier(struct net *net,
- 				      struct nf_ct_event_notifier *new)
- {
-@@ -291,6 +382,7 @@ void nf_conntrack_unregister_notifier(struct net *net,
- 	RCU_INIT_POINTER(net->ct.nf_conntrack_event_cb, NULL);
- 	mutex_unlock(&nf_ct_ecache_mutex);
- }
-+#endif
- EXPORT_SYMBOL_GPL(nf_conntrack_unregister_notifier);
- 
- int nf_ct_expect_register_notifier(struct net *net,
-diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c
-index 04111c1..8c741f7 100644
--- a/net/netfilter/nf_conntrack_netlink.c
-+++ b/net/netfilter/nf_conntrack_netlink.c
-@@ -28,6 +28,11 @@
- #include <linux/netlink.h>
- #include <linux/spinlock.h>
- #include <linux/interrupt.h>
-+
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+#include <linux/notifier.h>
-+#endif
-+
- #include <linux/slab.h>
- 
- #include <linux/netfilter.h>
-@@ -615,14 +620,22 @@ static size_t ctnetlink_nlmsg_size(const struct nf_conn *ct)
- 	       ;
- }
- 
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+static int ctnetlink_conntrack_event(struct notifier_block *this,
-+                           unsigned long events, void *ptr)
-+#else
- static int
- ctnetlink_conntrack_event(unsigned int events, struct nf_ct_event *item)
-+#endif
- {
- 	const struct nf_conntrack_zone *zone;
- 	struct net *net;
- 	struct nlmsghdr *nlh;
- 	struct nfgenmsg *nfmsg;
- 	struct nlattr *nest_parms;
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+	struct nf_ct_event *item = (struct nf_ct_event *)ptr;
-+#endif
- 	struct nf_conn *ct = item->ct;
- 	struct sk_buff *skb;
- 	unsigned int type;
-@@ -3260,9 +3273,15 @@ static int ctnetlink_stat_exp_cpu(struct net *net, struct sock *ctnl,
- }
- 
- #ifdef CONFIG_NF_CONNTRACK_EVENTS
-+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
-+static struct notifier_block ctnl_notifier = {
-+	.notifier_call = ctnetlink_conntrack_event,
-+};
-+#else
- static struct nf_ct_event_notifier ctnl_notifier = {
- 	.fcn = ctnetlink_conntrack_event,
- };
-+#endif
- 
- static struct nf_exp_event_notifier ctnl_notifier_exp = {
- 	.fcn = ctnetlink_expect_event,
-- 
-2.7.4
-
--- a/target/linux/generic/pending-4.14/601-add-kernel-imq-support.patch
+++ b/target/linux/generic/pending-4.14/601-add-kernel-imq-support.patch
--- a/target/linux/generic/pending-4.14/608-add-kernel-gargoyle-netfilter-match-modules.patch
+++ b/target/linux/generic/pending-4.14/608-add-kernel-gargoyle-netfilter-match-modules.patch
--- a/target/linux/generic/pending-4.14/760-net-usb-aqc111-Driver-skeleton-for-Aquantia-AQtionUSB-to-5GbE.patch
+++ b/target/linux/generic/pending-4.14/760-net-usb-aqc111-Driver-skeleton-for-Aquantia-AQtionUSB-to-5GbE.patch
--- a/target/linux/generic/pending-5.4/770-02-net-ethernet-mtk_eth_soc-fix-rx-vlan-offload.patch
+++ b/target/linux/generic/pending-5.4/770-02-net-ethernet-mtk_eth_soc-fix-rx-vlan-offload.patch
@@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 		skb_record_rx_queue(skb, 0);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -293,6 +293,7 @@
+@@ -295,6 +295,7 @@
 #define RX_DMA_LSO		BIT(30)
 #define RX_DMA_PLEN0(_x)	(((_x) & 0x3fff) << 16)
 #define RX_DMA_GET_PLEN0(_x)	(((_x) >> 16) & 0x3fff)
--- a/target/linux/generic/pending-5.4/770-04-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-q.patch
+++ b/target/linux/generic/pending-5.4/770-04-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-q.patch
@@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 			MTK_QDMA_GLO_CFG);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -195,7 +195,7 @@
+@@ -197,7 +197,7 @@
 #define MTK_RX_BT_32DWORDS	(3 << 11)
 #define MTK_NDP_CO_PRO		BIT(10)
 #define MTK_TX_WB_DDONE		BIT(6)
--- a/target/linux/generic/pending-5.4/770-06-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch
+++ b/target/linux/generic/pending-5.4/770-06-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch
@@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 	if (likely(napi_schedule_prep(&eth->tx_napi))) {
 		__napi_schedule(&eth->tx_napi);
 		mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
-@@ -2282,6 +2299,9 @@ static int mtk_stop(struct net_device *d
+@@ -2311,6 +2328,9 @@ static int mtk_stop(struct net_device *d
 	napi_disable(&eth->tx_napi);
 	napi_disable(&eth->rx_napi);
 
@@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
 		mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
 	mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
-@@ -2331,6 +2351,64 @@ err_disable_clks:
+@@ -2360,6 +2380,64 @@ err_disable_clks:
 	return ret;
 }
 
@@ -170,7 +170,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 static int mtk_hw_init(struct mtk_eth *eth)
 {
 	int i, val, ret;
-@@ -2352,9 +2430,6 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2381,9 +2459,6 @@ static int mtk_hw_init(struct mtk_eth *e
 			goto err_disable_pm;
 		}
 
@@ -180,7 +180,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 		/* disable delay and normal interrupt */
 		mtk_tx_irq_disable(eth, ~0);
 		mtk_rx_irq_disable(eth, ~0);
-@@ -2393,11 +2468,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2422,11 +2497,10 @@ static int mtk_hw_init(struct mtk_eth *e
 	/* Enable RX VLan Offloading */
 	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
 
@@ -193,8 +193,8 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 -	mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
 	mtk_tx_irq_disable(eth, ~0);
 	mtk_rx_irq_disable(eth, ~0);
- 	mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
-@@ -2916,6 +2990,13 @@ static int mtk_probe(struct platform_dev
+ 
+@@ -2930,6 +3004,13 @@ static int mtk_probe(struct platform_dev
 	spin_lock_init(&eth->page_lock);
 	spin_lock_init(&eth->tx_irq_lock);
 	spin_lock_init(&eth->rx_irq_lock);
@@ -218,7 +218,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 #define MTK_QDMA_PAGE_SIZE	2048
 #define	MTK_MAX_RX_LENGTH	1536
-@@ -129,13 +130,18 @@
+@@ -131,13 +132,18 @@
 
 /* PDMA Delay Interrupt Register */
 #define MTK_PDMA_DELAY_INT		0xa0c
@@ -242,7 +242,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 /* PDMA Interrupt Status Register */
 #define MTK_PDMA_INT_STATUS	0xa20
-@@ -217,6 +223,7 @@
+@@ -219,6 +225,7 @@
 /* QDMA Interrupt Status Register */
 #define MTK_QDMA_INT_STATUS	0x1A18
 #define MTK_RX_DONE_DLY		BIT(30)
@@ -250,7 +250,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 #define MTK_RX_DONE_INT3	BIT(19)
 #define MTK_RX_DONE_INT2	BIT(18)
 #define MTK_RX_DONE_INT1	BIT(17)
-@@ -226,8 +233,7 @@
+@@ -228,8 +235,7 @@
 #define MTK_TX_DONE_INT1	BIT(1)
 #define MTK_TX_DONE_INT0	BIT(0)
 #define MTK_RX_DONE_INT		MTK_RX_DONE_DLY
@@ -260,7 +260,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 /* QDMA Interrupt grouping registers */
 #define MTK_QDMA_INT_GRP1	0x1a20
-@@ -890,6 +896,18 @@ struct mtk_eth {
+@@ -892,6 +898,18 @@ struct mtk_eth {
 
 	const struct mtk_soc_data	*soc;
 
--- a/target/linux/generic/pending-5.4/770-08-net-ethernet-mtk_eth_soc-cache-hardware-pointer-of-l.patch
+++ b/target/linux/generic/pending-5.4/770-08-net-ethernet-mtk_eth_soc-cache-hardware-pointer-of-l.patch
@@ -49,7 +49,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 	} else {
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -622,6 +622,7 @@ struct mtk_tx_buf {
+@@ -624,6 +624,7 @@ struct mtk_tx_buf {
  * @phys:		The physical addr of tx_buf
  * @next_free:		Pointer to the next free descriptor
  * @last_free:		Pointer to the last free descriptor
@@ -57,7 +57,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  * @thresh:		The threshold of minimum amount of free descriptors
  * @free_count:		QDMA uses a linked list. Track how many free descriptors
  *			are present
-@@ -632,6 +633,7 @@ struct mtk_tx_ring {
+@@ -634,6 +635,7 @@ struct mtk_tx_ring {
 	dma_addr_t phys;
 	struct mtk_tx_dma *next_free;
 	struct mtk_tx_dma *last_free;
--- a/target/linux/generic/pending-5.4/770-13-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch
+++ b/target/linux/generic/pending-5.4/770-13-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch
@@ -0,0 +1,75 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 13 Sep 2020 08:17:02 +0200
+Subject: [PATCH] net: ethernet: mtk_eth_soc: fix parsing packets in GDM
+
+When using DSA, set the special tag in GDM ingress control to allow the MAC
+to parse packets properly earlier. This affects rx DMA source port reporting.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -19,6 +19,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/pinctrl/devinfo.h>
+ #include <linux/phylink.h>
+#include <net/dsa.h>
+ 
+ #include "mtk_eth_soc.h"
+ 
+@@ -1240,12 +1241,14 @@ static int mtk_poll_rx(struct napi_struc
+ 	u8 *data, *new_data;
+ 	struct mtk_rx_dma *rxd, trxd;
+ 	int done = 0, bytes = 0;
+	bool uses_dsa = eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]);
+ 
+ 	while (done < budget) {
+ 		struct net_device *netdev;
+ 		unsigned int pktlen;
+ 		dma_addr_t dma_addr;
+ 		int mac;
+		u16 hash;
+ 
+ 		ring = mtk_get_rx_ring(eth);
+ 		if (unlikely(!ring))
+@@ -1259,13 +1262,13 @@ static int mtk_poll_rx(struct napi_struc
+ 			break;
+ 
+ 		/* find out which mac the packet come from. values start at 1 */
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ 			mac = 0;
+-		} else {
+-			mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
+-				RX_DMA_FPORT_MASK;
+-			mac--;
+-		}
+		else if (uses_dsa)
+			mac = !(trxd.rxd4 >> 22);
+		else
+			mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
+			       RX_DMA_FPORT_MASK) - 1;
+ 
+ 		if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
+ 			     !eth->netdev[mac]))
+@@ -2247,6 +2250,9 @@ static void mtk_gdm_config(struct mtk_et
+ 
+ 		val |= config;
+ 
+		if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]))
+			val |= MTK_GDMA_SPECIAL_TAG;
+
+ 		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
+ 	}
+ 	/* Reset and enable PSE */
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -82,6 +82,7 @@
+ 
+ /* GDM Exgress Control Register */
+ #define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
+#define MTK_GDMA_SPECIAL_TAG	BIT(24)
+ #define MTK_GDMA_ICS_EN		BIT(22)
+ #define MTK_GDMA_TCS_EN		BIT(21)
+ #define MTK_GDMA_UCS_EN		BIT(20)
--- a/target/linux/generic/pending-5.4/770-14-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch
+++ b/target/linux/generic/pending-5.4/770-14-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch
@@ -0,0 +1,23 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 13 Sep 2020 08:27:24 +0200
+Subject: [PATCH] net: ethernet: mtk_eth_soc: set PPE flow hash as skb hash
+ if present
+
+This improves GRO performance
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1318,6 +1318,10 @@ static int mtk_poll_rx(struct napi_struc
+ 		skb->protocol = eth_type_trans(skb, netdev);
+ 		bytes += pktlen;
+ 
+		hash = trxd.rxd4 & GENMASK(13, 0);
+		if (hash != GENMASK(13, 0))
+			skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
+
+ 		if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
+ 		    (trxd.rxd2 & RX_DMA_VTAG))
+ 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
--- a/target/linux/mediatek/patches-5.4/0999-hnat.patch
+++ b/target/linux/mediatek/patches-5.4/0999-hnat.patch
@@ -144,10 +144,10 @@
 #include <linux/phylink.h>
 +#include <linux/netfilter.h>
 +#include <net/netfilter/nf_flow_table.h>
+ #include <net/dsa.h>
 
 #include "mtk_eth_soc.h"
- 
-@@ -1320,8 +1322,16 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1327,8 +1329,16 @@ static int mtk_poll_rx(struct napi_struc
 		    (trxd.rxd2 & RX_DMA_VTAG))
 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 					       RX_DMA_VID(trxd.rxd3));
@@ -166,7 +166,7 @@
 
 skip_rx:
 		ring->data[idx] = new_data;
-@@ -2255,6 +2265,9 @@ static int mtk_open(struct net_device *d
+@@ -2292,6 +2302,9 @@ static int mtk_open(struct net_device *d
 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
 		mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
 		refcount_set(&eth->dma_refcnt, 1);
@@ -176,7 +176,7 @@
 	}
 	else
 		refcount_inc(&eth->dma_refcnt);
-@@ -2316,6 +2329,9 @@ static int mtk_stop(struct net_device *d
+@@ -2355,6 +2368,9 @@ static int mtk_stop(struct net_device *d
 
 	mtk_dma_free(eth);
 
@@ -186,7 +186,7 @@
 	return 0;
 }
 
-@@ -2829,6 +2845,27 @@ static int mtk_set_rxnfc(struct net_devi
+@@ -2853,6 +2869,27 @@ static int mtk_set_rxnfc(struct net_devi
 	return ret;
 }
 
@@ -214,7 +214,7 @@
 static const struct ethtool_ops mtk_ethtool_ops = {
 	.get_link_ksettings	= mtk_get_link_ksettings,
 	.set_link_ksettings	= mtk_set_link_ksettings,
-@@ -2860,6 +2897,9 @@ static const struct net_device_ops mtk_n
+@@ -2884,6 +2921,9 @@ static const struct net_device_ops mtk_n
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	.ndo_poll_controller	= mtk_poll_controller,
 #endif
@@ -224,7 +224,7 @@
 };
 
 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
-@@ -3202,6 +3242,7 @@ static const struct mtk_soc_data mt7622_
+@@ -3226,6 +3266,7 @@ static const struct mtk_soc_data mt7622_
 	.hw_features = MTK_HW_FEATURES,
 	.required_clks = MT7622_CLKS_BITMAP,
 	.required_pctl = false,
@@ -234,7 +234,7 @@
 static const struct mtk_soc_data mt7623_data = {
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -787,6 +787,13 @@ enum mkt_eth_capabilities {
+@@ -790,6 +790,13 @@ enum mkt_eth_capabilities {
 		      MTK_MUX_U3_GMAC2_TO_QPHY | \
 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
 
@@ -248,7 +248,7 @@
 /* struct mtk_eth_data -	This is the structure holding all differences
  *				among various plaforms
  * @ana_rgc3:                   The offset for register ANA_RGC3 related to
-@@ -804,6 +811,7 @@ struct mtk_soc_data {
+@@ -807,6 +814,7 @@ struct mtk_soc_data {
 	u32		required_clks;
 	bool		required_pctl;
 	netdev_features_t hw_features;
@@ -256,7 +256,7 @@
 };
 
 /* currently no SoC has more than 2 macs */
-@@ -829,6 +837,23 @@ struct mtk_sgmii {
+@@ -832,6 +840,23 @@ struct mtk_sgmii {
 	u32             ana_rgc3;
 };
 
@@ -280,7 +280,7 @@
 /* struct mtk_eth -	This is the main datasructure for holding the state
  *			of the driver
  * @dev:		The device pointer
-@@ -914,6 +939,16 @@ struct mtk_eth {
+@@ -917,6 +942,16 @@ struct mtk_eth {
 	u32				tx_int_status_reg;
 	u32				rx_dma_l4_valid;
 	int				ip_align;
@@ -297,7 +297,7 @@
 };
 
 /* struct mtk_mac -	the structure that holds the info about the MACs of the
-@@ -946,6 +981,7 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -949,6 +984,7 @@ void mtk_stats_update_mac(struct mtk_mac
 
 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
@@ -305,7 +305,7 @@
 
 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
 		   u32 ana_rgc3);
-@@ -958,4 +994,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk
+@@ -961,4 +997,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk
 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
 
--- a/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch
+++ b/target/linux/mediatek/patches-5.4/1011-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch
@@ -37,7 +37,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/clk.h>
-@@ -2476,6 +2477,12 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2486,6 +2487,12 @@ static int mtk_hw_init(struct mtk_eth *e
 	if (ret)
 		goto err_disable_pm;
 
@@ -50,7 +50,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
 		ret = device_reset(eth->dev);
 		if (ret) {
-@@ -3078,6 +3085,16 @@ static int mtk_probe(struct platform_dev
+@@ -3088,6 +3095,16 @@ static int mtk_probe(struct platform_dev
 		}
 	}
 
@@ -69,7 +69,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 					  GFP_KERNEL);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -425,6 +425,11 @@
+@@ -426,6 +426,11 @@
 #define RSTCTRL_FE		BIT(6)
 #define RSTCTRL_PPE		BIT(31)
 
--- a/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts
+++ b/target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts
@@ -109,7 +109,8 @@
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <10000000>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
 		broken-flash-reset;

 		partitions {
@@ -138,14 +139,26 @@
 			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
-				reg = <0x50000 0xfb0000>;
+				reg = <0x50000 0x1fb0000>;
 			};
 		};
 	};
 };

+&pinctrl {
+	uart3_gpio: uart3-gpio {
+		uart3 {
+			groups = "uart3";
+			function = "gpio";
+		};
+	};
+};
+
 &pcie {
 	status = "okay";
+	pinctrl-0 = <&pcie_pins>, <&uart3_gpio>;
+	reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
+		      <&gpio 7 GPIO_ACTIVE_LOW>;
 };

 &pcie0 {
--- a/target/linux/ramips/image/mt7621.mk
+++ b/target/linux/ramips/image/mt7621.mk
@@ -333,7 +333,7 @@ TARGET_DEVICES += d-team_newifi-d2

 define Device/d-team_pbr-m1
  $(Device/dsa-migration)
-  IMAGE_SIZE := 16064k
+  IMAGE_SIZE := 32448k
  DEVICE_VENDOR := PandoraBox
  DEVICE_MODEL := PBR-M1
  DEVICE_PACKAGES := kmod-ata-ahci kmod-mt7603 kmod-mt76x2 kmod-sdhci-mt7620 \
--- a/target/linux/rtl838x/Makefile
+++ b/target/linux/rtl838x/Makefile
@@ -0,0 +1,22 @@
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+
+ARCH:=mips
+CPU_TYPE:=4kec
+BOARD:=rtl838x
+BOARDNAME:=Realtek MIPS
+FEATURES:=ramdisk squashfs
+
+KERNEL_PATCHVER:=5.4
+
+define Target/Description
+	Build firmware images for Realtek RTL838x based boards.
+endef
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += swconfig uboot-envtools ethtool kmod-gpio-button-hotplug
+
+$(eval $(call BuildTarget))
--- a/target/linux/rtl838x/base-files/etc/board.d/01_leds
+++ b/target/linux/rtl838x/base-files/etc/board.d/01_leds
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+. /lib/functions/uci-defaults.sh
+
+board=$(board_name)
+boardname="${board##*,}"
+
+board_config_update
+
+case $board in
+esac
+
+board_config_flush
+
+exit 0
--- a/target/linux/rtl838x/base-files/etc/board.d/02_network
+++ b/target/linux/rtl838x/base-files/etc/board.d/02_network
@@ -0,0 +1,87 @@
+#!/bin/sh
+
+. /lib/functions.sh
+. /lib/functions/uci-defaults.sh
+. /lib/functions/system.sh
+
+rtl838x_setup_switch()
+{
+	local switchid net portid master device lan_role lan_list
+
+	json_select_object switch
+	# Find slave ports
+	for net in $(ls -d /sys/class/net/*); do
+		switchid=$(cat $net/phys_switch_id 2>/dev/null)
+		[ -z "$switchid" ] && continue
+		device=$(basename $net)
+		portid=$(cat $net/phys_port_name)
+		lan_role="$lan_role ${portid##p}"
+		lan_list="$lan_list $device"
+		json_select_object "switch$((switchid))"
+			json_add_boolean enable 1
+			json_add_boolean reset 0
+			json_add_boolean dsa 1
+			json_select_array ports
+				json_add_object
+					json_add_int num "${portid##p}"
+					json_add_string role "lan"
+					json_add_string device "$device"
+				json_close_object
+			json_select ..
+		json_select ..
+	done
+	# Add switch master device
+	for net in $(ls -d /sys/class/net/*/dsa); do
+		master=$(dirname $net)
+		device=$(basename $master)
+		portid=$(cat $master/phys_port_name)
+		lan_role="$lan_role ${portid##p}"
+		json_select_object "switch$((switchid))"
+			json_select_array ports
+				json_add_object
+					json_add_int num "${portid##p}"
+					json_add_string device "$device"
+					json_add_boolean need_tag 0
+					json_add_boolean want_untag 0
+					json_add_boolean master 1
+				json_close_object
+			json_select ..
+			json_select_array roles
+				json_add_object
+					json_add_string role "lan"
+					lan_role=$(echo $lan_role | xargs -n1 | sort -n | xargs)
+					json_add_string ports "$lan_role"
+				json_close_object
+			json_select ..
+		json_select ..
+	done
+	json_select ..
+	lan_list=$(echo $lan_list | xargs -n1 | sort -V | xargs)
+	ucidef_set_interface_lan "$lan_list"
+}
+
+rtl838x_setup_macs()
+{
+	local board="$1"
+	local lan_mac
+	local wan_mac
+	local label_mac
+
+	case $board in
+	allnet,all-sg8208m)
+		lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)
+		label_mac=$lan_mac
+	esac
+
+	[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
+	[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
+	[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
+}
+
+board_config_update
+board=$(board_name)
+rtl838x_setup_switch
+rtl838x_setup_macs $board
+board_config_flush
+
+exit 0
--- a/target/linux/rtl838x/base-files/etc/inittab
+++ b/target/linux/rtl838x/base-files/etc/inittab
@@ -0,0 +1,3 @@
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+::askconsole:/usr/libexec/login.sh
--- a/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw
+++ b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw
--- a/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8218b.fw
+++ b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8218b.fw
--- a/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8380.fw
+++ b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8380.fw
--- a/target/linux/rtl838x/base-files/lib/upgrade/platform.sh
+++ b/target/linux/rtl838x/base-files/lib/upgrade/platform.sh
@@ -0,0 +1,19 @@
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+RAMFS_COPY_BIN='fw_printenv fw_setenv'
+RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
+
+platform_check_image() {
+	return 0
+}
+
+platform_do_upgrade() {
+	local board=$(board_name)
+
+	case "$board" in
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}
--- a/target/linux/rtl838x/config-5.4
+++ b/target/linux/rtl838x/config-5.4
@@ -0,0 +1,226 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_BOSTON is not set
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_LOAD_STORE_LR=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EFI_EARLYCON=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+# CONFIG_FIXED_PHY is not set
+# CONFIG_FONT_SUPPORT is not set
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_ARCH_COMPILER_H=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_COPY_THREAD_TLS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FAST_GUP=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+# CONFIG_MIPS_VPE_LOADER is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
+CONFIG_MTD_SPLIT_EVA_FW=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_RTL838X=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_RTL838X=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+# CONFIG_PHYLIB is not set
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PSB6970_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RTL838X=y
+CONFIG_GPIO_RTL838X=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_RTL838X=y
+CONFIG_SRCU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_VPE_LOADER=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USE_OF=y
+CONFIG_JFFS2_ZLIB=y
--- a/target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts
+++ b/target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
+	model = "ALLNET ALL-SG8208M";
+
+	aliases {
+		led-boot = &led_sys;
+		led-failsafe = &led_sys;
+		led-running = &led_sys;
+		led-upgrade = &led_sys;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <20>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_sys: sys {
+			label = "all-sg8208m:green:sys";
+			gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
+		};
+		// GPIO 25: power on/off all port leds
+	};
+};
+
+&gpio0 {
+	indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x80000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "u-boot-env";
+				reg = <0x80000 0x10000>;
+				read-only;
+			};
+
+			partition@90000 {
+				label = "u-boot-env2";
+				reg = <0x90000 0x10000>;
+				read-only;
+			};
+
+			partition@a0000 {
+				label = "jffs";
+				reg = <0xa0000 0x100000>;
+			};
+
+			partition@1a0000 {
+				label = "jffs2";
+				reg = <0x1a0000 0x100000>;
+			};
+
+			partition@2a0000 {
+				label = "firmware";
+				reg = <0x2a0000 0xd60000>;
+				compatible = "allnet,uimage";
+			};
+		};
+	};
+};
+
+&ethernet0 {
+	mdio: mdio-bus {
+		compatible = "realtek,rtl838x-mdio";
+		regmap = <&ethernet0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Internal phy */
+		phy8: ethernet-phy@8 {
+			reg = <8>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy9: ethernet-phy@9 {
+			reg = <9>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy10: ethernet-phy@10 {
+			reg = <10>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy11: ethernet-phy@11 {
+			reg = <11>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy12: ethernet-phy@12 {
+			reg = <12>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy13: ethernet-phy@13 {
+			reg = <13>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy14: ethernet-phy@14 {
+			reg = <14>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy15: ethernet-phy@15 {
+			reg = <15>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+	};
+};
+
+&switch0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <8>;
+			label = "lan1";
+			phy-handle = <&phy8>;
+			phy-mode = "internal";
+		};
+
+		port@1 {
+			reg = <9>;
+			label = "lan2";
+			phy-handle = <&phy9>;
+			phy-mode = "internal";
+		};
+
+		port@2 {
+			reg = <10>;
+			label = "lan3";
+			phy-handle = <&phy10>;
+			phy-mode = "internal";
+		};
+
+		port@3 {
+			reg = <11>;
+			label = "lan4";
+			phy-handle = <&phy11>;
+			phy-mode = "internal";
+		};
+
+		port@4 {
+			reg = <12>;
+			label = "lan5";
+			phy-handle = <&phy12>;
+			phy-mode = "internal";
+		};
+
+		port@5 {
+			reg = <13>;
+			label = "lan6";
+			phy-handle = <&phy13>;
+			phy-mode = "internal";
+		};
+
+		port@6 {
+			reg = <14>;
+			label = "lan7";
+			phy-handle = <&phy14>;
+			phy-mode = "internal";
+		};
+
+		port@7 {
+			reg = <15>;
+			label = "lan8";
+			phy-handle = <&phy15>;
+			phy-mode = "internal";
+		};
+
+		port@28 {
+			ethernet = <&ethernet0>;
+			reg = <28>;
+			phy-mode = "internal";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
--- a/target/linux/rtl838x/dts/rtl838x.dtsi
+++ b/target/linux/rtl838x/dts/rtl838x.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	compatible = "realtek,rtl838x-soc";
+	reg = <0xbb000000 0xa000>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		frequency = <500000000>;
+
+		cpu@0 {
+			compatible = "mips,mips4KEc";
+			reg = <0>;
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,38400";
+	};
+
+	cpuintc: cpuintc {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "rtl838x,icu";
+		reg = <0xb8003000 0x20>;
+	};
+
+	spi0: spi@b8001200 {
+		status = "okay";
+
+		compatible = "realtek,rtl838x-nor";
+		reg = <0xb8001200 0x100>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	uart0: uart@b8002000 {
+		status = "disabled";
+
+		compatible = "ns16550a";
+		reg = <0xb8002000 0x100>;
+
+		clock-frequency = <200000000>;
+		interrupts = <31>;
+
+		reg-io-width = <1>;
+		reg-shift = <2>;
+		fifo-size = <1>;
+		no-loopback-test;
+	};
+
+	uart1: uart@b8002100 {
+		status = "okay";
+
+		compatible = "ns16550a";
+		reg = <0xb8002100 0x100>;
+
+		clock-frequency = <200000000>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <30>;
+
+		reg-io-width = <1>;
+		reg-shift = <2>;
+		fifo-size = <1>;
+		no-loopback-test;
+	};
+
+	gpio0: gpio-controller@b8003500 {
+		compatible = "realtek,rtl838x-gpio";
+		reg = <0xb8003500 0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <23>;
+	};
+
+	ethernet0: ethernet@bb00a300 {
+		status = "okay";
+
+		compatible = "realtek,rtl838x-eth";
+		reg = <0xbb00a300 0x100>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <24>;
+		#interrupt-cells = <1>;
+		phy-mode = "internal";
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+		};
+	};
+
+	switch0: switch@bb000000 {
+		status = "okay";
+
+		compatible = "realtek,rtl838x-switch";
+	};
+};
--- a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h
+++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef RTL838X_IOREMAP_H_
+#define RTL838X_IOREMAP_H_
+
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
+{
+	return phys_addr;
+}
+
+static inline int is_rtl838x_internal_registers(phys_addr_t offset)
+{
+	/* IO-Block */
+	if (offset >= 0xb8000000 && offset < 0xb9000000)
+		return 1;
+	/* Switch block */
+	if (offset >= 0xbb000000 && offset < 0xbc000000)
+		return 1;
+	return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+					 unsigned long flags)
+{
+	if (is_rtl838x_internal_registers(offset))
+		return (void __iomem *)offset;
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return is_rtl838x_internal_registers((unsigned long)addr);
+}
+
+#endif
--- a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h
+++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_MACH_RTL838X_IRQ_H
+#define __ASM_MACH_RTL838X_IRQ_H
+
+#define MIPS_CPU_IRQ_BASE	0
+#define NR_IRQS			64
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_ATH79_IRQ_H */
--- a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h
+++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h
@@ -0,0 +1,428 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ */
+#ifndef _MACH_RTL838X_H_
+#define _MACH_RTL838X_H_
+
+/*
+ * Register access macros
+ */
+
+#define RTL838X_SW_BASE		((volatile void *) 0xBB000000)
+
+#define rtl838x_r32(reg)	__raw_readl(reg)
+#define rtl838x_w32(val, reg)	__raw_writel(val, reg)
+#define rtl838x_w32_mask(clear, set, reg) rtl838x_w32((rtl838x_r32(reg) & ~(clear)) | (set), reg)
+
+#define sw_r32(reg)		__raw_readl(RTL838X_SW_BASE + reg)
+#define sw_w32(val, reg)	__raw_writel(val, RTL838X_SW_BASE + reg)
+#define sw_w32_mask(clear, set, reg)	\
+				sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
+
+#define sw_r64(reg)		((((u64)__raw_readl(RTL838X_SW_BASE + reg)) << 32) | \
+				__raw_readl(RTL838X_SW_BASE + reg + 4))
+
+#define sw_w64(val, reg)	do { \
+					__raw_writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
+					__raw_writel((u32)((val) & 0xffffffff), \
+							RTL838X_SW_BASE + reg + 4); \
+				} while (0)
+
+/*
+ * SPRAM
+ */
+#define RTL838X_ISPRAM_BASE	0x0
+#define RTL838X_DSPRAM_BASE	0x0
+
+/*
+ * IRQ Controller
+ */
+#define RTL838X_IRQ_CPU_BASE	0
+#define RTL838X_IRQ_CPU_NUM	8
+#define RTL838X_IRQ_ICTL_BASE	(RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
+#define RTL838X_IRQ_ICTL_NUM	32
+
+/*
+ * MIPS32R2 counter
+ */
+#define RTL838X_COMPARE_IRQ	(RTL838X_IRQ_CPU_BASE + 7)
+
+/*
+ *  ICTL
+ *  Base address 0xb8003000UL
+ */
+#define RTL838X_ICTL1_IRQ	(RTL838X_IRQ_CPU_BASE + 2)
+#define RTL838X_ICTL2_IRQ	(RTL838X_IRQ_CPU_BASE + 3)
+#define RTL838X_ICTL3_IRQ	(RTL838X_IRQ_CPU_BASE + 4)
+#define RTL838X_ICTL4_IRQ	(RTL838X_IRQ_CPU_BASE + 5)
+#define RTL838X_ICTL5_IRQ	(RTL838X_IRQ_CPU_BASE + 6)
+
+#define GIMR			(0x00)
+#define UART0_IE		(1 << 31)
+#define UART1_IE		(1 << 30)
+#define TC0_IE			(1 << 29)
+#define TC1_IE			(1 << 28)
+#define OCPTO_IE		(1 << 27)
+#define HLXTO_IE		(1 << 26)
+#define SLXTO_IE		(1 << 25)
+#define NIC_IE			(1 << 24)
+#define GPIO_ABCD_IE		(1 << 23)
+#define GPIO_EFGH_IE		(1 << 22)
+#define RTC_IE			(1 << 21)
+#define WDT_IP1_IE		(1 << 19)
+#define WDT_IP2_IE		(1 << 18)
+
+#define GISR			(0x04)
+#define UART0_IP		(1 << 31)
+#define UART1_IP		(1 << 30)
+#define TC0_IP			(1 << 29)
+#define TC1_IP			(1 << 28)
+#define OCPTO_IP		(1 << 27)
+#define HLXTO_IP		(1 << 26)
+#define SLXTO_IP		(1 << 25)
+#define NIC_IP			(1 << 24)
+#define GPIO_ABCD_IP		(1 << 23)
+#define GPIO_EFGH_IP		(1 << 22)
+#define RTC_IP			(1 << 21)
+#define WDT_IP1_IP		(1 << 19)
+#define WDT_IP2_IP		(1 << 18)
+
+#define IRR0			(0x08)
+#define IRR0_SETTING		((UART0_RS  << 28) | \
+				 (UART1_RS  << 24) | \
+				 (TC0_RS    << 20) | \
+				 (TC1_RS    << 16) | \
+				 (OCPTO_RS  << 12) | \
+				 (HLXTO_RS  << 8)  | \
+				 (SLXTO_RS  << 4)  | \
+				 (NIC_RS    << 0)    \
+				)
+
+#define IRR1			(0x0c)
+
+#define IRR1_SETTING		((GPIO_ABCD_RS << 28) | \
+				 (GPIO_EFGH_RS << 24) | \
+				 (RTC_RS       << 20) | \
+				 (SWCORE_RS    << 16)   \
+				)
+
+#define IRR2			(0x10)
+#define IRR2_SETTING		0
+
+#define IRR3			(0x14)
+#define IRR3_SETTING		0
+
+/* Interrupt Routing Selection */
+#define UART0_RS		2
+#define UART1_RS		1
+#define TC0_RS			5
+#define TC1_RS			1
+#define OCPTO_RS		1
+#define HLXTO_RS		1
+#define SLXTO_RS		1
+#define NIC_RS			4
+#define GPIO_ABCD_RS		4
+#define GPIO_EFGH_RS		4
+#define RTC_RS			4
+#define	SWCORE_RS		3
+#define WDT_IP1_RS		4
+#define WDT_IP2_RS		5
+
+/* Interrupt IRQ Assignments */
+#define UART0_IRQ		31
+#define UART1_IRQ		30
+#define TC0_IRQ			29
+#define TC1_IRQ			28
+#define OCPTO_IRQ		27
+#define HLXTO_IRQ		26
+#define SLXTO_IRQ		25
+#define NIC_IRQ			24
+#define GPIO_ABCD_IRQ		23
+#define GPIO_EFGH_IRQ		22
+#define RTC_IRQ			21
+#define	SWCORE_IRQ		20
+#define WDT_IP1_IRQ		19
+#define WDT_IP2_IRQ		18
+
+#define SYSTEM_FREQ		200000000
+#define RTL838X_UART0_BASE	((volatile void *)(0xb8002000UL))
+#define RTL838X_UART0_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
+#define RTL838X_UART0_FREQ	(SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
+#define RTL838X_UART0_MAPBASE	0x18002000UL
+#define RTL838X_UART0_MAPSIZE	0x100
+#define RTL838X_UART0_IRQ	UART0_IRQ
+
+#define RTL838X_UART1_BASE	((volatile void *)(0xb8002100UL))
+#define RTL838X_UART1_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
+#define RTL838X_UART1_FREQ	(SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
+#define RTL838X_UART1_MAPBASE	0x18002100UL
+#define RTL838X_UART1_MAPSIZE	0x100
+#define RTL838X_UART1_IRQ	UART1_IRQ
+
+#define UART0_RBR		(RTL838X_UART0_BASE + 0x000)
+#define UART0_THR		(RTL838X_UART0_BASE + 0x000)
+#define UART0_DLL		(RTL838X_UART0_BASE + 0x000)
+#define UART0_IER		(RTL838X_UART0_BASE + 0x004)
+#define UART0_DLM		(RTL838X_UART0_BASE + 0x004)
+#define UART0_IIR		(RTL838X_UART0_BASE + 0x008)
+#define UART0_FCR		(RTL838X_UART0_BASE + 0x008)
+#define UART0_LCR		(RTL838X_UART0_BASE + 0x00C)
+#define UART0_MCR		(RTL838X_UART0_BASE + 0x010)
+#define UART0_LSR		(RTL838X_UART0_BASE + 0x014)
+
+#define UART1_RBR		(RTL838X_UART1_BASE + 0x000)
+#define UART1_THR		(RTL838X_UART1_BASE + 0x000)
+#define UART1_DLL		(RTL838X_UART1_BASE + 0x000)
+#define UART1_IER		(RTL838X_UART1_BASE + 0x004)
+#define UART1_DLM		(RTL838X_UART1_BASE + 0x004)
+#define UART1_IIR		(RTL838X_UART1_BASE + 0x008)
+#define UART1_FCR		(RTL838X_UART1_BASE + 0x008)
+   #define FCR_EN		0x01
+   #define FCR_RXRST		0x02
+   #define XRST			0x02
+   #define FCR_TXRST		0x04
+   #define TXRST		0x04
+   #define FCR_DMA		0x08
+   #define FCR_RTRG		0xC0
+   #define CHAR_TRIGGER_01	0x00
+   #define CHAR_TRIGGER_04	0x40
+   #define CHAR_TRIGGER_08	0x80
+   #define CHAR_TRIGGER_14	0xC0
+#define UART1_LCR		(RTL838X_UART1_BASE + 0x00C)
+   #define LCR_WLN		0x03
+   #define CHAR_LEN_5		0x00
+   #define CHAR_LEN_6		0x01
+   #define CHAR_LEN_7		0x02
+   #define CHAR_LEN_8		0x03
+   #define LCR_STB		0x04
+   #define ONE_STOP		0x00
+   #define TWO_STOP		0x04
+   #define LCR_PEN		0x08
+   #define PARITY_ENABLE	0x01
+   #define PARITY_DISABLE	0x00
+   #define LCR_EPS		0x30
+   #define PARITY_ODD		0x00
+   #define PARITY_EVEN		0x10
+   #define PARITY_MARK		0x20
+   #define PARITY_SPACE		0x30
+   #define LCR_BRK		0x40
+   #define LCR_DLAB		0x80
+   #define DLAB			0x80
+#define UART1_MCR		(RTL838X_UART1_BASE + 0x010)
+#define UART1_LSR		(RTL838X_UART1_BASE + 0x014)
+   #define LSR_DR		0x01
+   #define RxCHAR_AVAIL		0x01
+   #define LSR_OE		0x02
+   #define LSR_PE		0x04
+   #define LSR_FE		0x08
+   #define LSR_BI		0x10
+   #define LSR_THRE		0x20
+   #define TxCHAR_AVAIL		0x00
+   #define TxCHAR_EMPTY		0x20
+   #define LSR_TEMT		0x40
+   #define LSR_RFE		0x80
+
+/*
+ *  Timer/counter for 8390/80/28 TC & MP chip
+ */
+#define RTL838X_TIMER0_BASE	((volatile void *)(0xb8003100UL))
+#define RTL838X_TIMER0_IRQ	RTL838X_TC0_EXT_IRQ
+
+#define RTL8390TC_TC1DATA	(RTL838X_TIMER0_BASE + 0x04)
+#define RTL8390TC_TCD_OFFSET	8
+#define RTL8390TC_TC0CNT	(RTL838X_TIMER0_BASE + 0x08)
+#define RTL8390TC_TC1CNT	(RTL838X_TIMER0_BASE + 0x0C)
+#define RTL8390TC_TCCNR		(RTL838X_TIMER0_BASE + 0x10)
+#define RTL8390TC_TC0EN		(1 << 31)
+#define RTL8390TC_TC0MODE_TIMER	(1 << 30)
+#define RTL8390TC_TC1EN		(1 << 29)
+#define RTL8390TC_TC1MODE_TIMER	(1 << 28)
+#define RTL8390TC_TCIR		(RTL838X_TIMER0_BASE + 0x14)
+#define RTL8390TC_TC0IE		(1 << 31)
+#define RTL8390TC_TC1IE		(1 << 30)
+#define RTL8390TC_TC0IP		(1 << 29)
+#define RTL8390TC_TC1IP		(1 << 28)
+#define RTL8390TC_CDBR		(RTL838X_TIMER0_BASE + 0x18)
+#define RTL8390TC_DIVF_OFFSET	16
+#define RTL8390TC_WDTCNR	(RTL838X_TIMER0_BASE + 0x1C)
+
+#define RTL8390MP_TC1DATA	(RTL838X_TIMER0_BASE + 0x10)
+#define RTL8390MP_TC0CNT	(RTL838X_TIMER0_BASE + 0x04)
+#define RTL8390MP_TC1CNT	(RTL838X_TIMER0_BASE + 0x14)
+#define RTL8390MP_TC0CTL	(RTL838X_TIMER0_BASE + 0x08)
+#define RTL8390MP_TC1CTL	(RTL838X_TIMER0_BASE + 0x18)
+#define RTL8390MP_TCEN		(1 << 28)
+#define RTL8390MP_TCMODE_TIMER	(1 << 24)
+#define RTL8390MP_TCDIV_FACTOR	(0xFFFF << 0)
+#define RTL8390MP_TC0INT	(RTL838X_TIMER0_BASE + 0xC)
+#define RTL8390MP_TC1INT	(RTL838X_TIMER0_BASE + 0x1C)
+#define RTL8390MP_TCIE		(1 << 20)
+#define RTL8390MP_TCIP		(1 << 16)
+#define RTL8390MP_WDTCNR	(RTL838X_TIMER0_BASE + 0x50)
+
+#define RTL8380MP_TC0DATA	(RTL838X_TIMER0_BASE + 0x00)
+#define RTL8380MP_TC1DATA	(RTL838X_TIMER0_BASE + 0x10)
+#define RTL8380MP_TC0CNT	(RTL838X_TIMER0_BASE + 0x04)
+#define RTL8380MP_TC1CNT	(RTL838X_TIMER0_BASE + 0x14)
+#define RTL8380MP_TC0CTL	(RTL838X_TIMER0_BASE + 0x08)
+#define RTL8380MP_TC1CTL	(RTL838X_TIMER0_BASE + 0x18)
+#define RTL8380MP_TCEN		(1 << 28)
+#define RTL8380MP_TCMODE_TIMER	(1 << 24)
+#define RTL8380MP_TCDIV_FACTOR	(0xFFFF << 0)
+#define RTL8380MP_TC0INT	(RTL838X_TIMER0_BASE + 0xC)
+#define RTL8380MP_TC1INT	(RTL838X_TIMER0_BASE + 0x1C)
+#define RTL8380MP_TCIE		(1 << 20)
+#define RTL8380MP_TCIP		(1 << 16)
+#define RTL8380MP_WDTCNR	(RTL838X_TIMER0_BASE + 0x50)
+
+#define DIVISOR_RTL8390		55
+#define DIVISOR_RTL8380		2500
+#define DIVISOR_MAX		16834
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR			0xB8001000
+#define MC_MCR_VAL		0x00000000
+
+#define MC_DCR			0xB8001004
+#define MC_DCR0_VAL		0x54480000
+
+#define MC_DTCR			0xB8001008
+#define MC_DTCR_VAL		0xFFFF05C0
+
+/*
+ * GPIO
+ */
+#define GPIO_CTRL_REG_BASE		((volatile void *) 0xb8003500)
+#define RTL838X_GPIO_PABC_CNR		(GPIO_CTRL_REG_BASE + 0x0)
+#define RTL838X_GPIO_PABC_TYPE		(GPIO_CTRL_REG_BASE + 0x04)
+#define RTL838X_GPIO_PABC_DIR		(GPIO_CTRL_REG_BASE + 0x8)
+#define RTL838X_GPIO_PABC_DATA		(GPIO_CTRL_REG_BASE + 0xc)
+#define RTL838X_GPIO_PABC_ISR		(GPIO_CTRL_REG_BASE + 0x10)
+#define RTL838X_GPIO_PAB_IMR		(GPIO_CTRL_REG_BASE + 0x14)
+#define RTL838X_GPIO_PC_IMR		(GPIO_CTRL_REG_BASE + 0x18)
+
+#define RTL838X_MODEL_NAME_INFO		(0x00D4)
+#define RTL839X_MODEL_NAME_INFO		(0x0FF0)
+#define RTL838X_LED_GLB_CTRL		(0xA000)
+#define RTL839X_LED_GLB_CTRL		(0x00E4)
+#define RTL838X_EXT_GPIO_DIR_0		(0xA08C)
+#define RTL838X_EXT_GPIO_DIR_1		(0xA090)
+#define RTL838X_EXT_GPIO_DATA_0		(0xA094)
+#define RTL838X_EXT_GPIO_DATA_1		(0xA098)
+#define RTL838X_EXT_GPIO_INDRT_ACCESS	(0xA09C)
+#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
+#define RTL838X_EXTRA_GPIO_DIR_0	(0xA0E4)
+#define RTL838X_EXTRA_GPIO_DIR_1	(0xA0E8)
+#define RTL838X_EXTRA_GPIO_DATA_0	(0xA0EC)
+#define RTL838X_EXTRA_GPIO_DATA_1	(0xA0F0)
+#define RTL838X_DMY_REG5		(0x0144)
+#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
+
+#define RTL838X_GMII_INTF_SEL		(0x1000)
+#define RTL838X_IO_DRIVING_ABILITY_CTRL	(0x1010)
+
+#define RTL838X_GPIO_A7		31
+#define RTL838X_GPIO_A6		30
+#define RTL838X_GPIO_A5		29
+#define RTL838X_GPIO_A4		28
+#define RTL838X_GPIO_A3		27
+#define RTL838X_GPIO_A2		26
+#define RTL838X_GPIO_A1		25
+#define RTL838X_GPIO_A0		24
+#define RTL838X_GPIO_B7		23
+#define RTL838X_GPIO_B6		22
+#define RTL838X_GPIO_B5		21
+#define RTL838X_GPIO_B4		20
+#define RTL838X_GPIO_B3		19
+#define RTL838X_GPIO_B2		18
+#define RTL838X_GPIO_B1		17
+#define RTL838X_GPIO_B0		16
+#define RTL838X_GPIO_C7		15
+#define RTL838X_GPIO_C6		14
+#define RTL838X_GPIO_C5		13
+#define RTL838X_GPIO_C4		12
+#define RTL838X_GPIO_C3		11
+#define RTL838X_GPIO_C2		10
+#define RTL838X_GPIO_C1		9
+#define RTL838X_GPIO_C0		8
+
+#define RTL838X_INT_RW_CTRL		(0x0058)
+#define RTL838X_EXT_VERSION		(0x00D0)
+#define RTL838X_PLL_CML_CTRL		(0x0FF8)
+#define RTL838X_STRAP_DBG		(0x100C)
+
+/*
+ * Reset
+ */
+#define	RGCR				(0x1E70)
+#define RTL839X_RST_GLB_CTRL		(0x0014)
+#define RTL838X_RST_GLB_CTRL_1		(0x0040)
+
+/* LED control by switch */
+#define RTL838X_LED_MODE_SEL		(0x1004)
+#define RTL838X_LED_MODE_CTRL		(0xA004)
+#define RTL838X_LED_P_EN_CTRL		(0xA008)
+
+/* LED control by software */
+#define RTL838X_LED_SW_CTRL		(0xA00C)
+#define RTL838X_LED0_SW_P_EN_CTRL	(0xA010)
+#define RTL838X_LED1_SW_P_EN_CTRL	(0xA014)
+#define RTL838X_LED2_SW_P_EN_CTRL	(0xA018)
+#define RTL838X_LED_SW_P_CTRL(p)	(0xA01C + ((p) << 2))
+
+#define RTL839X_MAC_EFUSE_CTRL		(0x02ac)
+
+/*
+ * MDIO via Realtek's SMI interface
+ */
+#define RTL838X_SMI_GLB_CTRL		(0xa100)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_0	(0xa1b8)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_1	(0xa1bc)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_2	(0xa1c0)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_3	(0xa1c4)
+#define RTL838X_SMI_PORT0_5_ADDR_CTRL	(0xa1c8)
+#define RTL838X_SMI_POLL_CTRL		(0xa17c)
+
+#define RTL839X_SMI_GLB_CTRL		(0x03f8)
+#define RTL839X_SMI_PORT_POLLING_CTRL	(0x03fc)
+#define RTL839X_PHYREG_ACCESS_CTRL	(0x03DC)
+#define RTL839X_PHYREG_CTRL		(0x03E0)
+#define RTL839X_PHYREG_PORT_CTRL(p)	(0x03E4 + ((p >> 5) << 2))
+#define RTL839X_PHYREG_DATA_CTRL	(0x03F0)
+
+/*
+ * Switch interrupts
+ */
+#define RTL838X_IMR_GLB			(0x1100)
+#define RTL838X_IMR_PORT_LINK_STS_CHG	(0x1104)
+#define RTL838X_ISR_GLB_SRC		(0x1148)
+#define RTL838X_ISR_PORT_LINK_STS_CHG	(0x114C)
+#define RTL839X_IMR_GLB			(0x0064)
+#define RTL839X_IMR_PORT_LINK_STS_CHG	(0x0068)
+#define RTL839X_ISR_GLB_SRC		(0x009c)
+#define RTL839X_ISR_PORT_LINK_STS_CHG	(0x00a0)
+
+/* Definition of family IDs */
+#define RTL8389_FAMILY_ID   (0x8389)
+#define RTL8328_FAMILY_ID   (0x8328)
+#define RTL8390_FAMILY_ID   (0x8390)
+#define RTL8350_FAMILY_ID   (0x8350)
+#define RTL8380_FAMILY_ID   (0x8380)
+#define RTL8330_FAMILY_ID   (0x8330)
+
+struct rtl838x_soc_info {
+	unsigned char *name;
+	unsigned int id;
+	unsigned int family;
+	unsigned char *compatible;
+	volatile void *sw_base;
+	volatile void *icu_base;
+};
+
+void rtl838x_soc_detect(struct rtl838x_soc_info *i);
+
+#endif   /* _MACH_RTL838X_H_ */
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the rtl838x specific parts of the kernel
+#
+
+obj-y := serial.o setup.o prom.o irq.o
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform
@@ -0,0 +1,6 @@
+#
+# Realtek RTL838x SoCs
+#
+platform-$(CONFIG_RTL838X) += rtl838x/
+cflags-$(CONFIG_RTL838X)   += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/
+load-$(CONFIG_RTL838X)     += 0xffffffff80000000
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Realtek RTL838X architecture specific IRQ handling
+ *
+ * Copyright  (C) 2020 B. Koblitz
+ * based on the original BSP
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <mach-rtl838x.h>
+
+extern struct rtl838x_soc_info soc_info;
+
+#define icu_r32(reg)			rtl838x_r32(soc_info.icu_base + reg)
+#define icu_w32(val, reg)		rtl838x_w32(val, soc_info.icu_base + reg)
+#define icu_w32_mask(clear, set, reg)	rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
+
+static DEFINE_RAW_SPINLOCK(irq_lock);
+
+extern irqreturn_t c0_compare_interrupt(int irq, void *dev_id);
+unsigned int rtl838x_ictl_irq_dispatch1(void);
+unsigned int rtl838x_ictl_irq_dispatch2(void);
+unsigned int rtl838x_ictl_irq_dispatch3(void);
+unsigned int rtl838x_ictl_irq_dispatch4(void);
+unsigned int rtl838x_ictl_irq_dispatch5(void);
+
+static struct irqaction irq_cascade1 = {
+	.handler = no_action,
+	.name = "RTL838X IRQ cascade1",
+};
+
+static struct irqaction irq_cascade2 = {
+	.handler = no_action,
+	.name = "RTL838X IRQ cascade2",
+};
+
+static struct irqaction irq_cascade3 = {
+	.handler = no_action,
+	.name = "RTL838X IRQ cascade3",
+};
+
+static struct irqaction irq_cascade4 = {
+	.handler = no_action,
+	.name = "RTL838X IRQ cascade4",
+};
+
+static struct irqaction irq_cascade5 = {
+	.handler = no_action,
+	.name = "RTL838X IRQ cascade5",
+};
+
+static void rtl838x_ictl_enable_irq(struct irq_data *i)
+{
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&irq_lock, flags);
+	icu_w32_mask(0, 1 << i->irq, GIMR);
+	raw_spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static unsigned int rtl838x_ictl_startup_irq(struct irq_data *i)
+{
+	rtl838x_ictl_enable_irq(i);
+	return 0;
+}
+
+static void rtl838x_ictl_disable_irq(struct irq_data *i)
+{
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&irq_lock, flags);
+	icu_w32_mask(1 << i->irq, 0, GIMR);
+	raw_spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static void rtl838x_ictl_eoi_irq(struct irq_data *i)
+{
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&irq_lock, flags);
+	icu_w32_mask(0, 1 << i->irq, GIMR);
+	raw_spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static struct irq_chip rtl838x_ictl_irq = {
+	.name = "RTL838X",
+	.irq_startup = rtl838x_ictl_startup_irq,
+	.irq_shutdown = rtl838x_ictl_disable_irq,
+	.irq_enable = rtl838x_ictl_enable_irq,
+	.irq_disable = rtl838x_ictl_disable_irq,
+	.irq_ack = rtl838x_ictl_disable_irq,
+	.irq_mask = rtl838x_ictl_disable_irq,
+	.irq_unmask = rtl838x_ictl_enable_irq,
+	.irq_eoi = rtl838x_ictl_eoi_irq,
+};
+
+/*
+ *   RTL8390/80/28 Interrupt Scheme
+ *
+ *   Source       IRQ      CPU INT
+ *   --------   -------    -------
+ *   UART0          31        IP3
+ *   UART1          30        IP2
+ *   TIMER0         29        IP6
+ *   TIMER1         28        IP2
+ *   OCPTO          27        IP2
+ *   HLXTO          26        IP2
+ *   SLXTO          25        IP2
+ *   NIC            24        IP5
+ *   GPIO_ABCD      23        IP5
+ *   SWCORE         20        IP4
+ */
+
+unsigned int rtl838x_ictl_irq_dispatch1(void)
+{
+	/* Identify shared IRQ  */
+	unsigned int extint_ip = icu_r32(GIMR) & icu_r32(GISR);
+
+	if (extint_ip & TC1_IP)
+		do_IRQ(TC1_IRQ);
+	else if (extint_ip & UART1_IP)
+		do_IRQ(UART1_IRQ);
+	else
+		spurious_interrupt();
+
+	return IRQ_HANDLED;
+}
+
+unsigned int rtl838x_ictl_irq_dispatch2(void)
+{
+	do_IRQ(UART0_IRQ);
+	return IRQ_HANDLED;
+}
+
+unsigned int rtl838x_ictl_irq_dispatch3(void)
+{
+	do_IRQ(SWCORE_IRQ);
+	return IRQ_HANDLED;
+}
+
+unsigned int rtl838x_ictl_irq_dispatch4(void)
+{
+	/* Identify shared IRQ */
+	unsigned int extint_ip = icu_r32(GIMR) & icu_r32(GISR);
+
+	if (extint_ip & NIC_IP)
+		do_IRQ(NIC_IRQ);
+	else if (extint_ip & GPIO_ABCD_IP)
+		do_IRQ(GPIO_ABCD_IRQ);
+	else if ((extint_ip & GPIO_EFGH_IP) && (soc_info.family == RTL8328_FAMILY_ID))
+		do_IRQ(GPIO_EFGH_IRQ);
+	else
+		spurious_interrupt();
+
+	return IRQ_HANDLED;
+}
+
+unsigned int rtl838x_ictl_irq_dispatch5(void)
+{
+	do_IRQ(TC0_IRQ);
+	return IRQ_HANDLED;
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	unsigned int pending;
+
+	pending =  read_c0_cause() & read_c0_status() & ST0_IM;
+
+	if (pending & CAUSEF_IP7)
+		c0_compare_interrupt(7, NULL);
+	else if (pending & CAUSEF_IP6)
+		rtl838x_ictl_irq_dispatch5();
+	else if (pending & CAUSEF_IP5)
+		rtl838x_ictl_irq_dispatch4();
+	else if (pending & CAUSEF_IP4)
+		rtl838x_ictl_irq_dispatch3();
+	else if (pending & CAUSEF_IP3)
+		rtl838x_ictl_irq_dispatch2();
+	else if (pending & CAUSEF_IP2)
+		rtl838x_ictl_irq_dispatch1();
+	else
+		spurious_interrupt();
+}
+
+static void __init rtl838x_ictl_irq_init(unsigned int irq_base)
+{
+	int i;
+
+	for (i = 0; i < RTL838X_IRQ_ICTL_NUM; i++)
+		irq_set_chip_and_handler(irq_base + i, &rtl838x_ictl_irq, handle_level_irq);
+
+	setup_irq(RTL838X_ICTL1_IRQ, &irq_cascade1);
+	setup_irq(RTL838X_ICTL2_IRQ, &irq_cascade2);
+	setup_irq(RTL838X_ICTL3_IRQ, &irq_cascade3);
+	setup_irq(RTL838X_ICTL4_IRQ, &irq_cascade4);
+	setup_irq(RTL838X_ICTL5_IRQ, &irq_cascade5);
+
+	/* Set GIMR, IRR */
+	icu_w32(TC0_IE | UART0_IE, GIMR);
+	icu_w32(IRR0_SETTING, IRR0);
+	icu_w32(IRR1_SETTING, IRR1);
+	icu_w32(IRR2_SETTING, IRR2);
+	icu_w32(IRR3_SETTING, IRR3);
+}
+
+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(hw, &rtl838x_ictl_irq, handle_level_irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops irq_domain_ops = {
+	.xlate = irq_domain_xlate_onecell,
+	.map = intc_map,
+};
+
+int __init icu_of_init(struct device_node *node, struct device_node *parent)
+{
+	int i;
+	struct irq_domain *domain;
+	struct resource res;
+
+	pr_info("Found Interrupt controller: %s (%s)\n", node->name, node->full_name);
+	if (of_address_to_resource(node, 0, &res)) {
+		panic("Failed to get icu memory range");
+	}
+	if (!request_mem_region(res.start, resource_size(&res), res.name))
+		pr_err("Failed to request icu memory\n");
+	soc_info.icu_base = ioremap(res.start, resource_size(&res));
+	pr_info("ICU Memory: %08x\n", (u32)soc_info.icu_base);
+
+	mips_cpu_irq_init();
+
+	domain = irq_domain_add_simple(node, 32, 0, &irq_domain_ops, NULL);
+
+	/* Setup all external HW irqs */
+	for (i = 8; i < 32; i++)
+		irq_domain_associate(domain, i, i);
+
+	rtl838x_ictl_irq_init(RTL838X_IRQ_ICTL_BASE);
+	return 0;
+}
+
+void __init arch_init_irq(void)
+{
+	/* do board-specific irq initialization */
+	irqchip_init();
+}
+
+IRQCHIP_DECLARE(mips_cpu_intc, "rtl838x,icu", icu_of_init);
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * prom.c
+ * Early intialization code for the Realtek RTL838X SoC
+ *
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/cpu.h>
+
+#include <mach-rtl838x.h>
+
+extern char arcs_cmdline[];
+const void *fdt;
+extern const char __appended_dtb;
+//extern int __init rtl838x_serial_init(void);
+
+void prom_console_init(void)
+{
+	/* UART 16550A is initialized by the bootloader */
+}
+
+#ifdef CONFIG_EARLY_PRINTK
+#define rtl838x_r8(reg)		__raw_readb(reg)
+#define rtl838x_w8(val, reg)	__raw_writeb(val, reg)
+
+void unregister_prom_console(void)
+{
+
+}
+
+void disable_early_printk(void)
+{
+
+}
+
+void prom_putchar(char c)
+{
+	unsigned int retry = 0;
+
+	do {
+		if (retry++ >= 30000) {
+			/* Reset Tx FIFO */
+			rtl838x_w8(TXRST | CHAR_TRIGGER_14, UART0_FCR);
+			return;
+		}
+	} while ((rtl838x_r8(UART0_LSR) & LSR_THRE) == TxCHAR_AVAIL);
+
+	/* Send Character */
+	rtl838x_w8(c, UART0_THR);
+}
+
+char prom_getchar(void)
+{
+	return '\0';
+}
+#endif
+
+struct rtl838x_soc_info soc_info;
+
+const char *get_system_type(void)
+{
+	return soc_info.name;
+}
+
+
+void __init prom_free_prom_memory(void)
+{
+
+}
+
+void __init device_tree_init(void)
+{
+	pr_info("%s called\r\n", __func__);
+	if (!fdt_check_header(&__appended_dtb)) {
+		fdt = &__appended_dtb;
+		pr_info("Using appended Device Tree.\n");
+	}
+	initial_boot_params = (void *)fdt;
+	unflatten_and_copy_device_tree();
+}
+
+static void __init prom_init_cmdline(void)
+{
+	int argc = fw_arg0;
+	char **argv = (char **) KSEG1ADDR(fw_arg1);
+	int i;
+
+	arcs_cmdline[0] = '\0';
+
+	for (i = 0; i < argc; i++) {
+		char *p = (char *) KSEG1ADDR(argv[i]);
+
+		if (CPHYSADDR(p) && *p) {
+			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
+			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
+		}
+	}
+	pr_info("Kernel command line: %s\n", arcs_cmdline);
+}
+
+/* Do basic initialization */
+void __init prom_init(void)
+{
+	uint32_t model;
+
+	pr_info("%s called\n", __func__);
+	soc_info.sw_base = RTL838X_SW_BASE;
+
+	model = sw_r32(RTL838X_MODEL_NAME_INFO);
+	pr_info("RTL838X model is %x\n", model);
+	model = model >> 16 & 0xFFFF;
+
+	if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)
+	    && (model != 0x8380) && (model != 0x8382)) {
+		model = sw_r32(RTL839X_MODEL_NAME_INFO);
+		pr_info("RTL839X model is %x\n", model);
+		model = model >> 16 & 0xFFFF;
+	}
+
+	soc_info.id = model;
+
+	switch (model) {
+	case 0x8328:
+		soc_info.name = "RTL8328";
+		soc_info.family = RTL8328_FAMILY_ID;
+		break;
+	case 0x8332:
+		soc_info.name = "RTL8332";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8380:
+		soc_info.name = "RTL8380";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8382:
+		soc_info.name = "RTL8382";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8390:
+		soc_info.name = "RTL8390";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8391:
+		soc_info.name = "RTL8391";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8392:
+		soc_info.name = "RTL8392";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8393:
+		soc_info.name = "RTL8393";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	default:
+		soc_info.name = "DEFAULT";
+		soc_info.family = 0;
+	}
+	pr_info("SoC Type: %s\n", get_system_type());
+	prom_init_cmdline();
+}
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * 8250 serial console setup for the Realtek RTL838X SoC
+ *
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ *
+ * Copyright (C) 2020 B. Koblitz
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/ctype.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/version.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+#include <linux/tty.h>
+#include <linux/clk.h>
+
+#include <asm/mach-rtl838x/mach-rtl838x.h>
+
+extern char arcs_cmdline[];
+extern struct rtl838x_soc_info soc_info;
+
+int __init rtl838x_serial_init(void)
+{
+#ifdef CONFIG_SERIAL_8250
+	int ret;
+	struct uart_port p;
+	unsigned long baud = 0;
+	int err;
+	char parity = '\0', bits = '\0', flow = '\0';
+	char *s;
+	struct device_node *dn;
+
+	dn = of_find_compatible_node(NULL, NULL, "ns16550a");
+	if (dn) {
+		pr_info("Found NS16550a: %s (%s)\n", dn->name, dn->full_name);
+		dn = of_find_compatible_node(dn, NULL, "ns16550a");
+		if (dn && of_device_is_available(dn) && soc_info.family == RTL8380_FAMILY_ID) {
+			/* Enable UART1 on RTL838x */
+			pr_info("Enabling uart1\n");
+			sw_w32(0x10, RTL838X_GMII_INTF_SEL);
+		}
+	} else {
+		pr_err("No NS16550a UART found!");
+		return -ENODEV;
+	}
+
+	s = strstr(arcs_cmdline, "console=ttyS0,");
+	if (s) {
+		s += 14;
+		baud = kstrtoul(s, 10, &baud);
+		if (err)
+			baud = 0;
+		while (isdigit(*s))
+			s++;
+		if (*s == ',')
+			s++;
+		if (*s)
+			parity = *s++;
+		if (*s == ',')
+			s++;
+		if (*s)
+			bits = *s++;
+		if (*s == ',')
+			s++;
+		if (*s == 'h')
+			flow = 'r';
+	}
+
+	if (baud == 0) {
+		baud = 38400;
+		pr_warn("Using default baud rate: %lu\n", baud);
+	}
+	if (parity != 'n' && parity != 'o' && parity != 'e')
+		parity = 'n';
+	if (bits != '7' && bits != '8')
+		bits = '8';
+
+	memset(&p, 0, sizeof(p));
+
+	p.type = PORT_16550A;
+	p.membase = (unsigned char *) RTL838X_UART0_BASE;
+	p.irq = RTL838X_UART0_IRQ;
+	p.uartclk = SYSTEM_FREQ - (24 * baud);
+	p.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_FIXED_TYPE;
+	p.iotype = UPIO_MEM;
+	p.regshift = 2;
+	p.fifosize = 1;
+
+	/* Call early_serial_setup() here, to set up 8250 console driver */
+	if (early_serial_setup(&p) != 0)
+		ret = 1;
+#endif
+	return 0;
+}
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Setup for the Realtek RTL838X SoC:
+ *	Memory, Timer and Serial
+ *
+ * Copyright (C) 2020 B. Koblitz
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ *
+ */
+
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+
+#include <asm/bootinfo.h>
+#include <linux/of_fdt.h>
+#include <asm/reboot.h>
+#include <asm/time.h>		/* for mips_hpt_frequency */
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+
+#include "mach-rtl838x.h"
+
+extern int rtl838x_serial_init(void);
+extern struct rtl838x_soc_info soc_info;
+
+struct clk {
+	struct clk_lookup cl;
+	unsigned long rate;
+};
+
+struct clk cpu_clk;
+
+u32 pll_reset_value;
+
+static void rtl838x_restart(char *command)
+{
+	u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
+	 /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
+	void (*f)(void) = (void *) 0xbfc00000;
+
+	pr_info("System restart.\n");
+	if (soc_info.family == RTL8390_FAMILY_ID) {
+		f();
+		/* If calling reset vector fails, reset entire chip */
+		sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
+		/* If this fails, halt the CPU */
+		while
+			(1);
+	}
+
+	pr_info("PLL control register: %x, applying reset value %x\n",
+		pll, pll_reset_value);
+	sw_w32(3, RTL838X_INT_RW_CTRL);
+	sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
+	sw_w32(0, RTL838X_INT_RW_CTRL);
+
+	pr_info("Resetting RTL838X SoC\n");
+	/* Reset Global Control1 Register */
+	sw_w32(1, RTL838X_RST_GLB_CTRL_1);
+}
+
+static void rtl838x_halt(void)
+{
+	pr_info("System halted.\n");
+	while
+		(1);
+}
+
+static void __init rtl838x_setup(void)
+{
+	unsigned int val;
+
+	pr_info("Registering _machine_restart\n");
+	_machine_restart = rtl838x_restart;
+	_machine_halt = rtl838x_halt;
+
+	val = rtl838x_r32((volatile void *)0xBB0040000);
+	if (val == 3)
+		pr_info("PCI device found\n");
+	else
+		pr_info("NO PCI device found\n");
+
+	/* Setup System LED. Bit 15 (14 for RTL8390) then allows to toggle it */
+	if (soc_info.family == RTL8380_FAMILY_ID)
+		sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
+	else
+		sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
+}
+
+void __init plat_mem_setup(void)
+{
+	void *dtb;
+
+	pr_info("%s called\n", __func__);
+
+	set_io_port_base(KSEG1);
+
+	if (fw_passed_dtb) /* UHI interface */
+		dtb = (void *)fw_passed_dtb;
+	else if (__dtb_start != __dtb_end)
+		dtb = (void *)__dtb_start;
+	else
+		panic("no dtb found");
+
+	/*
+	 * Load the devicetree. This causes the chosen node to be
+	 * parsed resulting in our memory appearing
+	 */
+	__dt_setup_arch(dtb);
+
+	rtl838x_setup();
+}
+
+
+/*
+ * Linux clock API
+ */
+int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	if (!clk)
+		return 0;
+
+	return clk->rate;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	return -1;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	return -1;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+void __init plat_time_init(void)
+{
+	u32 freq = 500000000;
+	struct device_node *np;
+	struct clk *clk = &cpu_clk;
+
+	np = of_find_node_by_name(NULL, "cpus");
+	if (!np) {
+		pr_err("Missing 'cpus' DT node, using default frequency.");
+	} else {
+		if (of_property_read_u32(np, "frequency", &freq) < 0)
+			pr_err("No 'frequency' property in DT, using default.");
+		else
+			pr_info("CPU frequency from device tree: %d", freq);
+		of_node_put(np);
+	}
+
+	clk->rate = freq;
+
+	if (IS_ERR(clk))
+		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+
+	pr_info("CPU Clock: %ld MHz\n", clk->rate / 1000000);
+	mips_hpt_frequency = freq / 2;
+
+	pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
+	pr_info("PLL control register: %x\n", pll_reset_value);
+
+	/* With the info from the command line and cpu-freq we can setup the console */
+	rtl838x_serial_init();
+}
--- a/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c
+++ b/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c
@@ -0,0 +1,808 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <asm/mach-rtl838x/mach-rtl838x.h>
+
+/* RTL8231 registers for LED control */
+#define RTL8231_LED_FUNC0			0x0000
+#define RTL8231_GPIO_PIN_SEL(gpio)		((0x0002) + ((gpio) >> 4))
+#define RTL8231_GPIO_DIR(gpio)			((0x0005) + ((gpio) >> 4))
+#define RTL8231_GPIO_DATA(gpio)			((0x001C) + ((gpio) >> 4))
+#define RTL8231_GPIO_PIN_SEL0			0x0002
+#define RTL8231_GPIO_PIN_SEL1			0x0003
+#define RTL8231_GPIO_PIN_SEL2			0x0004
+#define RTL8231_GPIO_IO_SEL0			0x0005
+#define RTL8231_GPIO_IO_SEL1			0x0006
+#define RTL8231_GPIO_IO_SEL2			0x0007
+
+#define MDC_WAIT { int i; for (i = 0; i < 2; i++); }
+#define I2C_WAIT { int i; for (i = 0; i < 5; i++); }
+
+struct rtl838x_gpios {
+	struct gpio_chip gc;
+	u32 id;
+	struct device *dev;
+	int irq;
+	int bus_id;
+	int num_leds;
+	int min_led;
+	int leds_per_port;
+	u32 led_mode;
+	u16 rtl8381_phy_id;
+	int smi_clock;
+	int smi_data;
+	int i2c_sda;
+	int i2c_sdc;
+};
+
+extern struct mutex smi_lock;
+
+u32 rtl838x_rtl8231_read(u8 bus_id, u32 reg)
+{
+	u32 t = 0;
+
+	reg &= 0x1f;
+	bus_id &= 0x1f;
+
+	/* Calculate read register address */
+	t = (bus_id << 2) | (reg << 7);
+
+	mutex_lock(&smi_lock);
+	/* Set execution bit: cleared when operation completed */
+	t |= 1;
+	sw_w32(t, RTL838X_EXT_GPIO_INDRT_ACCESS);
+	do {	/* TODO: Return 0x80000000 if timeout */
+		t = sw_r32(RTL838X_EXT_GPIO_INDRT_ACCESS);
+	} while (t & 1);
+	pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16);
+
+	mutex_unlock(&smi_lock);
+	return (t & 0xffff0000) >> 16;
+}
+
+int rtl838x_rtl8231_write(u8 bus_id, u32 reg, u32 data)
+{
+	u32 t = 0;
+
+	pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data);
+	data &= 0xffff;
+	reg &= 0x1f;
+	bus_id &= 0x1f;
+
+	mutex_lock(&smi_lock);
+	t = (bus_id << 2) | (reg << 7) | (data << 16);
+	/* Set write bit */
+	t |= 2;
+
+	/* Set execution bit: cleared when operation completed */
+	t |= 1;
+	sw_w32(t, RTL838X_EXT_GPIO_INDRT_ACCESS);
+	do {	/* TODO: Return -1 if timeout */
+		t = sw_r32(RTL838X_EXT_GPIO_INDRT_ACCESS);
+	} while (t & 1);
+
+	mutex_unlock(&smi_lock);
+	return 0;
+}
+
+static int rtl8231_pin_dir(u8 bus_id, u32 gpio, u32 dir)
+{
+	/* dir 1: input
+	 * dir 0: output
+	 */
+
+	u32  v;
+	int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio);
+	int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
+	int pin = gpio % 16;
+	int dpin = pin;
+
+	if (gpio > 31) {
+		dpin = pin << 5;
+		pin_dir_addr = pin_sel_addr;
+	}
+
+	/* Select GPIO function for pin */
+	v = rtl838x_rtl8231_read(bus_id, pin_sel_addr);
+	if (v & 0x80000000) {
+		pr_err("Error reading RTL8231\n");
+		return -1;
+	}
+	rtl838x_rtl8231_write(bus_id, pin_sel_addr, v | (1 << pin));
+
+	v = rtl838x_rtl8231_read(bus_id, pin_dir_addr);
+	if (v & 0x80000000) {
+		pr_err("Error reading RTL8231\n");
+		return -1;
+	}
+	rtl838x_rtl8231_write(bus_id, pin_dir_addr,
+			      (v & ~(1 << dpin)) | (dir << dpin));
+	return 0;
+}
+
+static int rtl8231_pin_dir_get(u8 bus_id, u32 gpio, u32 *dir)
+{
+	/* dir 1: input
+	 * dir 0: output
+	 */
+
+	u32  v;
+	int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
+	int pin = gpio % 16;
+
+	if (gpio > 31) {
+		pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio);
+		pin = pin << 5;
+	}
+
+	v = rtl838x_rtl8231_read(bus_id, pin_dir_addr);
+	if (v & (1 << pin))
+		*dir = 1;
+	else
+		*dir = 0;
+	return 0;
+}
+
+static int rtl8231_pin_set(u8 bus_id, u32 gpio, u32 data)
+{
+	u32 v = rtl838x_rtl8231_read(bus_id, RTL8231_GPIO_DATA(gpio));
+
+	if (v & 0x80000000) {
+		pr_err("Error reading RTL8231\n");
+		return -1;
+	}
+	rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_DATA(gpio),
+			      (v & ~(1 << (gpio % 16))) | (data << (gpio % 16)));
+	return 0;
+}
+
+static int rtl8231_pin_get(u8 bus_id, u32 gpio, u16 *state)
+{
+	u32 v = rtl838x_rtl8231_read(bus_id, RTL8231_GPIO_DATA(gpio));
+
+	if (v & 0x80000000) {
+		pr_err("Error reading RTL8231\n");
+		return -1;
+	}
+
+	*state = v & 0xffff;
+	return 0;
+}
+
+static int rtl838x_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("%s: %d\n", __func__, offset);
+
+	if (offset < 32) {
+		rtl838x_w32_mask(1 << offset, 0, RTL838X_GPIO_PABC_DIR);
+		return 0;
+	}
+
+	/* Internal LED driver does not support input */
+	if (offset >= 32 && offset < 64)
+		return -ENOTSUPP;
+
+	if (offset >= 64 && offset < 100 && gpios->bus_id >= 0)
+		return rtl8231_pin_dir(gpios->bus_id, offset - 64, 1);
+
+	return -ENOTSUPP;
+}
+
+static int rtl838x_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
+{
+	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("%s: %d\n", __func__, offset);
+	if (offset < 32)
+		rtl838x_w32_mask(0, 1 << offset, RTL838X_GPIO_PABC_DIR);
+
+	/* LED for PWR and SYS driver is direction output by default */
+	if (offset >= 32 && offset < 64)
+		return 0;
+
+	if (offset >= 64 && offset < 100 && gpios->bus_id >= 0)
+		return rtl8231_pin_dir(gpios->bus_id, offset - 64, 0);
+	return 0;
+}
+
+static int rtl838x_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+	u32 v = 0;
+	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("%s: %d\n", __func__, offset);
+	if (offset < 32) {
+		v = rtl838x_r32(RTL838X_GPIO_PABC_DIR);
+		if (v & (1 << offset))
+			return 0;
+		return 1;
+	}
+
+	/* LED driver for PWR and SYS is direction output by default */
+	if (offset >= 32 && offset < 64)
+		return 0;
+
+	if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) {
+		rtl8231_pin_dir_get(gpios->bus_id, offset - 64, &v);
+		return v;
+	}
+
+	return 0;
+}
+
+static int rtl838x_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+	u32 v;
+	u16 state = 0;
+	int bit;
+	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("%s: %d\n", __func__, offset);
+
+	/* Internal GPIO of the RTL8380 */
+	if (offset < 32) {
+		v = rtl838x_r32(RTL838X_GPIO_PABC_DATA);
+		if (v & (1 << offset))
+			return 1;
+		return 0;
+	}
+
+	/* LED driver for PWR and SYS */
+	if (offset >= 32 && offset < 64) {
+		v = sw_r32(RTL838X_LED_GLB_CTRL);
+		if (v & (1 << (offset-32)))
+			return 1;
+		return 0;
+	}
+
+	/* Indirect access GPIO with RTL8231 */
+	if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) {
+		rtl8231_pin_get(gpios->bus_id, offset - 64, &state);
+		if (state & (1 << (offset % 16)))
+			return 1;
+		return 0;
+	}
+
+	bit = (offset - 100) % 32;
+	if (offset >= 100 && offset < 132) {
+		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit))
+			return 1;
+		return 0;
+	}
+	if (offset >= 132 && offset < 164) {
+		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit))
+			return 1;
+		return 0;
+	}
+	if (offset >= 164 && offset < 196) {
+		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit))
+			return 1;
+		return 0;
+	}
+	return 0;
+}
+
+void rtl838x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+	int bit;
+	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("rtl838x_set: %d, value: %d\n", offset, value);
+	/* Internal GPIO of the RTL8380 */
+	if (offset < 32) {
+		if (value)
+			rtl838x_w32_mask(0, 1 << offset, RTL838X_GPIO_PABC_DATA);
+		else
+			rtl838x_w32_mask(1 << offset, 0, RTL838X_GPIO_PABC_DATA);
+	}
+
+	/* LED driver for PWR and SYS */
+	if (offset >= 32 && offset < 64) {
+		bit = offset - 32;
+		if (value)
+			sw_w32_mask(0, 1 << bit, RTL838X_LED_GLB_CTRL);
+		else
+			sw_w32_mask(1 << bit, 0, RTL838X_LED_GLB_CTRL);
+		return;
+	}
+
+	/* Indirect access GPIO with RTL8231 */
+	if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) {
+		rtl8231_pin_set(gpios->bus_id, offset - 64, value);
+		return;
+	}
+
+	bit = (offset - 100) % 32;
+	/* First Port-LED */
+	if (offset >= 100 && offset < 132
+	   && offset >= (100 + gpios->min_led)
+	   && offset < (100 + gpios->min_led + gpios->num_leds)) {
+		if (value)
+			sw_w32_mask(7, 5, RTL838X_LED_SW_P_CTRL(bit));
+		else
+			sw_w32_mask(7, 0, RTL838X_LED_SW_P_CTRL(bit));
+	}
+	if (offset >= 132 && offset < 164
+	    && offset >= (132 + gpios->min_led)
+	    && offset < (132 + gpios->min_led + gpios->num_leds)) {
+		if (value)
+			sw_w32_mask(7 << 3, 5 << 3, RTL838X_LED_SW_P_CTRL(bit));
+		else
+			sw_w32_mask(7 << 3, 0, RTL838X_LED_SW_P_CTRL(bit));
+	}
+	if (offset >= 164 && offset < 196
+	    && offset >= (164 + gpios->min_led)
+	    && offset < (164 + gpios->min_led + gpios->num_leds)) {
+		if (value)
+			sw_w32_mask(7 << 6, 5 << 6, RTL838X_LED_SW_P_CTRL(bit));
+		else
+			sw_w32_mask(7 << 6, 0, RTL838X_LED_SW_P_CTRL(bit));
+	}
+	__asm__ volatile ("sync");
+}
+
+int rtl8231_init(struct rtl838x_gpios *gpios)
+{
+	uint32_t v;
+	u8 bus_id = gpios->bus_id;
+
+	pr_info("%s called\n", __func__);
+
+	/* Enable RTL8231 indirect access mode */
+	sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL);
+	sw_w32_mask(3, 1, RTL838X_DMY_REG5);
+
+	/* Enable RTL8231 via GPIO_A1 line */
+	rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DIR);
+	rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DATA);
+	mdelay(50); /* wait 50ms for reset */
+
+	/*Select GPIO functionality for pins 0-15, 16-31 and 32-37 */
+	rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL(0), 0xffff);
+	rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL(16), 0xffff);
+	rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL2, 0x03ff);
+
+	v = rtl838x_rtl8231_read(bus_id, RTL8231_LED_FUNC0);
+	pr_info("RTL8231 led function now: %x\n", v);
+
+	return 0;
+}
+
+static void smi_write_bit(struct rtl838x_gpios *gpios, u32 bit)
+{
+	if (bit)
+		rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DATA);
+	else
+		rtl838x_w32_mask(1 << gpios->smi_data, 0, RTL838X_GPIO_PABC_DATA);
+
+	MDC_WAIT;
+	rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA);
+	MDC_WAIT;
+	rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA);
+}
+
+static int smi_read_bit(struct rtl838x_gpios *gpios)
+{
+	u32 v;
+
+	MDC_WAIT;
+	rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA);
+	MDC_WAIT;
+	rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA);
+
+	v = rtl838x_r32(RTL838X_GPIO_PABC_DATA);
+	if (v & (1 << gpios->smi_data))
+		return 1;
+	return 0;
+}
+
+/* Tri-state of MDIO line */
+static void smi_z(struct rtl838x_gpios *gpios)
+{
+	/* MDIO pin to input */
+	rtl838x_w32_mask(1 << gpios->smi_data, 0, RTL838X_GPIO_PABC_DIR);
+	MDC_WAIT;
+	rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA);
+	MDC_WAIT;
+	rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA);
+}
+
+static void smi_write_bits(struct rtl838x_gpios *gpios, u32 data, int len)
+{
+	while (len) {
+		len--;
+		smi_write_bit(gpios, data & (1 << len));
+	}
+}
+
+static void smi_read_bits(struct rtl838x_gpios *gpios, int len, u32 *data)
+{
+	u32 v = 0;
+
+	while (len) {
+		len--;
+		v <<= 1;
+		v |= smi_read_bit(gpios);
+	}
+	*data = v;
+}
+
+/* Bit-banged verson of SMI write access, caller must hold smi_lock */
+int rtl8380_smi_write(struct rtl838x_gpios *gpios, u16 reg, u32 data)
+{
+	u16 bus_id = gpios->bus_id;
+
+	/* Set clock and data pins on RTL838X to output */
+	rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DIR);
+	rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DIR);
+
+	/* Write start bits */
+	smi_write_bits(gpios, 0xffffffff, 32);
+
+	smi_write_bits(gpios, 0x5, 4);		/* ST and write OP */
+
+	smi_write_bits(gpios, bus_id, 5);	/* 5 bits: phy address */
+	smi_write_bits(gpios, reg, 5);		/* 5 bits: register address */
+
+	smi_write_bits(gpios, 0x2, 2);		/* TURNAROUND */
+
+	smi_write_bits(gpios, data, 16);	/* 16 bits: data*/
+
+	smi_z(gpios);
+
+	return 0;
+}
+
+/* Bit-banged verson of SMI read access, caller must hold smi_lock */
+int rtl8380_smi_read(struct rtl838x_gpios *gpios, u16 reg, u32 *data)
+{
+	u16 bus_id = gpios->bus_id;
+
+	/* Set clock and data pins on RTL838X to output */
+	rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DIR);
+	rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DIR);
+
+	/* Write start bits */
+	smi_write_bits(gpios, 0xffffffff, 32);
+
+	smi_write_bits(gpios, 0x6, 4);		/* ST and read OP */
+
+	smi_write_bits(gpios, bus_id, 5);	/* 5 bits: phy address */
+	smi_write_bits(gpios, reg, 5);		/* 5 bits: register address */
+
+	smi_z(gpios);				/* TURNAROUND */
+
+	smi_read_bits(gpios, 16, data);
+	return 0;
+}
+
+static void i2c_pin_set(struct rtl838x_gpios *gpios, int pin, u32 data)
+{
+	u32 v;
+
+	rtl8380_smi_read(gpios, RTL8231_GPIO_DATA(pin), &v);
+	if (!data)
+		v &= ~(1 << (pin % 16));
+	else
+		v |= (1 << (pin % 16));
+	rtl8380_smi_write(gpios, RTL8231_GPIO_DATA(pin), v);
+}
+
+static void i2c_pin_get(struct rtl838x_gpios *gpios, int pin, u32 *data)
+{
+	u32 v;
+
+	rtl8380_smi_read(gpios, RTL8231_GPIO_DATA(pin), &v);
+	if (v & (1 << (pin % 16))) {
+		*data = 1;
+		return;
+	}
+	*data = 0;
+}
+
+static void i2c_pin_dir(struct rtl838x_gpios *gpios, int pin, u16 direction)
+{
+	u32 v;
+
+	rtl8380_smi_read(gpios, RTL8231_GPIO_DIR(pin), &v);
+	if (direction) // Output
+		v &= ~(1 << (pin % 16));
+	else
+		v |= (1 << (pin % 16));
+	rtl8380_smi_write(gpios, RTL8231_GPIO_DIR(pin), v);
+}
+
+static void i2c_start(struct rtl838x_gpios *gpios)
+{
+	i2c_pin_dir(gpios, gpios->i2c_sda, 0); /* Output */
+	i2c_pin_dir(gpios, gpios->i2c_sdc, 0); /* Output */
+	I2C_WAIT;
+	i2c_pin_set(gpios, gpios->i2c_sdc, 1);
+	I2C_WAIT;
+	i2c_pin_set(gpios, gpios->i2c_sda, 1);
+	I2C_WAIT;
+	i2c_pin_set(gpios, gpios->i2c_sda, 0);
+	I2C_WAIT;
+	i2c_pin_set(gpios, gpios->i2c_sdc, 0);
+	I2C_WAIT;
+}
+
+static void i2c_stop(struct rtl838x_gpios *gpios)
+{
+	I2C_WAIT;
+	i2c_pin_set(gpios, gpios->i2c_sdc, 1);
+	i2c_pin_set(gpios, gpios->i2c_sda, 0);
+	I2C_WAIT;
+
+	i2c_pin_set(gpios, gpios->i2c_sda, 1);
+	I2C_WAIT;
+	i2c_pin_set(gpios, gpios->i2c_sdc, 0);
+
+	i2c_pin_dir(gpios, gpios->i2c_sda, 1); /* Input */
+	i2c_pin_dir(gpios, gpios->i2c_sdc, 1); /* Input */
+}
+
+static void i2c_read_bits(struct rtl838x_gpios *gpios, int len, u32 *data)
+{
+	u32 v = 0, t;
+
+	while (len) {
+		len--;
+		v <<= 1;
+		i2c_pin_set(gpios, gpios->i2c_sdc, 1);
+		I2C_WAIT;
+		i2c_pin_get(gpios, gpios->i2c_sda, &t);
+		v |= t;
+		i2c_pin_set(gpios, gpios->i2c_sdc, 0);
+		I2C_WAIT;
+	}
+	*data = v;
+}
+
+static void i2c_write_bits(struct rtl838x_gpios *gpios, u32 data, int len)
+{
+	while (len) {
+		len--;
+		i2c_pin_set(gpios, gpios->i2c_sda, data & (1 << len));
+		I2C_WAIT;
+		i2c_pin_set(gpios, gpios->i2c_sdc, 1);
+		I2C_WAIT;
+		i2c_pin_set(gpios, gpios->i2c_sdc, 0);
+		I2C_WAIT;
+	}
+}
+
+/* This initializes direct external GPIOs via the RTL8231 */
+int rtl8380_rtl8321_init(struct rtl838x_gpios *gpios)
+{
+	u32 v;
+	int mdc = gpios->smi_clock;
+	int mdio = gpios->smi_data;
+
+	pr_info("Configuring SMI: Clock %d, Data %d\n", mdc, mdio);
+	sw_w32_mask(0, 0x2, RTL838X_IO_DRIVING_ABILITY_CTRL);
+
+	/* Enter simulated GPIO mode */
+	sw_w32_mask(1, 0, RTL838X_EXTRA_GPIO_CTRL);
+
+	/* MDIO clock to 2.6MHz */
+	sw_w32_mask(0x3 << 8, 0, RTL838X_EXTRA_GPIO_CTRL);
+
+	/* Configure SMI clock and data GPIO pins */
+	rtl838x_w32_mask((1 << mdc) | (1 << mdio), 0, RTL838X_GPIO_PABC_CNR);
+	rtl838x_w32_mask(0, (1 << mdc) | (1 << mdio), RTL838X_GPIO_PABC_DIR);
+
+	rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL0, 0xffff);
+	rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL1, 0xffff);
+	rtl8380_smi_read(gpios, RTL8231_GPIO_PIN_SEL2, &v);
+	v |= 0x1f;
+	rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL2, v);
+
+	rtl8380_smi_write(gpios, RTL8231_GPIO_IO_SEL0, 0xffff);
+	rtl8380_smi_write(gpios, RTL8231_GPIO_IO_SEL1, 0xffff);
+	rtl8380_smi_read(gpios, RTL8231_GPIO_IO_SEL2, &v);
+	v |= 0x1f << 5;
+	rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL2, v);
+
+	return 0;
+}
+
+void rtl8380_led_test(u32 mask)
+{
+	int i;
+	u32 mode_sel = sw_r32(RTL838X_LED_MODE_SEL);
+	u32 led_gbl = sw_r32(RTL838X_LED_GLB_CTRL);
+	u32 led_p_en = sw_r32(RTL838X_LED_P_EN_CTRL);
+
+	/* 2 Leds for ports 0-23 and 24-27, 3 would be 0x7 */
+	sw_w32_mask(0x3f, 0x3 | (0x3 << 3), RTL838X_LED_GLB_CTRL);
+	/* Enable all leds */
+	sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
+
+	/* Enable software control of all leds */
+	sw_w32(0xFFFFFFF, RTL838X_LED_SW_CTRL);
+	sw_w32(0xFFFFFFF, RTL838X_LED0_SW_P_EN_CTRL);
+	sw_w32(0xFFFFFFF, RTL838X_LED1_SW_P_EN_CTRL);
+	sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL);
+
+	for (i = 0; i < 28; i++) {
+		if (mask & (1 << i))
+			sw_w32(5 | (5 << 3) | (5 << 6),
+			       RTL838X_LED_SW_P_CTRL(i));
+	}
+	msleep(3000);
+
+	sw_w32(led_p_en, RTL838X_LED_P_EN_CTRL);
+	/* Disable software control of all leds */
+	sw_w32(0x0000000, RTL838X_LED_SW_CTRL);
+	sw_w32(0x0000000, RTL838X_LED0_SW_P_EN_CTRL);
+	sw_w32(0x0000000, RTL838X_LED1_SW_P_EN_CTRL);
+	sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL);
+
+	sw_w32(led_gbl, RTL838X_LED_GLB_CTRL);
+	sw_w32(mode_sel, RTL838X_LED_MODE_SEL);
+}
+
+void take_port_leds(struct rtl838x_gpios *gpios)
+{
+	int leds_per_port = gpios->leds_per_port;
+	int mode = gpios->led_mode;
+
+	pr_info("%s, %d, %x\n", __func__, leds_per_port, mode);
+	pr_debug("Bootloader settings: %x %x %x\n",
+		sw_r32(RTL838X_LED0_SW_P_EN_CTRL),
+		sw_r32(RTL838X_LED1_SW_P_EN_CTRL),
+		sw_r32(RTL838X_LED2_SW_P_EN_CTRL)
+	);
+
+	pr_debug("led glb: %x, sel %x\n",
+	       sw_r32(RTL838X_LED_GLB_CTRL), sw_r32(RTL838X_LED_MODE_SEL));
+	pr_debug("RTL838X_LED_P_EN_CTRL: %x", sw_r32(RTL838X_LED_P_EN_CTRL));
+	pr_debug("RTL838X_LED_MODE_CTRL: %x", sw_r32(RTL838X_LED_MODE_CTRL));
+
+	sw_w32_mask(3, 0, RTL838X_LED_MODE_SEL);
+	sw_w32(mode, RTL838X_LED_MODE_CTRL);
+
+	/* Enable software control of all leds */
+	sw_w32(0xFFFFFFF, RTL838X_LED_SW_CTRL);
+	sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
+
+	sw_w32(0x0000000, RTL838X_LED0_SW_P_EN_CTRL);
+	sw_w32(0x0000000, RTL838X_LED1_SW_P_EN_CTRL);
+	sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL);
+
+	sw_w32_mask(0x3f, 0, RTL838X_LED_GLB_CTRL);
+	switch (leds_per_port) {
+	case 3:
+		sw_w32_mask(0, 0x7 | (0x7 << 3), RTL838X_LED_GLB_CTRL);
+		sw_w32(0xFFFFFFF, RTL838X_LED2_SW_P_EN_CTRL);
+		/* FALLTHRU */
+	case 2:
+		sw_w32_mask(0, 0x3 | (0x3 << 3), RTL838X_LED_GLB_CTRL);
+		sw_w32(0xFFFFFFF, RTL838X_LED1_SW_P_EN_CTRL);
+		/* FALLTHRU */
+	case 1:
+		sw_w32_mask(0, 0x1 | (0x1 << 3), RTL838X_LED_GLB_CTRL);
+		sw_w32(0xFFFFFFF, RTL838X_LED0_SW_P_EN_CTRL);
+		break;
+	default:
+		pr_err("No LEDS configured for software control\n");
+	}
+}
+
+static const struct of_device_id rtl838x_gpio_of_match[] = {
+	{ .compatible = "realtek,rtl838x-gpio" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, rtl838x_gpio_of_match);
+
+static int rtl838x_gpio_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct rtl838x_gpios *gpios;
+	int err;
+	u8 indirect_bus_id;
+
+	pr_info("Probing RTL838X GPIOs\n");
+
+	if (!np) {
+		dev_err(&pdev->dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
+	if (!gpios)
+		return -ENOMEM;
+
+	gpios->id = sw_r32(RTL838X_MODEL_NAME_INFO) >> 16;
+
+	switch (gpios->id) {
+	case 0x8332:
+		pr_debug("Found RTL8332M GPIO\n");
+		break;
+	case 0x8380:
+		pr_debug("Found RTL8380M GPIO\n");
+		break;
+	case 0x8381:
+		pr_debug("Found RTL8381M GPIO\n");
+		break;
+	case 0x8382:
+		pr_debug("Found RTL8382M GPIO\n");
+		break;
+	default:
+		pr_err("Unknown GPIO chip id (%04x)\n", gpios->id);
+		return -ENODEV;
+	}
+
+	gpios->dev = dev;
+	gpios->gc.base = 0;
+	/* 0-31: internal
+	 * 32-63, LED control register
+	 * 64-99: external RTL8231
+	 * 100-131: PORT-LED 0
+	 * 132-163: PORT-LED 1
+	 * 164-195: PORT-LED 2
+	 */
+	gpios->gc.ngpio = 196;
+	gpios->gc.label = "rtl838x";
+	gpios->gc.parent = dev;
+	gpios->gc.owner = THIS_MODULE;
+	gpios->gc.can_sleep = true;
+	gpios->bus_id = -1;
+	gpios->irq = 31;
+
+	gpios->gc.direction_input = rtl838x_direction_input;
+	gpios->gc.direction_output = rtl838x_direction_output;
+	gpios->gc.set = rtl838x_gpio_set;
+	gpios->gc.get = rtl838x_gpio_get;
+	gpios->gc.get_direction = rtl838x_get_direction;
+
+	if (!of_property_read_u8(np, "indirect-access-bus-id", &indirect_bus_id)) {
+		gpios->bus_id = indirect_bus_id;
+		rtl8231_init(gpios);
+	}
+	if (!of_property_read_u8(np, "smi-bus-id", &indirect_bus_id)) {
+		gpios->bus_id = indirect_bus_id;
+		gpios->smi_clock = RTL838X_GPIO_A2;
+		gpios->smi_data = RTL838X_GPIO_A3;
+		gpios->i2c_sda = 1;
+		gpios->i2c_sdc = 2;
+		rtl8380_rtl8321_init(gpios);
+	}
+
+	if (of_property_read_bool(np, "take-port-leds")) {
+		if (of_property_read_u32(np, "leds-per-port", &gpios->leds_per_port))
+			gpios->leds_per_port = 2;
+		if (of_property_read_u32(np, "led-mode", &gpios->led_mode))
+			gpios->led_mode = (0x1ea << 15) | 0x1ea;
+		if (of_property_read_u32(np, "num-leds", &gpios->num_leds))
+			gpios->num_leds = 32;
+		if (of_property_read_u32(np, "min-led", &gpios->min_led))
+			gpios->min_led = 0;
+		take_port_leds(gpios);
+	}
+
+	err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
+	return err;
+}
+
+
+static struct platform_driver rtl838x_gpio_driver = {
+	.driver = {
+		.name = "rtl838x-gpio",
+		.of_match_table	= rtl838x_gpio_of_match,
+	},
+	.probe = rtl838x_gpio_probe,
+};
+
+module_platform_driver(rtl838x_gpio_driver);
+
+MODULE_DESCRIPTION("Realtek RTL838X GPIO API support");
+MODULE_LICENSE("GPL v2");
--- a/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
+++ b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/spi-nor.h>
+
+#include "rtl838x-spi.h"
+#include <asm/mach-rtl838x/mach-rtl838x.h>
+
+extern struct rtl838x_soc_info soc_info;
+
+struct rtl838x_nor {
+	struct spi_nor nor;
+	struct device *dev;
+	volatile void __iomem *base;
+	bool fourByteMode;
+	u32 chipSize;
+	uint32_t flags;
+	uint32_t io_status;
+};
+
+static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor)
+{
+	/* Needed because of MMU constraints */
+	SPI_WAIT_READY;
+	spi_w32w(SPI_CS_INIT, SFCSR);	//deactivate CS0, CS1
+	spi_w32w(0, SFCSR);		//activate CS0,CS1
+	spi_w32w(SPI_CS_INIT, SFCSR);	//deactivate CS0, CS1
+
+	return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT)
+			: ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL);
+}
+
+static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor)
+{
+	uint32_t sfcsr, sfdr;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr  = (SPINOR_OP_RDSR)<<24;
+
+	pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr);
+	pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4);
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	spi_w32_mask(0, SPI_LEN4, SFCSR);
+	SPI_WAIT_READY;
+
+	return spi_r32(SFDR);
+}
+
+static void spi_write_disable(struct rtl838x_nor *rtl838x_nor)
+{
+	uint32_t sfcsr, sfdr;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = (SPINOR_OP_WRDI) << 24;
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
+
+	spi_prep(rtl838x_nor);
+}
+
+static void spi_write_enable(struct rtl838x_nor *rtl838x_nor)
+{
+	uint32_t sfcsr, sfdr;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = (SPINOR_OP_WREN) << 24;
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
+
+	spi_prep(rtl838x_nor);
+}
+
+static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable)
+{
+	uint32_t sfcsr, sfdr;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	if (enable)
+		sfdr = (SPINOR_OP_EN4B) << 24;
+	else
+		sfdr = (SPINOR_OP_EX4B) << 24;
+
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
+
+	spi_prep(rtl838x_nor);
+}
+
+static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
+{
+	int res = 3;
+	u32 reg;
+
+	sw_w32(0x3, RTL838X_INT_RW_CTRL);
+	if (!sw_r32(RTL838X_EXT_VERSION)) {
+		if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
+			res = 4;
+	} else {
+		reg = sw_r32(RTL838X_PLL_CML_CTRL);
+		if ((reg & (1 << 30)) && (reg & (1 << 31)))
+			res = 4;
+		if ((!(reg & (1 << 30)))
+		     && sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
+			res = 4;
+	}
+	sw_w32(0x0, RTL838X_INT_RW_CTRL);
+	return res;
+}
+
+static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
+{
+	if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9))
+		return 4;
+	return 3;
+}
+
+ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
+			       size_t length, u_char *buffer, uint8_t command)
+{
+	uint32_t sfcsr, sfdr;
+	uint32_t len = length;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = command << 24;
+
+	/* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/
+	sfcsr |= SPI_LEN4;
+	sfdr |= from;
+
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+
+	/* Read Data, 4 bytes at a time */
+	while (length >= 4) {
+		SPI_WAIT_READY;
+		*((uint32_t *) buffer) = spi_r32(SFDR);
+/*		printk("%.8x  ", *((uint32_t*) buffer)); */
+		buffer += 4;
+		length -= 4;
+	}
+
+	/* The rest needs to be read 1 byte a time */
+	sfcsr &= SPI_LEN_INIT|SPI_LEN1;
+	SPI_WAIT_READY;
+	spi_w32w(sfcsr, SFCSR);
+	while (length > 0) {
+		SPI_WAIT_READY;
+		*(buffer) = spi_r32(SFDR) >> 24;
+/*		printk("%.2x  ", *(buffer)); */
+		buffer++;
+		length--;
+	}
+	return len;
+}
+
+/*
+ * Do fast read in 3 or 4 Byte addressing mode
+ */
+static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
+			       size_t length, u_char *buffer, uint8_t command)
+{
+	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
+	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
+	uint32_t sfcsr;
+	uint32_t len = length;
+
+	pr_debug("Fast read from %llx, len %x, shift %d\n",
+		 from, sfcsr_addr_len, sfdr_addr_shift);
+	sfcsr = spi_prep(rtl838x_nor);
+
+	/* Send read command */
+	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
+	spi_w32w(command << 24, SFDR);
+
+	/* Send address */
+	spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR);
+	spi_w32w(from << sfdr_addr_shift, SFDR);
+
+	/* Dummy cycles */
+	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
+	spi_w32w(0, SFDR);
+
+	/* Start reading */
+	spi_w32w(sfcsr | SPI_LEN4, SFCSR);
+
+	/* Read Data, 4 bytes at a time */
+	while (length >= 4) {
+		SPI_WAIT_READY;
+		*((uint32_t *) buffer) = spi_r32(SFDR);
+/*		printk("%.8x  ", *((uint32_t*) buffer)); */
+		buffer += 4;
+		length -= 4;
+	}
+
+	/* The rest needs to be read 1 byte a time */
+	sfcsr &= SPI_LEN_INIT|SPI_LEN1;
+	SPI_WAIT_READY;
+	spi_w32w(sfcsr, SFCSR);
+	while (length > 0) {
+		SPI_WAIT_READY;
+		*(buffer) = spi_r32(SFDR) >> 24;
+/*		printk("%.2x  ", *(buffer)); */
+		buffer++;
+		length--;
+	}
+	return len;
+
+}
+
+/*
+ * Do write (Page Programming) in 3 or 4 Byte addressing mode
+ */
+static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to,
+				    size_t length, const u_char *buffer,
+				    uint8_t command)
+{
+	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
+	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
+	uint32_t sfcsr;
+	uint32_t len = length;
+
+	pr_debug("Write to %llx, len %x, shift %d\n",
+		 to, sfcsr_addr_len, sfdr_addr_shift);
+	sfcsr = spi_prep(rtl838x_nor);
+
+	/* Send write command, command IO-width is 1 (bit 25/26) */
+	spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
+	spi_w32w(command << 24, SFDR);
+
+	/* Send address */
+	spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
+	spi_w32w(to << sfdr_addr_shift, SFDR);
+
+	/* Write Data, 1 byte at a time, if we are not 4-byte aligned */
+	if (((long)buffer) % 4) {
+		spi_w32w(sfcsr | SPI_LEN1, SFCSR);
+		while (length > 0 && (((long)buffer) % 4)) {
+			SPI_WAIT_READY;
+			spi_w32(*(buffer) << 24, SFDR);
+			buffer += 1;
+			length -= 1;
+		}
+	}
+
+	/* Now we can write 4 bytes at a time */
+	SPI_WAIT_READY;
+	spi_w32w(sfcsr | SPI_LEN4, SFCSR);
+	while (length >= 4) {
+		SPI_WAIT_READY;
+		spi_w32(*((uint32_t *)buffer), SFDR);
+		buffer += 4;
+		length -= 4;
+	}
+
+	/* Final bytes might need to be written 1 byte at a time, again */
+	SPI_WAIT_READY;
+	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
+	while (length > 0) {
+		SPI_WAIT_READY;
+		spi_w32(*(buffer) << 24, SFDR);
+		buffer++;
+		length--;
+	}
+	return len;
+}
+
+static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len,
+				 const u_char *buffer)
+{
+	int ret = 0;
+	uint32_t offset = 0;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+	size_t l = len;
+	uint8_t cmd = SPINOR_OP_PP;
+
+	/* Do write in 4-byte mode on large Macronix chips */
+	if (rtl838x_nor->fourByteMode) {
+		cmd = SPINOR_OP_PP_4B;
+		spi_4b_set(rtl838x_nor, true);
+	}
+
+	pr_debug("In %s %8x to: %llx\n", __func__,
+		 (unsigned int) rtl838x_nor, to);
+
+	while (l >= SPI_MAX_TRANSFER_SIZE) {
+		while
+			(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
+		do {
+			spi_write_enable(rtl838x_nor);
+		} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
+		ret = rtl838x_do_4b_write(rtl838x_nor, to + offset,
+				SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
+		l -= SPI_MAX_TRANSFER_SIZE;
+		offset += SPI_MAX_TRANSFER_SIZE;
+	}
+
+	if (l > 0) {
+		while
+			(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
+		do {
+			spi_write_enable(rtl838x_nor);
+		} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
+		ret = rtl838x_do_4b_write(rtl838x_nor, to+offset,
+					  len, buffer+offset, cmd);
+	}
+
+	return len;
+}
+
+static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from,
+				size_t length, u_char *buffer)
+{
+	uint32_t offset = 0;
+	uint8_t cmd = SPINOR_OP_READ_FAST;
+	size_t l = length;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	/* Do fast read in 3, or 4-byte mode on large Macronix chips */
+	if (rtl838x_nor->fourByteMode) {
+		cmd = SPINOR_OP_READ_FAST_4B;
+		spi_4b_set(rtl838x_nor, true);
+	}
+
+	/* TODO: do timeout and return error */
+	pr_debug("Waiting for pending writes\n");
+	while
+		(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
+	do {
+		spi_write_enable(rtl838x_nor);
+	} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
+
+	pr_debug("cmd is %d\n", cmd);
+	pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__,
+		 from, (u32)buffer, (u32)cmd, length);
+
+	while (l >= SPI_MAX_TRANSFER_SIZE) {
+		rtl838x_do_4bf_read(rtl838x_nor, from + offset,
+				    SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
+		l -= SPI_MAX_TRANSFER_SIZE;
+		offset += SPI_MAX_TRANSFER_SIZE;
+	}
+
+	if (l > 0)
+		rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd);
+
+	return length;
+}
+
+static int rtl838x_erase(struct spi_nor *nor, loff_t offs)
+{
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
+	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
+	uint32_t sfcsr;
+	uint8_t cmd = SPINOR_OP_SE;
+
+	pr_debug("Erasing sector at %llx\n", offs);
+
+	/* Do erase in 4-byte mode on large Macronix chips */
+	if (rtl838x_nor->fourByteMode) {
+		cmd = SPINOR_OP_SE_4B;
+		spi_4b_set(rtl838x_nor, true);
+	}
+	/* TODO: do timeout and return error */
+	while
+		(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
+	do {
+		spi_write_enable(rtl838x_nor);
+	} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
+
+	sfcsr = spi_prep(rtl838x_nor);
+
+	/* Send erase command, command IO-width is 1 (bit 25/26) */
+	spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
+	spi_w32w(cmd << 24, SFDR);
+
+	/* Send address */
+	spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
+	spi_w32w(offs << sfdr_addr_shift, SFDR);
+
+	return 0;
+}
+
+static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+	int length = len;
+	u8 *buffer = buf;
+	uint32_t sfcsr, sfdr;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len);
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = opcode << 24;
+
+	sfcsr |= SPI_LEN1;
+
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+
+	while (length > 0) {
+		SPI_WAIT_READY;
+		*(buffer) = spi_r32(SFDR) >> 24;
+		buffer++;
+		length--;
+	}
+
+	return len;
+}
+
+static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+	uint32_t sfcsr, sfdr;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len);
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = opcode << 24;
+
+	if (len == 1) { /* SPINOR_OP_WRSR */
+		sfdr |= buf[0];
+		sfcsr |= SPI_LEN2;
+	}
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	return 0;
+}
+
+static int spi_enter_sio(struct spi_nor *nor)
+{
+	uint32_t sfcsr, sfcr2, sfdr;
+	uint32_t ret = 0, reg = 0, size_bits;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	pr_debug("In %s\n", __func__);
+	rtl838x_nor->io_status = 0;
+	sfdr = SPI_C_RSTQIO << 24;
+	sfcsr = spi_prep(rtl838x_nor);
+
+	reg = spi_r32(SFCR2);
+	pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg),
+						  (reg & SFCR2_RDOPT));
+	size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7);
+
+	sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits
+		| (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0)
+		| SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4)
+		| SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST);
+	pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg));
+
+	SPI_WAIT_READY;
+	spi_w32w(sfcr2, SFCR2);
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+
+	spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2);
+	rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK;
+	rtl838x_nor->io_status |= CIO1;
+
+	spi_prep(rtl838x_nor);
+
+	return ret;
+}
+
+int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name)
+{
+	static const struct spi_nor_hwcaps hwcaps = {
+		.mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP
+			| SNOR_HWCAPS_READ_FAST
+	};
+
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	pr_debug("In %s\n", __func__);
+
+	spi_w32_mask(0, SFCR_EnableWBO, SFCR);
+	spi_w32_mask(0, SFCR_EnableRBO, SFCR);
+
+	rtl838x_nor->flags = CS0 | R_MODE;
+
+	spi_nor_scan(nor, NULL, &hwcaps);
+	pr_debug("------------- Got size: %llx\n", nor->mtd.size);
+
+	return 0;
+}
+
+int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor,
+			struct device_node *flash_node)
+{
+	int ret;
+	struct spi_nor *nor;
+
+	pr_info("%s called\n", __func__);
+	nor = &rtl838x_nor->nor;
+	nor->dev = rtl838x_nor->dev;
+	nor->priv = rtl838x_nor;
+	spi_nor_set_flash_node(nor, flash_node);
+
+	nor->read_reg = rtl838x_nor_read_reg;
+	nor->write_reg = rtl838x_nor_write_reg;
+	nor->read = rtl838x_nor_read;
+	nor->write = rtl838x_nor_write;
+	nor->erase = rtl838x_erase;
+	nor->mtd.name = "rtl838x_nor";
+	nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B
+					: SPINOR_OP_SE;
+	/* initialized with NULL */
+	ret = rtl838x_spi_nor_scan(nor, NULL);
+	if (ret)
+		return ret;
+
+	spi_enter_sio(nor);
+	spi_write_disable(rtl838x_nor);
+
+	ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0);
+	return ret;
+}
+
+static int rtl838x_nor_drv_probe(struct platform_device *pdev)
+{
+	struct device_node *flash_np;
+	struct resource *res;
+	int ret;
+	struct rtl838x_nor *rtl838x_nor;
+	int addrMode;
+
+	pr_info("Initializing rtl838x_nor_driver\n");
+	if (!pdev->dev.of_node) {
+		dev_err(&pdev->dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL);
+	if (!rtl838x_nor)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, rtl838x_nor);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR((void *)rtl838x_nor->base))
+		return PTR_ERR((void *)rtl838x_nor->base);
+
+	pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base);
+	rtl838x_nor->dev = &pdev->dev;
+
+	/* only support one attached flash */
+	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
+	if (!flash_np) {
+		dev_err(&pdev->dev, "no SPI flash device to configure\n");
+		ret = -ENODEV;
+		goto nor_free;
+	}
+
+	/* Get the 3/4 byte address mode as configure by bootloader */
+	if (soc_info.family == RTL8390_FAMILY_ID)
+		addrMode = rtl8390_get_addr_mode(rtl838x_nor);
+	else
+		addrMode = rtl838x_get_addr_mode(rtl838x_nor);
+	pr_info("Address mode is %d bytes\n", addrMode);
+	if (addrMode == 4)
+		rtl838x_nor->fourByteMode = true;
+
+	ret = rtl838x_nor_init(rtl838x_nor, flash_np);
+
+nor_free:
+	return ret;
+}
+
+static int rtl838x_nor_drv_remove(struct platform_device *pdev)
+{
+/*	struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */
+	return 0;
+}
+
+static const struct of_device_id rtl838x_nor_of_ids[] = {
+	{ .compatible = "realtek,rtl838x-nor"},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids);
+
+static struct platform_driver rtl838x_nor_driver = {
+	.probe = rtl838x_nor_drv_probe,
+	.remove = rtl838x_nor_drv_remove,
+	.driver = {
+		.name = "rtl838x-nor",
+		.pm = NULL,
+		.of_match_table = rtl838x_nor_of_ids,
+	},
+};
+
+module_platform_driver(rtl838x_nor_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver");
--- a/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
+++ b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2009 Realtek Semiconductor Corp.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _RTL838X_SPI_H
+#define _RTL838X_SPI_H
+
+
+/*
+ * Register access macros
+ */
+
+#define spi_r32(reg)		__raw_readl(rtl838x_nor->base + reg)
+#define spi_w32(val, reg)	__raw_writel(val, rtl838x_nor->base + reg)
+#define spi_w32_mask(clear, set, reg)	\
+	spi_w32((spi_r32(reg) & ~(clear)) | (set), reg)
+
+#define SPI_WAIT_READY		do { \
+				} while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY))
+
+#define spi_w32w(val, reg)	do { \
+					__raw_writel(val, rtl838x_nor->base + reg); \
+					SPI_WAIT_READY; \
+				} while (0)
+
+#define SFCR   (0x00)			/*SPI Flash Configuration Register*/
+	#define SFCR_CLK_DIV(val)	((val)<<29)
+	#define SFCR_EnableRBO		(1<<28)
+	#define SFCR_EnableWBO		(1<<27)
+	#define SFCR_SPI_TCS(val)	((val)<<23) /*4 bit, 1111 */
+
+#define SFCR2  (0x04)	/*For memory mapped I/O */
+	#define SFCR2_SFCMD(val)	((val)<<24) /*8 bit, 1111_1111 */
+	#define SFCR2_SIZE(val)		((val)<<21) /*3 bit, 111 */
+	#define SFCR2_RDOPT		(1<<20)
+	#define SFCR2_CMDIO(val)	((val)<<18) /*2 bit, 11 */
+	#define SFCR2_ADDRIO(val)	((val)<<16) /*2 bit, 11 */
+	#define SFCR2_DUMMYCYCLE(val)	((val)<<13) /*3 bit, 111 */
+	#define SFCR2_DATAIO(val)	((val)<<11) /*2 bit, 11 */
+	#define SFCR2_HOLD_TILL_SFDR2	(1<<10)
+	#define SFCR2_GETSIZE(x)	(((x)&0x00E00000)>>21)
+
+#define SFCSR  (0x08)	/*SPI Flash Control&Status Register*/
+	#define SFCSR_SPI_CSB0		(1<<31)
+	#define SFCSR_SPI_CSB1		(1<<30)
+	#define SFCSR_LEN(val)		((val)<<28)  /*2 bits*/
+	#define SFCSR_SPI_RDY		(1<<27)
+	#define SFCSR_IO_WIDTH(val)	((val)<<25)  /*2 bits*/
+	#define SFCSR_CHIP_SEL		(1<<24)
+	#define SFCSR_CMD_BYTE(val)	((val)<<16)  /*8 bit, 1111_1111 */
+
+#define SFDR   (0x0C)	/*SPI Flash Data Register*/
+#define SFDR2  (0x10)	/*SPI Flash Data Register - for post SPI bootup setting*/
+	#define SPI_CS_INIT		(SFCSR_SPI_CSB0 | SFCSR_SPI_CSB1 | SPI_LEN1)
+	#define SPI_CS0			SFCSR_SPI_CSB0
+	#define SPI_CS1			SFCSR_SPI_CSB1
+	#define SPI_eCS0		((SFCSR_SPI_CSB1)) /*and SFCSR to active CS0*/
+	#define SPI_eCS1		((SFCSR_SPI_CSB0)) /*and SFCSR to active CS1*/
+
+	#define SPI_WIP (1)		/* Write In Progress */
+	#define SPI_WEL (1<<1)		/* Write Enable Latch*/
+	#define SPI_SST_QIO_WIP (1<<7)	/* SST QIO Flash Write In Progress */
+	#define SPI_LEN_INIT 0xCFFFFFFF /* and SFCSR to init   */
+	#define SPI_LEN4    0x30000000	/* or SFCSR to set */
+	#define SPI_LEN3    0x20000000	/* or SFCSR to set */
+	#define SPI_LEN2    0x10000000	/* or SFCSR to set */
+	#define SPI_LEN1    0x00000000	/* or SFCSR to set */
+	#define SPI_SETLEN(val) do {		\
+			SPI_REG(SFCSR) &= 0xCFFFFFFF;   \
+			SPI_REG(SFCSR) |= (val-1)<<28;	\
+		} while (0)
+/*
+ * SPI interface control
+ */
+#define RTL8390_SOC_SPI_MMIO_CONF (0x04)
+
+#define IOSTATUS_CIO_MASK (0x00000038)
+
+/* Chip select: bits 4-7*/
+#define CS0 (1<<4)
+#define R_MODE 0x04
+
+/* io_status */
+#define IO1 (1<<0)
+#define IO2 (1<<1)
+#define CIO1 (1<<3)
+#define CIO2 (1<<4)
+#define CMD_IO1 (1<<6)
+#define W_ADDR_IO1 ((1)<<12)
+#define R_ADDR_IO2 ((2)<<9)
+#define R_DATA_IO2 ((2)<<15)
+#define W_DATA_IO1 ((1)<<18)
+
+/* Commands */
+#define SPI_C_RSTQIO 0xFF
+
+#define SPI_MAX_TRANSFER_SIZE 256
+
+#endif		/* _RTL838X_SPI_H */
--- a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h
+++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _RTL838X_H
+#define _RTL838X_H
+
+#include <net/dsa.h>
+
+/*
+ * Register definition
+ */
+#define RTL838X_CPU_PORT			28
+#define RTL839X_CPU_PORT			52
+
+#define RTL838X_MAC_PORT_CTRL(port)		(0xd560 + (((port) << 7)))
+#define RTL839X_MAC_PORT_CTRL(port)		(0x8004 + (((port) << 7)))
+#define RTL838X_RST_GLB_CTRL_0			(0x003c)
+#define RTL838X_MAC_FORCE_MODE_CTRL		(0xa104)
+#define RTL839X_MAC_FORCE_MODE_CTRL		(0x02bc)
+
+#define RTL838X_DMY_REG31			(0x3b28)
+#define RTL838X_SDS_MODE_SEL			(0x0028)
+#define RTL838X_SDS_CFG_REG			(0x0034)
+#define RTL838X_INT_MODE_CTRL			(0x005c)
+#define RTL838X_CHIP_INFO			(0x00d8)
+#define RTL839X_CHIP_INFO			(0x0ff4)
+#define RTL838X_SDS4_REG28			(0xef80)
+#define RTL838X_SDS4_DUMMY0			(0xef8c)
+#define RTL838X_SDS5_EXT_REG6			(0xf18c)
+#define RTL838X_PORT_ISO_CTRL(port)		(0x4100 + ((port) << 2))
+#define RTL839X_PORT_ISO_CTRL(port)		(0x1400 + ((port) << 3))
+#define RTL8380_SDS4_FIB_REG0			(0xF800)
+#define RTL838X_STAT_PORT_STD_MIB		(0x1200)
+#define RTL839X_STAT_PORT_STD_MIB		(0xC000)
+#define RTL838X_STAT_RST			(0x3100)
+#define RTL839X_STAT_RST			(0xF504)
+#define RTL838X_STAT_PORT_RST			(0x3104)
+#define RTL839X_STAT_PORT_RST			(0xF508)
+#define RTL838X_STAT_CTRL			(0x3108)
+#define RTL839X_STAT_CTRL			(0x04cc)
+
+/* Registers of the internal Serdes of the 8380 */
+#define MAPLE_SDS4_REG0r			RTL838X_SDS4_REG28
+#define MAPLE_SDS5_REG0r			(RTL838X_SDS4_REG28 + 0x100)
+#define MAPLE_SDS4_REG3r			RTL838X_SDS4_DUMMY0
+#define MAPLE_SDS5_REG3r			(RTL838X_SDS4_REG28 + 0x100)
+#define MAPLE_SDS4_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x880)
+#define MAPLE_SDS5_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x980)
+
+/* VLAN registers */
+#define RTL838X_VLAN_PROFILE(idx)		(0x3A88 + ((idx) << 2))
+#define RTL838X_VLAN_PORT_EGR_FLTR		(0x3A84)
+#define RTL838X_VLAN_PORT_PB_VLAN(port)		(0x3C00 + ((port) << 2))
+#define RTL838X_VLAN_PORT_IGR_FLTR_0		(0x3A7C)
+#define RTL838X_VLAN_PORT_IGR_FLTR_1		(0x3A7C + 4)
+
+/* Table 0/1 access registers */
+#define RTL838X_TBL_ACCESS_CTRL_0		(0x6914)
+#define RTL838X_TBL_ACCESS_DATA_0(idx)		(0x6918 + ((idx) << 2))
+#define RTL838X_TBL_ACCESS_CTRL_1		(0xA4C8)
+#define RTL838X_TBL_ACCESS_DATA_1(idx)		(0xA4CC + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_CTRL_0		(0x1190)
+#define RTL839X_TBL_ACCESS_DATA_0(idx)		(0x1194 + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_CTRL_1		(0x6b80)
+#define RTL839X_TBL_ACCESS_DATA_1(idx)		(0x6b84 + ((idx) << 2))
+
+/* MAC handling */
+#define RTL838X_MAC_LINK_STS			(0xa188)
+#define RTL839X_MAC_LINK_STS			(0x0390)
+#define RTL838X_MAC_LINK_SPD_STS(port)		(0xa190 + (((port >> 4) << 2)))
+#define RTL838X_MAC_LINK_DUP_STS		(0xa19c)
+#define RTL838X_MAC_TX_PAUSE_STS		(0xa1a0)
+#define RTL838X_MAC_RX_PAUSE_STS		(0xa1a4)
+#define RTL838X_EEE_TX_TIMER_GIGA_CTRL		(0xaa04)
+#define RTL838X_EEE_TX_TIMER_GELITE_CTRL	(0xaa08)
+
+/* MAC link state bits */
+#define FORCE_EN				(1 << 0)
+#define FORCE_LINK_EN				(1 << 1)
+#define NWAY_EN					(1 << 2)
+#define DUPLX_MODE				(1 << 3)
+#define TX_PAUSE_EN				(1 << 6)
+#define RX_PAUSE_EN				(1 << 7)
+
+/* EEE */
+#define RTL838X_MAC_EEE_ABLTY			(0xa1a8)
+#define RTL838X_EEE_PORT_TX_EN			(0x014c)
+#define RTL838X_EEE_PORT_RX_EN			(0x0150)
+#define RTL838X_EEE_CLK_STOP_CTRL		(0x0148)
+
+/* L2 functionality */
+#define RTL838X_L2_CTRL_0			(0x3200)
+#define RTL839X_L2_CTRL_0			(0x3800)
+#define RTL838X_L2_CTRL_1			(0x3204)
+#define RTL839X_L2_CTRL_1			(0x3804)
+#define RTL838X_L2_PORT_AGING_OUT		(0x3358)
+#define RTL839X_L2_PORT_AGING_OUT		(0x3b74)
+#define RTL838X_TBL_ACCESS_L2_CTRL		(0x6900)
+#define RTL839X_TBL_ACCESS_L2_CTRL		(0x1180)
+#define RTL838X_TBL_ACCESS_L2_DATA(idx)		(0x6908 + ((idx) << 2))
+#define RTL838X_TBL_ACCESS_L2_DATA(idx)		(0x6908 + ((idx) << 2))
+#define RTL838X_L2_TBL_FLUSH_CTRL		(0x3370)
+#define RTL839X_L2_TBL_FLUSH_CTRL		(0x3ba0)
+
+/* Port Mirroring */
+#define RTL838X_MIR_CTRL(grp)			(0x5D00 + (((grp) << 2)))
+#define RTL838X_MIR_DPM_CTRL(grp)		(0x5D20 + (((grp) << 2)))
+#define RTL838X_MIR_SPM_CTRL(grp)		(0x5D10 + (((grp) << 2)))
+
+enum phy_type {
+	PHY_NONE = 0,
+	PHY_RTL838X_SDS = 1,
+	PHY_RTL8218B_INT = 2,
+	PHY_RTL8218B_EXT = 3,
+	PHY_RTL8214FC = 4
+};
+
+struct rtl838x_port {
+	bool enable;
+	u64 pm;
+	u16 pvid;
+	bool eee_enabled;
+	enum phy_type phy;
+};
+
+struct rtl838x_vlan_info {
+	u64 untagged_ports;
+	u64 tagged_ports;
+	u32 vlan_conf;
+};
+
+struct rtl838x_switch_priv;
+
+struct rtl838x_reg {
+	void (*mask_port_reg)(u64 clear, u64 set, int reg);
+	void (*set_port_reg)(u64 set, int reg);
+	u64 (*get_port_reg)(int reg);
+	int stat_port_rst;
+	int stat_rst;
+	int (*stat_port_std_mib)(int p);
+	void (*mask_port_iso_ctrl)(u64 clear, u64 set, int port);
+	void (*set_port_iso_ctrl)(u64 set, int port);
+	int l2_ctrl_0;
+	int l2_ctrl_1;
+	int l2_port_aging_out;
+	int smi_poll_ctrl;
+	int l2_tbl_flush_ctrl;
+	void (*exec_tbl0_cmd)(u32 cmd);
+	void (*exec_tbl1_cmd)(u32 cmd);
+	int (*tbl_access_data_0)(int i);
+	int isr_glb_src;
+	int isr_port_link_sts_chg;
+	int imr_port_link_sts_chg;
+	int imr_glb;
+	void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
+	void (*vlan_set_tagged)(u32 vlan, u64 portmask, u32 conf);
+	void (*vlan_set_untagged)(u32 vlan, u64 portmask);
+	int  (*mac_force_mode_ctrl)(int port);
+	int rst_glb_ctrl;
+};
+
+struct rtl838x_switch_priv {
+	/* Switch operation */
+	struct dsa_switch *ds;
+	struct device *dev;
+	u16 id;
+	u16 family_id;
+	char version;
+	struct rtl838x_port ports[54]; /* TODO: correct size! */
+	struct mutex reg_mutex;
+	int link_state_irq;
+	int mirror_group_ports[4];
+	struct mii_bus *mii_bus;
+	const struct rtl838x_reg *r;
+	u8 cpu_port;
+	u8 port_mask;
+};
+
+extern struct rtl838x_soc_info soc_info;
+extern void rtl8380_sds_rst(int mac);
+
+extern int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+extern int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+extern int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+extern int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+extern int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val);
+extern int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val);
+
+#endif /* _RTL838X_H */
--- a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c
+++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c
--- a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c
+++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c
--- a/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c
--- a/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h
+++ b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _RTL838X_ETH_H
+#define _RTL838X_ETH_H
+
+/*
+ * Register definition
+ */
+
+#define RTL838X_CPU_PORT			28
+#define RTL839X_CPU_PORT			52
+
+#define RTL838X_MAC_PORT_CTRL			(0xd560)
+#define RTL839X_MAC_PORT_CTRL			(0x8004)
+#define RTL838X_DMA_IF_INTR_STS			(0x9f54)
+#define RTL839X_DMA_IF_INTR_STS			(0x7868)
+#define RTL838X_DMA_IF_INTR_MSK			(0x9f50)
+#define RTL839X_DMA_IF_INTR_MSK			(0x7864)
+#define RTL838X_DMA_IF_CTRL			(0x9f58)
+#define RTL839X_DMA_IF_CTRL			(0x786c)
+#define RTL838X_RST_GLB_CTRL_0			(0x003c)
+#define RTL838X_MAC_FORCE_MODE_CTRL		(0xa104)
+#define RTL839X_MAC_FORCE_MODE_CTRL		(0x02bc)
+
+/* MAC address settings */
+#define RTL838X_MAC				(0xa9ec)
+#define RTL839X_MAC				(0x02b4)
+#define RTL838X_MAC_ALE				(0x6b04)
+#define RTL838X_MAC2				(0xa320)
+
+#define RTL838X_DMA_RX_BASE			(0x9f00)
+#define RTL839X_DMA_RX_BASE			(0x780c)
+#define RTL838X_DMA_TX_BASE			(0x9f40)
+#define RTL839X_DMA_TX_BASE			(0x784c)
+#define RTL838X_DMA_IF_RX_RING_SIZE		(0xB7E4)
+#define RTL839X_DMA_IF_RX_RING_SIZE		(0x6038)
+#define RTL838X_DMA_IF_RX_RING_CNTR		(0xB7E8)
+#define RTL839X_DMA_IF_RX_RING_CNTR		(0x603c)
+#define RTL838X_DMA_IF_RX_CUR			(0x9F20)
+#define RTL839X_DMA_IF_RX_CUR			(0x782c)
+
+#define RTL838X_DMY_REG31			(0x3b28)
+#define RTL838X_SDS_MODE_SEL			(0x0028)
+#define RTL838X_SDS_CFG_REG			(0x0034)
+#define RTL838X_INT_MODE_CTRL			(0x005c)
+#define RTL838X_CHIP_INFO			(0x00d8)
+#define RTL838X_SDS4_REG28			(0xef80)
+#define RTL838X_SDS4_DUMMY0			(0xef8c)
+#define RTL838X_SDS5_EXT_REG6			(0xf18c)
+#define RTL838X_PORT_ISO_CTRL(port)		(0x4100 + ((port) << 2))
+#define RTL838X_STAT_PORT_STD_MIB(port)		(0x1200 + (((port) << 8)))
+#define RTL838X_STAT_RST			(0x3100)
+#define RTL838X_STAT_CTRL			(0x3108)
+
+/* Registers of the internal Serdes of the 8380 */
+#define MAPLE_SDS4_REG0r			RTL838X_SDS4_REG28
+#define MAPLE_SDS5_REG0r			(RTL838X_SDS4_REG28 + 0x100)
+#define MAPLE_SDS4_REG3r			RTL838X_SDS4_DUMMY0
+#define MAPLE_SDS5_REG3r			(RTL838X_SDS4_REG28 + 0x100)
+#define MAPLE_SDS4_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x880)
+#define MAPLE_SDS5_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x980)
+
+/* VLAN registers */
+#define RTL838X_VLAN_PROFILE(idx)		(0x3A88 + ((idx) << 2))
+#define RTL838X_VLAN_PORT_EGR_FLTR		(0x3A84)
+#define RTL838X_VLAN_PORT_PB_VLAN(port)		(0x3C00 + ((port) << 2))
+#define RTL838X_VLAN_PORT_IGR_FLTR_0		(0x3A7C)
+#define RTL838X_VLAN_PORT_IGR_FLTR_1		(0x3A7C + 4)
+#define RTL838X_TBL_ACCESS_CTRL_0		(0x6914)
+#define RTL838X_TBL_ACCESS_DATA_0(idx)		(0x6918 + ((idx) << 2))
+#define RTL838X_TBL_ACCESS_CTRL_1		(0xA4C8)
+#define RTL838X_TBL_ACCESS_DATA_1(idx)		(0xA4CC + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_L2_CTRL		(0x1180)
+#define RTL839X_TBL_ACCESS_L2_DATA(idx)		(0x1184 + ((idx) << 2))
+/* MAC handling */
+#define RTL838X_MAC_LINK_STS			(0xa188)
+#define RTL839X_MAC_LINK_STS			(0x0390)
+#define RTL838X_MAC_LINK_SPD_STS		(0xa190)
+#define RTL839X_MAC_LINK_SPD_STS		(0x03a0)
+#define RTL838X_MAC_LINK_DUP_STS		(0xa19c)
+#define RTL839X_MAC_LINK_DUP_STS		(0x03b0)
+// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
+#define RTL838X_MAC_TX_PAUSE_STS		(0xa1a0)
+#define RTL839X_MAC_TX_PAUSE_STS		(0x03b8)
+#define RTL838X_MAC_RX_PAUSE_STS		(0xa1a4)
+#define RTL839X_MAC_RX_PAUSE_STS		(0x03c0)
+#define RTL838X_EEE_TX_TIMER_GIGA_CTRL		(0xaa04)
+#define RTL838X_EEE_TX_TIMER_GELITE_CTRL	(0xaa08)
+#define RTL839X_MAC_GLB_CTRL			(0x02a8)
+#define RTL839X_SCHED_LB_TICK_TKN_CTRL		(0x60f8)
+
+#define RTL838X_L2_TBL_FLUSH_CTRL		(0x3370)
+#define RTL839X_L2_TBL_FLUSH_CTRL		(0x3ba0)
+
+/* MAC link state bits */
+#define FORCE_EN				(1 << 0)
+#define FORCE_LINK_EN				(1 << 1)
+#define NWAY_EN					(1 << 2)
+#define DUPLX_MODE				(1 << 3)
+#define TX_PAUSE_EN				(1 << 6)
+#define RX_PAUSE_EN				(1 << 7)
+
+inline int rtl838x_mac_port_ctrl(int p)
+{
+	return RTL838X_MAC_PORT_CTRL + (p << 7);
+}
+
+inline int rtl839x_mac_port_ctrl(int p)
+{
+	return RTL839X_MAC_PORT_CTRL + (p << 7);
+}
+
+static inline int rtl838x_mac_force_mode_ctrl(int p)
+{
+	return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
+}
+
+static inline int rtl839x_mac_force_mode_ctrl(int p)
+{
+	return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
+}
+
+inline int rtl838x_dma_rx_base(int i)
+{
+	return RTL838X_DMA_RX_BASE + (i << 2);
+}
+
+inline int rtl839x_dma_rx_base(int i)
+{
+	return RTL839X_DMA_RX_BASE + (i << 2);
+}
+
+inline int rtl838x_dma_tx_base(int i)
+{
+	return RTL838X_DMA_TX_BASE + (i << 2);
+}
+
+inline int rtl839x_dma_tx_base(int i)
+{
+	return RTL839X_DMA_TX_BASE + (i << 2);
+}
+
+inline int rtl838x_dma_if_rx_ring_size(int i)
+{
+	return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
+}
+
+inline int rtl839x_dma_if_rx_ring_size(int i)
+{
+	return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
+}
+
+inline int rtl838x_dma_if_rx_ring_cntr(int i)
+{
+	return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
+}
+
+inline int rtl839x_dma_if_rx_ring_cntr(int i)
+{
+	return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
+}
+
+
+inline int rtl838x_dma_if_rx_cur(int i)
+{
+	return RTL838X_DMA_IF_RX_CUR + (i << 2);
+}
+
+inline int rtl839x_dma_if_rx_cur(int i)
+{
+	return RTL839X_DMA_IF_RX_CUR + (i << 2);
+}
+
+inline u32 rtl838x_get_mac_link_sts(int port)
+{
+	return (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port));
+}
+
+inline u32 rtl839x_get_mac_link_sts(int p)
+{
+	return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & (1 << p));
+}
+
+inline u32 rtl838x_get_mac_link_dup_sts(int port)
+{
+	return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port));
+}
+
+inline u32 rtl839x_get_mac_link_dup_sts(int p)
+{
+	return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & (1 << p));
+}
+
+inline u32 rtl838x_get_mac_link_spd_sts(int port)
+{
+	int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
+	u32 speed = sw_r32(r);
+
+	speed >>= (port % 16) << 1;
+	return (speed & 0x3);
+}
+
+inline u32 rtl839x_get_mac_link_spd_sts(int port)
+{
+	int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
+	u32 speed = sw_r32(r);
+
+	speed >>= (port % 16) << 1;
+	return (speed & 0x3);
+}
+
+inline u32 rtl838x_get_mac_rx_pause_sts(int port)
+{
+	return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
+}
+
+inline u32 rtl839x_get_mac_rx_pause_sts(int p)
+{
+	return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
+}
+
+inline u32 rtl838x_get_mac_tx_pause_sts(int port)
+{
+	return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
+}
+
+inline u32 rtl839x_get_mac_tx_pause_sts(int p)
+{
+	return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
+}
+
+
+struct rtl838x_reg {
+	int (*mac_port_ctrl)(int port);
+	int dma_if_intr_sts;
+	int dma_if_intr_msk;
+	int dma_if_ctrl;
+	int  (*mac_force_mode_ctrl)(int port);
+	int  (*dma_rx_base)(int ring);
+	int  (*dma_tx_base)(int ring);
+	int  (*dma_if_rx_ring_size)(int ring);
+	int  (*dma_if_rx_ring_cntr)(int ring);
+	int  (*dma_if_rx_cur)(int ring);
+	int rst_glb_ctrl;
+	u32 (*get_mac_link_sts)(int port);
+	u32 (*get_mac_link_dup_sts)(int port);
+	u32 (*get_mac_link_spd_sts)(int port);
+	u32 (*get_mac_rx_pause_sts)(int port);
+	u32 (*get_mac_tx_pause_sts)(int port);
+	int mac;
+	int l2_tbl_flush_ctrl;
+};
+
+int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+
+extern int rtl8380_sds_power(int mac, int val);
+
+#endif /* _RTL838X_ETH_H */
--- a/target/linux/rtl838x/image/Makefile
+++ b/target/linux/rtl838x/image/Makefile
@@ -0,0 +1,44 @@
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+KERNEL_LOADADDR = 0x80000000
+KERNEL_ENTRY = 0x80000400
+
+define Build/custom-uimage
+	mkimage -A $(LINUX_KARCH) \
+		-O linux -T kernel \
+		-C gzip -a $(KERNEL_LOADADDR) $(if $(UIMAGE_MAGIC),-M $(UIMAGE_MAGIC),) \
+		-e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \
+		-n '$(1)' -d $@ $@.new
+	mv $@.new $@
+endef
+
+
+define Device/Default
+  PROFILES = Default
+  KERNEL := kernel-bin | append-dtb | gzip | uImage gzip
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | uImage gzip
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_DTS = $$(SOC)_$(1)
+  SUPPORTED_DEVICES := $(subst _,$(comma),$(1))
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \
+	append-metadata | check-size
+endef
+
+define Device/allnet_all-sg8208m
+  SOC := rtl8382
+  IMAGE_SIZE := 7168k
+  DEVICE_VENDOR := ALLNET
+  DEVICE_MODEL := ALL-SG8208M
+  UIMAGE_MAGIC := 0x00000006
+  KERNEL := kernel-bin | append-dtb | gzip | custom-uimage 2.2.2.0
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | custom-uimage 2.2.2.0
+  DEVICE_PACKAGES := ip-full ip-bridge kmod-gpio-button-hotplug tc
+endef
+TARGET_DEVICES += allnet_all-sg8208m
+
+$(eval $(call BuildImage))
--- a/Show More
+++ b/Show More