33 lines
1.4 KiB
Diff
33 lines
1.4 KiB
Diff
From aba7987a536cee67fb0cb724099096fd8f8f5350 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Thu, 12 Jun 2025 00:47:48 +0300
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Subject: [PATCH] arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576
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As with the RK3588 SoC, the HDMI PHY PLL on RK3576 can be used as a more
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accurate pixel clock source for VOP2, which is actually mandatory to
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ensure proper support for display modes handling.
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Add the missing #clock-cells property to allow using the clock provider
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functionality of HDMI PHY.
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Fixes: ad0ea230ab2a ("arm64: dts: rockchip: Add hdmi for rk3576")
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Cc: stable@vger.kernel.org
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-2-4b11007d8675@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -2407,6 +2407,7 @@
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reg = <0x0 0x2b000000 0x0 0x2000>;
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clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
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clock-names = "ref", "apb";
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+ #clock-cells = <0>;
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resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
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<&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
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reset-names = "apb", "init", "cmn", "lane";
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