53 lines
1.7 KiB
Diff
53 lines
1.7 KiB
Diff
From 21bc1a7fcea4635a49f6b2eff3e4c661e80e8f43 Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko@sntech.de>
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Date: Mon, 7 Jul 2025 18:49:03 +0200
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Subject: [PATCH] arm64: dts: rockchip: add mipi-dcphy to rk3576
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Add the MIPI-DC-phy node to the RK3576, that will be used by the one
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DSI2 controller and hopefully in some future also for camera input.
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/20250707164906.1445288-11-heiko@sntech.de
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 22 ++++++++++++++++++++++
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1 file changed, 22 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -966,6 +966,12 @@
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reg = <0x0 0x26032000 0x0 0x100>;
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};
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+ mipidcphy_grf: syscon@26034000 {
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+ compatible = "rockchip,rk3576-dcphy-grf", "syscon";
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+ reg = <0x0 0x26034000 0x0 0x2000>;
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+ clocks = <&cru PCLK_PMUPHY_ROOT>;
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+ };
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+
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vo1_grf: syscon@26036000 {
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compatible = "rockchip,rk3576-vo1-grf", "syscon";
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reg = <0x0 0x26036000 0x0 0x100>;
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@@ -2563,6 +2569,22 @@
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status = "disabled";
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};
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+ mipidcphy: phy@2b020000 {
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+ compatible = "rockchip,rk3576-mipi-dcphy";
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+ reg = <0x0 0x2b020000 0x0 0x10000>;
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+ clocks = <&cru PCLK_MIPI_DCPHY>,
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+ <&cru CLK_PHY_REF_SRC>;
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+ clock-names = "pclk", "ref";
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+ resets = <&cru SRST_M_MIPI_DCPHY>,
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+ <&cru SRST_P_MIPI_DCPHY>,
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+ <&cru SRST_P_DCPHY_GRF>,
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+ <&cru SRST_S_MIPI_DCPHY>;
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+ reset-names = "m_phy", "apb", "grf", "s_phy";
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+ rockchip,grf = <&mipidcphy_grf>;
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+ #phy-cells = <1>;
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+ status = "disabled";
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+ };
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+
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combphy0_ps: phy@2b050000 {
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compatible = "rockchip,rk3576-naneng-combphy";
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reg = <0x0 0x2b050000 0x0 0x100>;
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