28 lines
1.2 KiB
Diff
28 lines
1.2 KiB
Diff
From aadaa27956e3430217d9e6b8af5880e39b05b961 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Sun, 23 Feb 2025 11:31:39 +0200
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Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
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Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
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provider support"), the HDMI PHY PLL can be used as an alternative and
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more accurate pixel clock source for VOP2 to improve display modes
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handling on RK3588 SoC.
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Add the missing #clock-cells property to allow using the clock provider
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functionality of HDMI1 PHY.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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@@ -446,6 +446,7 @@
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reg = <0x0 0xfed70000 0x0 0x2000>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
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clock-names = "ref", "apb";
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+ #clock-cells = <0>;
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#phy-cells = <0>;
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resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
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<&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
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