93 lines
3.3 KiB
Diff
93 lines
3.3 KiB
Diff
From 263fac6b09b42a1b077c21354370d38758237ab0 Mon Sep 17 00:00:00 2001
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From: Yao Zi <ziyao@disroot.org>
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Date: Thu, 18 Sep 2025 15:30:56 +0000
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Subject: [PATCH] arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528
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Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC
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doesn't provide a separate MSI controller, thus the one integrated in
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designware PCIe IP must be used.
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Signed-off-by: Yao Zi <ziyao@disroot.org>
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Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
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Link: https://patch.msgid.link/20250918153057.56023-3-ziyao@disroot.org
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 +++++++++++++++++++++++++++++++-
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1 file changed, 55 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@@ -7,6 +7,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rockchip,rk3528-cru.h>
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#include <dt-bindings/power/rockchip,rk3528-power.h>
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@@ -294,10 +295,63 @@
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soc {
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compatible = "simple-bus";
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- ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
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+ ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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+ pcie: pcie@fe000000 {
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+ compatible = "rockchip,rk3528-pcie",
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+ "rockchip,rk3568-pcie";
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+ reg = <0x0 0xfe000000 0x0 0x400000>,
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+ <0x0 0xfe4f0000 0x0 0x010000>,
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+ <0x0 0xfc000000 0x0 0x100000>;
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+ reg-names = "dbi", "apb", "config";
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+ bus-range = <0x0 0xff>;
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+ clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
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+ <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
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+ <&cru CLK_PCIE_AUX>;
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+ clock-names = "aclk_mst", "aclk_slv",
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+ "aclk_dbi", "pclk",
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+ "aux";
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+ device_type = "pci";
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+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
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+ "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
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+ <0 0 0 2 &pcie_intc 1>,
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+ <0 0 0 3 &pcie_intc 2>,
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+ <0 0 0 4 &pcie_intc 3>;
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+ linux,pci-domain = <0>;
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+ max-link-speed = <2>;
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+ num-lanes = <1>;
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+ phys = <&combphy PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy";
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+ power-domains = <&power RK3528_PD_VPU>;
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+ ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>,
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+ <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>,
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+ <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
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+ resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>;
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+ reset-names = "pwr", "pipe";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ status = "disabled";
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+
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+ pcie_intc: legacy-interrupt-controller {
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+ interrupt-controller;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ };
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+ };
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+
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gic: interrupt-controller@fed01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xfed01000 0 0x1000>,
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