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sunxi: add PCIe support for Allwinner A523

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Patches are taken from Armbian.

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2026-07-03 17:17:14 +08:00
parent 15a751772f
commit 5f89c80883
15 changed files with 7366 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/generic/pending-6.18/401-mtd-spinand-fmsh-add-support-for-FM25G0102B.patch → target/linux/generic/backport-6.18/436-v7.3-mtd-spinand-fmsh-add-support-for-FM25G-01-02-B.patch
+9 -19
View File
@@ -1,7 +1,7 @@
From d5a5c9eb2ee9ff5b4cc0be15ac7f4879d4c2f247 Mon Sep 17 00:00:00 2001
From: Ziyang Huang <hzyitc@outlook.com>
To: miquel.raynal@bootlin.com
Subject: [PATCH v3] mtd: spinand: fmsh: add support for FM25G{01,02}B
Date: Sun, 31 May 2026 21:05:17 +0800
Date: Tue, 23 Jun 2026 22:54:22 +0800
Subject: [PATCH] mtd: spinand: fmsh: add support for FM25G{01,02}B
Add support for FudanMicro FM25G01B SPI NAND and FudanMicro FM25G02B SPI
NAND.
@@ -10,19 +10,10 @@ FM25G01B datasheet: https://www.fmsh.com/nvm/FM25G01B_ds_eng.pdf
FM25G02B datasheet: https://www.fmsh.com/nvm/FM25G02B_ds_eng.pdf
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
Link: https://lore.kernel.org/all/SEYPR01MB58821E380C5DD8F7B3FFDA23C9142@SEYPR01MB5882.apcprd01.prod.exchangelabs.com/
[Fix chip names in the commit message, mask macro in the switch operator]
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Changes since v2:
More verbose commit message.
Use only one section in fm25g01b_ooblayout_free().
Changes since v1:
Fix copy-paste issue. (Correct FM25G01B size.)
drivers/mtd/nand/spi/fmsh.c | 96 +++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
drivers/mtd/nand/spi/fmsh.c | 95 +++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)
--- a/drivers/mtd/nand/spi/fmsh.c
+++ b/drivers/mtd/nand/spi/fmsh.c
@@ -43,11 +34,10 @@ Changes since v1:
#define FM25S01BI3_STATUS_ECC_MASK (7 << 4)
#define FM25S01BI3_STATUS_ECC_NO_BITFLIPS (0 << 4)
#define FM25S01BI3_STATUS_ECC_1_3_BITFLIPS (1 << 4)
@@ -34,6 +44,67 @@ static SPINAND_OP_VARIANTS(update_cache_
@@ -34,6 +44,66 @@ static SPINAND_OP_VARIANTS(update_cache_
SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0),
SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0));
+
+static int fm25g01b_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
@@ -111,7 +101,7 @@ Changes since v1:
static int fm25s01a_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -102,6 +173,11 @@ static int fm25s01bi3_ooblayout_free(str
@@ -102,6 +172,11 @@ static int fm25s01bi3_ooblayout_free(str
return 0;
}
@@ -123,7 +113,7 @@ Changes since v1:
static const struct mtd_ooblayout_ops fm25s01a_ooblayout = {
.ecc = fm25s01a_ooblayout_ecc,
.free = fm25s01a_ooblayout_free,
@@ -113,6 +189,26 @@ static const struct mtd_ooblayout_ops fm
@@ -113,6 +188,26 @@ static const struct mtd_ooblayout_ops fm
};
static const struct spinand_info fmsh_spinand_table[] = {
target/linux/generic/hack-6.18/400-mtd-spinand-Support-fmsh.patch
+2 -2
View File
@@ -17,7 +17,7 @@ Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
--- a/drivers/mtd/nand/spi/fmsh.c
+++ b/drivers/mtd/nand/spi/fmsh.c
@@ -188,6 +188,115 @@ static const struct mtd_ooblayout_ops fm
@@ -187,6 +187,115 @@ static const struct mtd_ooblayout_ops fm
.free = fm25s01bi3_ooblayout_free,
};
@@ -133,7 +133,7 @@ Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
static const struct spinand_info fmsh_spinand_table[] = {
SPINAND_INFO("FM25G01B",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xd1),
@@ -228,6 +337,51 @@ static const struct spinand_info fmsh_sp
@@ -227,6 +336,51 @@ static const struct spinand_info fmsh_sp
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25s01bi3_ooblayout,
fm25s01bi3_ecc_get_status)),
target/linux/sunxi/cortexa53/config-6.18
+23 -2
View File
@@ -45,6 +45,7 @@ CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA=y
CONFIG_ARM_SMMU_V3=y
# CONFIG_ARM_SMMU_V3_SVA is not set
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AW_INNO_COMBOPHY=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
@@ -63,8 +64,8 @@ CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_NEED_SYNC=y
CONFIG_DWMAC_SUN8I=y
CONFIG_DWMAC_SUN55I=y
CONFIG_DWMAC_SUN8I=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FRAME_POINTER=y
CONFIG_FUNCTION_ALIGNMENT=4
@@ -78,6 +79,7 @@ CONFIG_GENERIC_MSI_IRQ=y
CONFIG_HAS_IOPORT=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
# CONFIG_HOTPLUG_PCI_PCIE is not set
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
@@ -98,6 +100,22 @@ CONFIG_NO_IOPORT_MAP=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIE_DW_DEBUGFS is not set
CONFIG_PCIE_DW_PLAT_HOST=y
# CONFIG_PCIE_SUN55I_NONE is not set
CONFIG_PCIE_SUN55I_RC=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_PINCTRL_SUN50I_A100=y
@@ -140,6 +158,7 @@ CONFIG_SUN50I_IOMMU=y
CONFIG_SUN55I_A523_CCU=y
CONFIG_SUN55I_A523_MCU_CCU=y
CONFIG_SUN55I_A523_R_CCU=y
CONFIG_SUN55I_IOMMU=y
CONFIG_SUN55I_PCK600=y
CONFIG_SUN6I_RTC_CCU=y
CONFIG_SUN6I_R_INTC=y
@@ -147,14 +166,16 @@ CONFIG_SUNXI_NMI_INTC=y
CONFIG_SURFACE_PLATFORMS=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THREAD_INFO_IN_TASK=y
# CONFIG_UACCE is not set
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
# CONFIG_UACCE is not set
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_USB_MUSB_DUAL_ROLE=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB_PHY=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_VDSO_GETRANDOM=y
CONFIG_VMAP_STACK=y
target/linux/sunxi/cortexa53/target.mk
+1 -1
View File
@@ -8,4 +8,4 @@ ARCH:=aarch64
BOARDNAME:=Allwinner A64/H5/H6/H616/H618
CPU_TYPE:=cortex-a53
KERNELNAME:=Image dtbs
FEATURES+=fpu
FEATURES+=fpu pci pcie
target/linux/sunxi/patches-6.18/121-clk-a523-add-initial-cpufreq-support.patch → target/linux/sunxi/patches-6.18/121-01-clk-a523-add-initial-cpufreq-support.patch
View File
target/linux/sunxi/patches-6.18/121-02-clk-gate-add-regmap-gate-support.patch
+244
View File
@@ -0,0 +1,244 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Fri, 10 Jun 2022 18:20:29 +0100
Subject: clk: gate: add support for regmap based gates
While we have nice wrappers for simple bit-flip MMIO based clock gates,
a single bit to toggle in a regmap still requires to write a lot of clock
framework boilerplate.
Support generic wrappers for regmap based clock gates, by adding them to
the existing clock-gates.c file. Since a read-modify-write operation in a
regmap can be much more complex than a readl/writel pair, we cannot use
the .enable/.disable ops members, but do the actual flipping already in
.prepare/.unprepare, where we can sleep. Also we cannot provide an
.is_enabled function, since this must not sleep as well.
On the upside all the locking for the r/m/w operation is provided by
regmap already, so we can skip that.
The rest of the CCF boilerplate code can be shared.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/clk/clk-gate.c | 60 +++++++++-
include/linux/clk-provider.h | 36 +++++-
2 files changed, 89 insertions(+), 7 deletions(-)
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -9,6 +9,7 @@
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/module.h>
+#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
@@ -124,11 +125,42 @@ const struct clk_ops clk_gate_ops = {
};
EXPORT_SYMBOL_GPL(clk_gate_ops);
+static int clk_gate_regmap_setclrbit(struct clk_hw *hw, bool enable)
+{
+ struct clk_gate *gate = to_clk_gate(hw);
+ bool set = gate->flags & CLK_GATE_SET_TO_DISABLE;
+
+ set ^= enable;
+
+ if (set)
+ return regmap_set_bits(gate->regmap, gate->regmap_offs,
+ BIT(gate->bit_idx));
+ else
+ return regmap_clear_bits(gate->regmap, gate->regmap_offs,
+ BIT(gate->bit_idx));
+}
+
+static int clk_gate_regmap_prepare(struct clk_hw *hw)
+{
+ return clk_gate_regmap_setclrbit(hw, true);
+}
+
+static void clk_gate_regmap_unprepare(struct clk_hw *hw)
+{
+ clk_gate_regmap_setclrbit(hw, false);
+}
+
+const struct clk_ops clk_gate_regmap_ops = {
+ .prepare = clk_gate_regmap_prepare,
+ .unprepare = clk_gate_regmap_unprepare,
+};
+
struct clk_hw *__clk_hw_register_gate(struct device *dev,
struct device_node *np, const char *name,
const char *parent_name, const struct clk_hw *parent_hw,
const struct clk_parent_data *parent_data,
unsigned long flags,
+ struct regmap *regmap, unsigned int regmap_offs,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock)
{
@@ -150,7 +182,10 @@ struct clk_hw *__clk_hw_register_gate(st
return ERR_PTR(-ENOMEM);
init.name = name;
- init.ops = &clk_gate_ops;
+ if (regmap)
+ init.ops = &clk_gate_regmap_ops;
+ else
+ init.ops = &clk_gate_ops;
init.flags = flags;
init.parent_names = parent_name ? &parent_name : NULL;
init.parent_hws = parent_hw ? &parent_hw : NULL;
@@ -162,6 +197,8 @@ struct clk_hw *__clk_hw_register_gate(st
/* struct clk_gate assignments */
gate->reg = reg;
+ gate->regmap = regmap;
+ gate->regmap_offs = regmap_offs;
gate->bit_idx = bit_idx;
gate->flags = clk_gate_flags;
gate->lock = lock;
@@ -197,6 +234,22 @@ struct clk *clk_register_gate(struct dev
}
EXPORT_SYMBOL_GPL(clk_register_gate);
+struct clk *clk_register_regmap_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ struct regmap *regmap, unsigned int regmap_offs,
+ u8 bit_idx, u8 clk_gate_flags)
+{
+ struct clk_hw *hw;
+
+ hw = clk_hw_register_regmap_gate(dev, name, parent_name, flags, regmap,
+ regmap_offs, bit_idx, clk_gate_flags);
+
+ if (IS_ERR(hw))
+ return ERR_CAST(hw);
+ return hw->clk;
+}
+EXPORT_SYMBOL_GPL(clk_register_regmap_gate);
+
void clk_unregister_gate(struct clk *clk)
{
struct clk_gate *gate;
@@ -234,6 +287,7 @@ struct clk_hw *__devm_clk_hw_register_ga
const char *parent_name, const struct clk_hw *parent_hw,
const struct clk_parent_data *parent_data,
unsigned long flags,
+ struct regmap *regmap, unsigned int regmap_offs,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock)
{
@@ -244,8 +298,8 @@ struct clk_hw *__devm_clk_hw_register_ga
return ERR_PTR(-ENOMEM);
hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw,
- parent_data, flags, reg, bit_idx,
- clk_gate_flags, lock);
+ parent_data, flags, regmap, regmap_offs,
+ reg, bit_idx, clk_gate_flags, lock);
if (!IS_ERR(hw)) {
*ptr = hw;
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -8,6 +8,7 @@
#include <linux/of.h>
#include <linux/of_clk.h>
+#include <linux/regmap.h>
/*
* flags used across common struct clk. these flags should only affect the
@@ -526,6 +527,8 @@ void of_fixed_clk_setup(struct device_no
struct clk_gate {
struct clk_hw hw;
void __iomem *reg;
+ struct regmap *regmap;
+ unsigned int regmap_offs;
u8 bit_idx;
u8 flags;
spinlock_t *lock;
@@ -543,6 +546,7 @@ struct clk_hw *__clk_hw_register_gate(st
const char *parent_name, const struct clk_hw *parent_hw,
const struct clk_parent_data *parent_data,
unsigned long flags,
+ struct regmap *regmap, unsigned int regmap_offs,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock);
struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
@@ -550,12 +554,17 @@ struct clk_hw *__devm_clk_hw_register_ga
const char *parent_name, const struct clk_hw *parent_hw,
const struct clk_parent_data *parent_data,
unsigned long flags,
+ struct regmap *regmap, unsigned int regmap_offs,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock);
struct clk *clk_register_gate(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock);
+struct clk *clk_register_regmap_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ struct regmap *regmap, unsigned int regmap_offs,
+ u8 bit_idx, u8 clk_gate_flags);
/**
* clk_hw_register_gate - register a gate clock with the clock framework
* @dev: device that is registering this clock
@@ -570,8 +579,14 @@ struct clk *clk_register_gate(struct dev
#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
clk_gate_flags, lock) \
__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
- NULL, (flags), (reg), (bit_idx), \
+ NULL, (flags), NULL, 0, (reg), (bit_idx), \
(clk_gate_flags), (lock))
+
+#define clk_hw_register_regmap_gate(dev, name, parent_name, flags, regmap, \
+ regmap_offs, bit_idx, clk_gate_flags) \
+ __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
+ NULL, (flags), regmap, regmap_offs, NULL, \
+ (bit_idx), (clk_gate_flags), NULL)
/**
* clk_hw_register_gate_parent_hw - register a gate clock with the clock
* framework
@@ -587,8 +602,15 @@ struct clk *clk_register_gate(struct dev
#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
bit_idx, clk_gate_flags, lock) \
__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
- NULL, (flags), (reg), (bit_idx), \
+ NULL, (flags), NULL, 0, (reg), (bit_idx), \
(clk_gate_flags), (lock))
+
+#define clk_hw_register_regmap_gate_parent_hw(dev, name, parent_hw, flags, \
+ regmap, regmap_offs, bit_idx, \
+ clk_gate_flags) \
+ __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
+ NULL, (flags), regmap, regmap_offs, NULL, \
+ (bit_idx), (clk_gate_flags), NULL)
/**
* clk_hw_register_gate_parent_data - register a gate clock with the clock
* framework
@@ -604,7 +626,7 @@ struct clk *clk_register_gate(struct dev
#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
bit_idx, clk_gate_flags, lock) \
__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
- (flags), (reg), (bit_idx), \
+ (flags), NULL, 0, (reg), (bit_idx), \
(clk_gate_flags), (lock))
/**
* devm_clk_hw_register_gate - register a gate clock with the clock framework
@@ -620,8 +642,14 @@ struct clk *clk_register_gate(struct dev
#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
clk_gate_flags, lock) \
__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
- NULL, (flags), (reg), (bit_idx), \
+ NULL, (flags), NULL, 0, (reg), (bit_idx), \
(clk_gate_flags), (lock))
+#define devm_clk_hw_register_regmap_gate(dev, name, parent_name, flags, \
+ regmap, regmap_offs, bit_idx, \
+ clk_gate_flags) \
+ __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
+ NULL, (flags), (regmap), (regmap_offs), NULL, \
+ (bit_idx), (clk_gate_flags), NULL)
/**
* devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
* framework
target/linux/sunxi/patches-6.18/121-03-clk-sunxi-ng-fix-clock-handling-for-ccu-sun55i-a523.patch
+57
View File
@@ -0,0 +1,57 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Marvin Wewer <mwewer37@proton.me>
Date: Tue, 9 Dec 2025 16:43:16 +0000
Subject: clk: sunxi-ng: add A523 USB3 ref clock and reset
Signed-off-by: Marvin Wewer <mwewer37@proton.me>
---
drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 13 +++++++++-
include/dt-bindings/clock/sun55i-a523-ccu.h | 1 +
2 files changed, 13 insertions(+), 1 deletion(-)
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
@@ -1186,6 +1186,15 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(fano
BIT(23), /* gate */
0);
+static const struct clk_parent_data usb3_ref_parents[] = { { .fw_name = "hosc" }, { .hw = &pll_periph0_200M_clk.hw }, { .hw = &pll_periph1_200M_clk.hw } };
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb3_ref_clk, "usb3-ref",
+ usb3_ref_parents, 0x0A84,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+
/*
* Contains all clocks that are controlled by a hardware register. They
* have a (sunxi) .common member, which needs to be initialised by the common
@@ -1354,6 +1363,7 @@ static struct ccu_common *sun55i_a523_cc
&fanout0_clk.common,
&fanout1_clk.common,
&fanout2_clk.common,
+ &usb3_ref_clk.common,
};
static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
@@ -1538,8 +1548,9 @@ static struct clk_hw_onecell_data sun55i
[CLK_FANOUT1] = &fanout1_clk.common.hw,
[CLK_FANOUT2] = &fanout2_clk.common.hw,
[CLK_NPU] = &npu_clk.common.hw,
+ [CLK_USB3_REF] = &usb3_ref_clk.common.hw,
},
- .num = CLK_NPU + 1,
+ .num = CLK_USB3_REF + 1,
};
static struct ccu_reset_map sun55i_a523_ccu_resets[] = {
--- a/include/dt-bindings/clock/sun55i-a523-ccu.h
+++ b/include/dt-bindings/clock/sun55i-a523-ccu.h
@@ -186,5 +186,6 @@
#define CLK_FANOUT1 177
#define CLK_FANOUT2 178
#define CLK_NPU 179
+#define CLK_USB3_REF 180
#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */
target/linux/sunxi/patches-6.18/124-iommu-sunxi-add-iommu-driver.patch
+2363
View File
File diff suppressed because it is too large Load Diff
target/linux/sunxi/patches-6.18/125-phy-allwinner-add-pcie-usb3-driver.patch
+1229
View File
File diff suppressed because it is too large Load Diff
target/linux/sunxi/patches-6.18/126-pci-sunxi-enable-pcie-support.patch
+3236
View File
File diff suppressed because it is too large Load Diff
target/linux/sunxi/patches-6.18/130-04-arm64-dts-sun55i-dtsi-add-iommu-usbc-pcie-combophy-nodes.patch
+117
View File
@@ -0,0 +1,117 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Marvin Wewer <mwewer37@proton.me>
Date: Mon, 5 Jan 2026 21:41:18 +0000
Subject: arm64: dts: allwinner: sun55i-a523: add iommu and PCIe/USB-C nodes
Signed-off-by: Marvin Wewer <mwewer37@proton.me>
---
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 84 ++++++++++
1 file changed, 84 insertions(+)
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h>
#include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -122,6 +123,17 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
+ iommu: iommu@2010000 {
+ compatible = "allwinner,sun55i-a523-iommu";
+ reg = <0x0 0x02010000 0x0 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iommu-irq";
+ clocks = <&ccu CLK_IOMMU>;
+ clock-names = "iommu";
+ /* clock-frequency = <24000000>; */
+ #iommu-cells = <2>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -860,6 +872,78 @@
};
};
+ usbc1: usbc1@11 {
+ device_type = "usbc1";
+ reg = <0x11 0x1000>;
+ usb_regulator_io = "nocare";
+ usb_wakeup_suspend = <0>;
+ status = "disabled";
+ };
+
+ combophy: phy@4f00000 {
+ compatible = "allwinner,inno-combphy";
+ reg = <0x04f00000 0x80000>, /* Sub-System Application Registers */
+ <0x04f80000 0x80000>; /* Combo INNO PHY Registers */
+ reg-names = "phy-ctl", "phy-clk";
+ power-domains = <&pck600 PD_PCIE>;
+ phy_refclk_sel = <0>; /* 0:internal clk; 1:external clk */
+ clocks = <&ccu CLK_USB3_REF>, <&ccu CLK_PLL_PERIPH0_200M>;
+ clock-names = "phyclk_ref","refclk_par";
+ resets = <&ccu RST_BUS_PCIE_USB3>;
+ reset-names = "phy_rst";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie: pcie@4800000 {
+ compatible = "allwinner,sunxi-pcie-v210-rc";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ reg = <0x04800000 0x480000>;
+ reg-names = "dbi";
+ device_type = "pci";
+ ranges = <0x00000800 0 0x20000000 0x20000000 0 0x01000000
+ 0x81000000 0 0x21000000 0x21000000 0 0x01000000
+ 0x82000000 0 0x22000000 0x22000000 0 0x0e000000>;
+ num-lanes = <1>;
+ phys = <&combophy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "sii", "edma-w0", "edma-w1", "edma-w2", "edma-w3",
+ "edma-r0", "edma-r1", "edma-r2", "edma-r3";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ num-edma = <4>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ linux,pci-domain = <0>;
+ power-domains = <&pck600 PD_PCIE>;
+ clocks = <&osc24M>, <&ccu CLK_PCIE_AUX>;
+ clock-names = "hosc", "pclk_aux";
+ status = "disabled";
+
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
ppu: power-controller@7001400 {
compatible = "allwinner,sun55i-a523-ppu";
reg = <0x07001400 0x400>;
target/linux/sunxi/patches-6.18/131-arm64-dts-allwinner-a527-Radxa-A5E-improvements.patch → target/linux/sunxi/patches-6.18/131-01-arm64-dts-allwinner-a527-Radxa-A5E-improvements.patch
View File
target/linux/sunxi/patches-6.18/131-02-arm64-dts-sun55i-a527-cubie-a5e-enable-usbc-pcie-combophy.patch
+82
View File
@@ -0,0 +1,82 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Marvin Wewer <mwewer37@proton.me>
Date: Sun, 11 Jan 2026 12:11:10 +0000
Subject: arm64: dts: allwinner: a527-cubie-a5e: enable PCIe/USB-C combophy
Signed-off-by: Marvin Wewer <mwewer37@proton.me>
---
---
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 58 ++++++++++
1 file changed, 58 insertions(+)
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -77,6 +77,39 @@
gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
enable-active-high;
};
+
+ reg_pcie_vcc3v3: regulator-pcie-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&r_pio 0 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ gma340_oe: gma340-oe {
+ compatible = "regulator-fixed";
+ regulator-name = "gma340-oe";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pio 1 7 GPIO_ACTIVE_LOW>;
+ };
+
+ gma340_pcie: gma340-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "gma340-pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pio 1 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&cpu0 {
@@ -430,3 +463,28 @@
usb1_vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
+
+/* PCIE and USB Switch */
+&combophy {
+ resets = <&ccu RST_BUS_PCIE_USB3>;
+ phy_use_sel = <0>; /* 0:PCIE; 1:USB3 */
+ status = "okay";
+};
+
+&pcie {
+ reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>;
+ num-lanes = <1>;
+ clk-freq-100M;
+ pcie3v3-supply = <&reg_pcie_vcc3v3>;
+ status = "okay";
+};
+
+&usbc1 {
+ device_type = "usbc1";
+ usb_regulator_io = "nocare";
+ usb_wakeup_suspend = <1>;
+ wakeup-source;
+ status = "okay";
+};
+
target/linux/sunxi/patches-6.18/433-arm64-dts-allwinner-add-LED-aliases-to-Cubie-A5E.patch
+2 -2
View File
@@ -37,7 +37,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
};
use-led {
@@ -129,6 +131,25 @@
@@ -162,6 +164,25 @@
reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
reset-assert-us = <10000>;
reset-deassert-us = <150000>;
@@ -63,7 +63,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
};
};
@@ -139,6 +160,25 @@
@@ -172,6 +193,25 @@
reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */
reset-assert-us = <10000>;
reset-deassert-us = <150000>;
target/linux/sunxi/patches-6.18/702-net-phy-add-driver-for-MAXIO-phy.patch
+1 -1
View File
@@ -10,7 +10,7 @@
/* As long as the interface is active, we keep the timestamping counter enabled
* with fine resolution and binary rollover. This avoid non-monotonic behavior
* (clock jumps) when changing timestamping settings at runtime.
@@ -7908,6 +7911,16 @@ int stmmac_resume(struct device *dev)
@@ -7909,6 +7912,16 @@ int stmmac_resume(struct device *dev)
stmmac_free_tx_skbufs(priv);
stmmac_clear_descriptors(priv, &priv->dma_conf);