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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2026-04-27 12:10:47 +08:00
parent b2616f2bca 10ca4886c4
commit 256521d9da
417 changed files with 11345 additions and 64092 deletions
Download Patch File Download Diff File Expand all files Collapse all files
package/kernel/linux/modules/crypto.mk
+3 -3
View File
@@ -740,7 +740,7 @@ define KernelPackage/crypto-md5
DEPENDS:=+kmod-crypto-hash
KCONFIG:= \
CONFIG_CRYPTO_MD5 \
CONFIG_CRYPTO_MD5_OCTEON \
CONFIG_CRYPTO_MD5_OCTEON@lt6.18 \
CONFIG_CRYPTO_MD5_PPC@lt6.18
FILES:=$(LINUX_DIR)/crypto/md5.ko \
$(LINUX_DIR)/lib/crypto/libmd5.ko@ge6.18
@@ -749,8 +749,8 @@ define KernelPackage/crypto-md5
endef
define KernelPackage/crypto-md5/octeon
FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-md5.ko
AUTOLOAD+=$(call AutoLoad,09,octeon-md5)
FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-md5.ko@lt6.18
AUTOLOAD+=$(call AutoLoad,09,LINUX_6_12:octeon-md5)
endef
define KernelPackage/crypto-md5/powerpc
package/kernel/linux/modules/netdevices.mk
+1 -1
View File
@@ -2504,7 +2504,7 @@ $(eval $(call KernelPackage,lan743x))
define KernelPackage/amazon-ena
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Elastic Network Adapter (for Amazon AWS)
DEPENDS:=@TARGET_x86_64||TARGET_armsr
DEPENDS:=@TARGET_x86_64||TARGET_armsr +LINUX_6_18:kmod-ptp
KCONFIG:=CONFIG_ENA_ETHERNET
FILES:=$(LINUX_DIR)/drivers/net/ethernet/amazon/ena/ena.ko
AUTOLOAD:=$(call AutoLoad,12,ena)
package/kernel/linux/modules/netsupport.mk
+1 -1
View File
@@ -605,7 +605,7 @@ define KernelPackage/pppox
SUBMENU:=$(NETWORK_SUPPORT_MENU)
TITLE:=PPPoX helper
DEPENDS:=kmod-ppp
KCONFIG:=CONFIG_PPPOE
HIDDEN:=1
FILES:=$(LINUX_DIR)/drivers/net/ppp/pppox.ko
endef
package/kernel/ntfs/Makefile
+4 -5
View File
@@ -5,11 +5,11 @@ PKG_NAME:=linux-ntfs
PKG_RELEASE:=1
PKG_BUILD_PARALLEL:=1
PKG_SOURCE_DATE:=2026-03-03
PKG_SOURCE_DATE:=2026-04-25
PKG_SOURCE_URL:=https://github.com/namjaejeon/linux-ntfs
PKG_SOURCE_PROTO:=git
PKG_SOURCE_VERSION:=6f6beff9ac623c691e8da7455a0e9b14bf957108
PKG_MIRROR_HASH:=b11f051e41e9993421753961bf948380bdf705a043a83f9b55dcbd7dc664fae2
PKG_SOURCE_VERSION:=ce7495f3e5c6a0b85d3350c18bbc06370cdcceb5
PKG_MIRROR_HASH:=0815623624dae868c3ca0ae82cf57ebf5d19e6b42778e2b9d241f85369fe348f
PKG_LICENSE:=GPL-2.0-or-later
@@ -35,8 +35,7 @@ define KernelPackage/fs-ntfs/description
endef
NOSTDINC_FLAGS += \
$(KERNEL_NOSTDINC_FLAGS) \
-DCONFIG_NTFS_FS_POSIX_ACL
$(KERNEL_NOSTDINC_FLAGS)
EXTRA_KCONFIG:= \
CONFIG_NTFS_FS=m
package/kernel/ntfs/patches/001-conditionally-enable-posix-acl.patch
+11
View File
@@ -0,0 +1,11 @@
--- a/Makefile
+++ b/Makefile
@@ -9,7 +9,7 @@ ntfs-y := aops.o attrib.o collate.o dir.
iomap.o debug.o sysctl.o quota.o object_id.o bdev-io.o
ccflags-$(CONFIG_NTFS_DEBUG) += -DDEBUG
-ccflags-y += -DCONFIG_NTFS_FS_POSIX_ACL
+ccflags-$(CONFIG_FS_POSIX_ACL) += -DCONFIG_NTFS_FS_POSIX_ACL
else
# Called from external kernel module build
package/libs/wolfssl/Makefile
+2 -2
View File
@@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=wolfssl
PKG_VERSION:=5.9.0
PKG_VERSION:=5.9.1
PKG_REAL_VERSION:=$(PKG_VERSION)-stable
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_REAL_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_REAL_VERSION)
PKG_HASH:=6efc62b86f145a5c52bfd62294ca66c20ce85b54e9033f5d7e0ee73eb30306c1
PKG_HASH:=d5ca7af48cd2d9a91d539e9baedeba55a0605a28d7ac8b01dc3d5254a13ca341
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_REAL_VERSION)
package/libs/wolfssl/patches/100-disable-hardening-check.patch
+1 -1
View File
@@ -1,6 +1,6 @@
--- a/wolfssl/wolfcrypt/settings.h
+++ b/wolfssl/wolfcrypt/settings.h
@@ -4122,7 +4122,7 @@ extern void uITRON4_free(void *p) ;
@@ -4154,7 +4154,7 @@ extern void uITRON4_free(void *p) ;
/* warning for not using harden build options (default with ./configure) */
/* do not warn if big integer support is disabled */
package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-iface.json
+11
View File
@@ -169,6 +169,10 @@
"description": "Management frame protection for Beacon frames",
"type": "boolean"
},
"bridge_isolate": {
"description": "Enable bridge port isolation for the wireless interface",
"type": "boolean"
},
"bss_load_update_period": {
"description": "BSS Load update period (in BUs)",
"type": "number",
@@ -760,6 +764,13 @@
"description": "Network Authentication Type",
"type": "string"
},
"network_vlan": {
"description": "Make a wireless interface a tagged member of extra VLANs",
"type": "array",
"items": {
"type": "string"
}
},
"no_probe_resp_if_max_sta": {
"description": "Do not answer probe requests if iface_max_num_sta was reached",
"type": "boolean"
package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-station.json
+7
View File
@@ -4,6 +4,13 @@
"description": "OpenWrt WiFi Station Schema",
"type": "object",
"properties": {
"iface": {
"description": "List of interfaces this station is associated with",
"type": "array",
"items": {
"type": "string"
}
},
"mac": {
"description": "The station's MAC addresses",
"type": "array",
package/network/config/wifi-scripts/files-ucode/usr/share/schema/wireless.wifi-vlan.json
+37
View File
@@ -4,10 +4,47 @@
"description": "OpenWrt WiFi VLAN Schema",
"type": "object",
"properties": {
"bridge_isolate": {
"description": "Enable bridge port isolation for the wireless interface",
"type": "boolean"
},
"iface": {
"description": "List of interfaces this VLAN is associated with",
"type": "array",
"items": {
"type": "string"
}
},
"isolate": {
"description": "Isolates wireless clients from each other",
"type": "boolean"
},
"multicast_to_unicast": {
"description": "Request that the AP will do multicast-to-unicast conversion for ARP, IPv4, and IPv6 frames",
"type": "boolean"
},
"name": {
"description": "VLAN name",
"type": "string"
},
"network": {
"description": "Specifies one or multiple logical network interfaces declared in the network configuration, each one should be a L3 bridge to be able to attach this L2 wireless interface.",
"type": "array",
"items": {
"type": "string"
}
},
"network_vlan": {
"description": "Make a wireless interface a tagged member of extra VLANs",
"type": "array",
"items": {
"type": "string"
}
},
"proxy_arp": {
"description": "Proxy ARP",
"type": "boolean"
},
"vid": {
"description": "VLAN ID",
"type": "string"
package/utils/util-linux/patches/0001-nsenter-Fix-AT_HANDLE_FID-on-musl.patch
+30
View File
@@ -0,0 +1,30 @@
From 5452239f6e69d2d3aaa427d2d2253247cfb7cb7b Mon Sep 17 00:00:00 2001
From: Aleksi Hannula <ahannula4+nixgit@gmail.com>
Date: Tue, 7 Apr 2026 14:52:16 +0300
Subject: [PATCH] nsenter: Fix AT_HANDLE_FID on musl
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Aleksi Hannula <ahannula4+nixgit@gmail.com>
---
sys-utils/nsenter.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/sys-utils/nsenter.c b/sys-utils/nsenter.c
index e10ba9cf90ab..98507958c0f1 100644
--- a/sys-utils/nsenter.c
+++ b/sys-utils/nsenter.c
@@ -29,6 +29,9 @@
#ifdef HAVE_LINUX_NSFS_H
# include <linux/nsfs.h>
#endif
+#ifndef AT_HANDLE_FID
+# define AT_HANDLE_FID 0x200
+#endif
#ifndef NS_GET_USERNS
# define NS_GET_USERNS _IO(0xb7, 0x1)
#endif
--
2.53.0
target/linux/airoha/dts/an7581-evb-emmc.dtsi
+4
View File
@@ -5,6 +5,10 @@
#include <dt-bindings/gpio/gpio.h>
#include "an7581.dtsi"
&afe {
status = "okay";
};
&sound {
audio-routing = "Headphone", "HP_L",
"Headphone", "HP_R",
target/linux/airoha/dts/an7581.dtsi
+1
View File
@@ -439,6 +439,7 @@
reg = <0x0 0x1fbe2200 0x0 0x9000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart4: serial@1fbf0600 {
target/linux/generic/backport-6.12/901-v6.14-PCI-dwc-Add-dw_pcie_suspend_noirq-dw_pcie_resume.patch
+57
View File
@@ -0,0 +1,57 @@
From ec57335b81d8fcf3088994c532b5ca21e839616a Mon Sep 17 00:00:00 2001
From: Bjorn Helgaas <bhelgaas@google.com>
Date: Fri, 17 Jan 2025 15:03:04 -0600
Subject: [PATCH] PCI: dwc: Add dw_pcie_suspend_noirq(),
dw_pcie_resume_noirq() stubs for !CONFIG_PCIE_DW_HOST
Previously pcie-designware.h declared dw_pcie_suspend_noirq() and
dw_pcie_resume_noirq() unconditionally, even though they were only
implemented when CONFIG_PCIE_DW_HOST was defined.
Add no-op stubs for them when CONFIG_PCIE_DW_HOST is not defined so
drivers that support both Root Complex and Endpoint modes don't need
Link: https://lore.kernel.org/r/20250117213810.GA656803@bhelgaas
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -498,9 +498,6 @@ void dw_pcie_iatu_detect(struct dw_pcie
int dw_pcie_edma_detect(struct dw_pcie *pci);
void dw_pcie_edma_remove(struct dw_pcie *pci);
-int dw_pcie_suspend_noirq(struct dw_pcie *pci);
-int dw_pcie_resume_noirq(struct dw_pcie *pci);
-
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
{
dw_pcie_write_dbi(pci, reg, 0x4, val);
@@ -678,6 +675,8 @@ static inline enum dw_pcie_ltssm dw_pcie
}
#ifdef CONFIG_PCIE_DW_HOST
+int dw_pcie_suspend_noirq(struct dw_pcie *pci);
+int dw_pcie_resume_noirq(struct dw_pcie *pci);
irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
int dw_pcie_setup_rc(struct dw_pcie_rp *pp);
int dw_pcie_host_init(struct dw_pcie_rp *pp);
@@ -686,6 +685,16 @@ int dw_pcie_allocate_domains(struct dw_p
void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
int where);
#else
+static inline int dw_pcie_suspend_noirq(struct dw_pcie *pci)
+{
+ return 0;
+}
+
+static inline int dw_pcie_resume_noirq(struct dw_pcie *pci)
+{
+ return 0;
+}
+
static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
{
return IRQ_NONE;
target/linux/generic/backport-6.12/902-v6.16-genirq-msi-Add-helper-for-creating-MSI-parent-irq-do.patch
+70
View File
@@ -0,0 +1,70 @@
From e4d001b54f78769ba1a1404c2801ae95e19fd893 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Tue, 13 May 2025 18:28:12 +0100
Subject: [PATCH] genirq/msi: Add helper for creating MSI-parent irq
domains
Creating an irq domain that serves as an MSI parent requires
a substantial amount of esoteric boiler-plate code, some of
which is often provided twice (such as the bus token).
To make things a bit simpler for the unsuspecting MSI tinkerer,
provide a helper that does it for them, and serves as documentation
of what needs to be provided.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20250513172819.2216709-3-maz@kernel.org
---
include/linux/msi.h | 4 ++++
kernel/irq/msi.c | 26 ++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -586,6 +586,10 @@ struct irq_domain *msi_create_irq_domain
struct msi_domain_info *info,
struct irq_domain *parent);
+struct irq_domain_info;
+struct irq_domain *msi_create_parent_irq_domain(struct irq_domain_info *info,
+ const struct msi_parent_ops *msi_parent_ops);
+
bool msi_create_device_irq_domain(struct device *dev, unsigned int domid,
const struct msi_domain_template *template,
unsigned int hwsize, void *domain_data,
--- a/kernel/irq/msi.c
+++ b/kernel/irq/msi.c
@@ -886,6 +886,32 @@ struct irq_domain *msi_create_irq_domain
}
/**
+ * msi_create_parent_irq_domain - Create an MSI-parent interrupt domain
+ * @info: MSI irqdomain creation info
+ * @msi_parent_ops: MSI parent callbacks and configuration
+ *
+ * Return: pointer to the created &struct irq_domain or %NULL on failure
+ */
+struct irq_domain *msi_create_parent_irq_domain(struct irq_domain_info *info,
+ const struct msi_parent_ops *msi_parent_ops)
+{
+ struct irq_domain *d;
+
+ info->hwirq_max = max(info->hwirq_max, info->size);
+ info->size = info->hwirq_max;
+ info->domain_flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
+ info->bus_token = msi_parent_ops->bus_select_token;
+
+ d = irq_domain_instantiate(info);
+ if (IS_ERR(d))
+ return NULL;
+
+ d->msi_parent_ops = msi_parent_ops;
+ return d;
+}
+EXPORT_SYMBOL_GPL(msi_create_parent_irq_domain);
+
+/**
* msi_parent_init_dev_msi_info - Delegate initialization of device MSI info down
* in the domain hierarchy
* @dev: The device for which the domain should be created
target/linux/generic/backport-6.12/903-v6.16-irqchip-Make-irq-msi-lib.h-globally-available.patch
+229
View File
@@ -0,0 +1,229 @@
From e51b27438a10391fdc94dd2046d9ffa9c2679c74 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Tue, 13 May 2025 18:28:11 +0100
Subject: [PATCH] irqchip: Make irq-msi-lib.h globally available
Move irq-msi-lib.h into include/linux/irqchip, making it available
to compilation units outside of drivers/irqchip.
This requires some churn in drivers to fetch it from the new location,
generated using this script:
git grep -l -w \"irq-msi-lib.h\" | \
xargs sed -i -e 's:"irq-msi-lib.h":\<linux/irqchip/irq-msi-lib.h\>:'
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20250513172819.2216709-2-maz@kernel.org
---
drivers/irqchip/irq-bcm2712-mip.c | 2 +-
drivers/irqchip/irq-gic-v2m.c | 2 +-
drivers/irqchip/irq-gic-v3-its-msi-parent.c | 2 +-
drivers/irqchip/irq-gic-v3-its.c | 2 +-
drivers/irqchip/irq-gic-v3-mbi.c | 2 +-
drivers/irqchip/irq-imx-mu-msi.c | 2 +-
drivers/irqchip/irq-loongarch-avec.c | 2 +-
drivers/irqchip/irq-loongson-pch-msi.c | 2 +-
drivers/irqchip/irq-msi-lib.c | 2 +-
drivers/irqchip/irq-mvebu-gicp.c | 2 +-
drivers/irqchip/irq-mvebu-icu.c | 2 +-
drivers/irqchip/irq-mvebu-odmi.c | 2 +-
drivers/irqchip/irq-mvebu-sei.c | 2 +-
drivers/irqchip/irq-riscv-imsic-platform.c | 2 +-
drivers/irqchip/irq-sg2042-msi.c | 2 +-
{drivers => include/linux}/irqchip/irq-msi-lib.h | 6 +++---
16 files changed, 18 insertions(+), 18 deletions(-)
rename {drivers => include/linux}/irqchip/irq-msi-lib.h (84%)
--- a/drivers/irqchip/irq-gic-v2m.c
+++ b/drivers/irqchip/irq-gic-v2m.c
@@ -26,7 +26,7 @@
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/arm-gic-common.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
/*
* MSI_TYPER:
--- a/drivers/irqchip/irq-gic-v3-its-msi-parent.c
+++ b/drivers/irqchip/irq-gic-v3-its-msi-parent.c
@@ -8,7 +8,7 @@
#include <linux/pci.h>
#include "irq-gic-common.h"
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
#define ITS_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
MSI_FLAG_USE_DEF_CHIP_OPS | \
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -38,7 +38,7 @@
#include <asm/exception.h>
#include "irq-gic-common.h"
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
--- a/drivers/irqchip/irq-gic-v3-mbi.c
+++ b/drivers/irqchip/irq-gic-v3-mbi.c
@@ -18,7 +18,7 @@
#include <linux/irqchip/arm-gic-v3.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
struct mbi_range {
u32 spi_start;
--- a/drivers/irqchip/irq-imx-mu-msi.c
+++ b/drivers/irqchip/irq-imx-mu-msi.c
@@ -24,7 +24,7 @@
#include <linux/pm_domain.h>
#include <linux/spinlock.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
#define IMX_MU_CHANS 4
--- a/drivers/irqchip/irq-loongarch-avec.c
+++ b/drivers/irqchip/irq-loongarch-avec.c
@@ -18,7 +18,7 @@
#include <asm/loongarch.h>
#include <asm/setup.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
#include "irq-loongson.h"
#define VECTORS_PER_REG 64
--- a/drivers/irqchip/irq-loongson-pch-msi.c
+++ b/drivers/irqchip/irq-loongson-pch-msi.c
@@ -15,7 +15,7 @@
#include <linux/pci.h>
#include <linux/slab.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
#include "irq-loongson.h"
static int nr_pics;
--- a/drivers/irqchip/irq-msi-lib.c
+++ b/drivers/irqchip/irq-msi-lib.c
@@ -4,7 +4,7 @@
#include <linux/export.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
/**
* msi_lib_init_dev_msi_info - Domain info setup for MSI domains
--- a/drivers/irqchip/irq-mvebu-gicp.c
+++ b/drivers/irqchip/irq-mvebu-gicp.c
@@ -17,7 +17,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -20,7 +20,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
#include <dt-bindings/interrupt-controller/mvebu-icu.h>
--- a/drivers/irqchip/irq-mvebu-odmi.c
+++ b/drivers/irqchip/irq-mvebu-odmi.c
@@ -18,7 +18,7 @@
#include <linux/of_address.h>
#include <linux/slab.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
--- a/drivers/irqchip/irq-mvebu-sei.c
+++ b/drivers/irqchip/irq-mvebu-sei.c
@@ -14,7 +14,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
-#include "irq-msi-lib.h"
+#include <linux/irqchip/irq-msi-lib.h>
/* Cause register */
#define GICP_SECR(idx) (0x0 + ((idx) * 0x4))
--- a/drivers/irqchip/irq-msi-lib.h
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (C) 2022 Linutronix GmbH
-// Copyright (C) 2022 Intel
-
-#ifndef _DRIVERS_IRQCHIP_IRQ_MSI_LIB_H
-#define _DRIVERS_IRQCHIP_IRQ_MSI_LIB_H
-
-#include <linux/bits.h>
-#include <linux/irqdomain.h>
-#include <linux/msi.h>
-
-#ifdef CONFIG_PCI_MSI
-#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI)
-#else
-#define MATCH_PCI_MSI (0)
-#endif
-
-#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI)
-
-int msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec,
- enum irq_domain_bus_token bus_token);
-
-bool msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
- struct irq_domain *real_parent,
- struct msi_domain_info *info);
-
-#endif /* _DRIVERS_IRQCHIP_IRQ_MSI_LIB_H */
--- /dev/null
+++ b/include/linux/irqchip/irq-msi-lib.h
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2022 Linutronix GmbH
+// Copyright (C) 2022 Intel
+
+#ifndef _IRQCHIP_IRQ_MSI_LIB_H
+#define _IRQCHIP_IRQ_MSI_LIB_H
+
+#include <linux/bits.h>
+#include <linux/irqdomain.h>
+#include <linux/msi.h>
+
+#ifdef CONFIG_PCI_MSI
+#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI)
+#else
+#define MATCH_PCI_MSI (0)
+#endif
+
+#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI)
+
+int msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ enum irq_domain_bus_token bus_token);
+
+bool msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
+ struct irq_domain *real_parent,
+ struct msi_domain_info *info);
+
+#endif /* _IRQCHIP_IRQ_MSI_LIB_H */
target/linux/generic/backport-6.12/904-v6.16-irqchip-irq-msi-lib-Fix-build-with-PCI-disabled.patch
+34
View File
@@ -0,0 +1,34 @@
From a8b289f0f2dcbadd8c207ad8f33cf7ba2b4eb088 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 10 Jul 2025 10:00:12 +0200
Subject: [PATCH] irqchip/irq-msi-lib: Fix build with PCI disabled
The armada-370-xp irqchip fails in some randconfig builds because
of a missing declaration:
In file included from drivers/irqchip/irq-armada-370-xp.c:23:
include/linux/irqchip/irq-msi-lib.h:25:39: error: 'struct msi_domain_info' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
Add a forward declaration for the msi_domain_info structure.
[ tglx: Fixed up the subsystem prefix. Is it really that hard to get right? ]
Fixes: e51b27438a10 ("irqchip: Make irq-msi-lib.h globally available")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/all/20250710080021.2303640-1-arnd@kernel.org
---
include/linux/irqchip/irq-msi-lib.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/linux/irqchip/irq-msi-lib.h
+++ b/include/linux/irqchip/irq-msi-lib.h
@@ -17,6 +17,7 @@
#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI)
+struct msi_domain_info;
int msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec,
enum irq_domain_bus_token bus_token);
target/linux/generic/backport-6.12/905-v6.17-PCI-dwc-Export-DWC-MSI-controller-related-APIs.patch
+144
View File
@@ -0,0 +1,144 @@
From a60d92f6d941bd77bf3aaec724a7c95857c0165b Mon Sep 17 00:00:00 2001
From: Mayank Rana <mayank.rana@oss.qualcomm.com>
Date: Mon, 16 Jun 2025 15:42:56 -0700
Subject: [PATCH] PCI: dwc: Export DWC MSI controller related APIs
Export dw_pcie_msi_host_init(), dw_pcie_msi_init(), and dw_pcie_free_msi()
APIs to allow them to be reused by the upcoming DWC based ECAM driver
implementation. Also, move MSI IRQ related initialization code to
dw_pcie_msi_init(), as this code must be executed before dw_pcie_msi_init()
API can be used with ECAM driver.
Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
[mani: commit message rewording]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250616224259.3549811-2-mayank.rana@oss.qualcomm.com
---
.../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++---------
drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++
2 files changed, 34 insertions(+), 18 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -250,7 +250,7 @@ int dw_pcie_allocate_domains(struct dw_p
return 0;
}
-static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
+void dw_pcie_free_msi(struct dw_pcie_rp *pp)
{
u32 ctrl;
@@ -263,19 +263,34 @@ static void dw_pcie_free_msi(struct dw_p
irq_domain_remove(pp->msi_domain);
irq_domain_remove(pp->irq_domain);
}
+EXPORT_SYMBOL_GPL(dw_pcie_free_msi);
-static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
+void dw_pcie_msi_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
u64 msi_target = (u64)pp->msi_data;
+ u32 ctrl, num_ctrls;
if (!pci_msi_enabled() || !pp->has_msi_ctrl)
return;
+ num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+
+ /* Initialize IRQ Status array */
+ for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
+ (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
+ pp->irq_mask[ctrl]);
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
+ (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
+ ~0);
+ }
+
/* Program the msi_data */
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
}
+EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
{
@@ -317,7 +332,7 @@ static int dw_pcie_parse_split_msi_irq(s
return 0;
}
-static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
+int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct device *dev = pci->dev;
@@ -391,6 +406,7 @@ static int dw_pcie_msi_host_init(struct
return 0;
}
+EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init);
static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
{
@@ -809,7 +825,7 @@ static int dw_pcie_iatu_setup(struct dw_
int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- u32 val, ctrl, num_ctrls;
+ u32 val;
int ret;
/*
@@ -820,20 +836,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *
dw_pcie_setup(pci);
- if (pp->has_msi_ctrl) {
- num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
-
- /* Initialize IRQ Status array */
- for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
- dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
- (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
- pp->irq_mask[ctrl]);
- dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
- (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
- ~0);
- }
- }
-
dw_pcie_msi_init(pp);
/* Setup RC BARs */
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -678,6 +678,9 @@ static inline enum dw_pcie_ltssm dw_pcie
int dw_pcie_suspend_noirq(struct dw_pcie *pci);
int dw_pcie_resume_noirq(struct dw_pcie *pci);
irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
+void dw_pcie_msi_init(struct dw_pcie_rp *pp);
+int dw_pcie_msi_host_init(struct dw_pcie_rp *pp);
+void dw_pcie_free_msi(struct dw_pcie_rp *pp);
int dw_pcie_setup_rc(struct dw_pcie_rp *pp);
int dw_pcie_host_init(struct dw_pcie_rp *pp);
void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
@@ -700,6 +703,17 @@ static inline irqreturn_t dw_handle_msi_
return IRQ_NONE;
}
+static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp)
+{ }
+
+static inline int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
+{
+ return -ENODEV;
+}
+
+static inline void dw_pcie_free_msi(struct dw_pcie_rp *pp)
+{ }
+
static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
{
return 0;
target/linux/generic/backport-6.12/906-v6.17-PCI-dwc-Switch-to-msi_create_parent_irq_domain.patch
+145
View File
@@ -0,0 +1,145 @@
From 8e717112caf35998b198d3762b381de70711bdec Mon Sep 17 00:00:00 2001
From: Nam Cao <namcao@linutronix.de>
Date: Thu, 26 Jun 2025 16:47:51 +0200
Subject: [PATCH] PCI: dwc: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://patch.msgid.link/04d4a96046490e50139826c16423954e033cdf89.1750858083.git.namcao@linutronix.de
[Keep of_node_to_fwnode instead of dev_fwnode]
---
drivers/pci/controller/dwc/Kconfig | 1 +
.../pci/controller/dwc/pcie-designware-host.c | 69 +++++++------------
drivers/pci/controller/dwc/pcie-designware.h | 1 -
3 files changed, 25 insertions(+), 46 deletions(-)
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -9,6 +9,7 @@ config PCIE_DW
config PCIE_DW_HOST
bool
select PCIE_DW
+ select IRQ_MSI_LIB
config PCIE_DW_EP
bool
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -10,6 +10,7 @@
#include <linux/iopoll.h>
#include <linux/irqchip/chained_irq.h>
+#include <linux/irqchip/irq-msi-lib.h>
#include <linux/irqdomain.h>
#include <linux/msi.h>
#include <linux/of_address.h>
@@ -23,35 +24,21 @@
static struct pci_ops dw_pcie_ops;
static struct pci_ops dw_child_pcie_ops;
-static void dw_msi_ack_irq(struct irq_data *d)
-{
- irq_chip_ack_parent(d);
-}
-
-static void dw_msi_mask_irq(struct irq_data *d)
-{
- pci_msi_mask_irq(d);
- irq_chip_mask_parent(d);
-}
-
-static void dw_msi_unmask_irq(struct irq_data *d)
-{
- pci_msi_unmask_irq(d);
- irq_chip_unmask_parent(d);
-}
-
-static struct irq_chip dw_pcie_msi_irq_chip = {
- .name = "PCI-MSI",
- .irq_ack = dw_msi_ack_irq,
- .irq_mask = dw_msi_mask_irq,
- .irq_unmask = dw_msi_unmask_irq,
-};
-
-static struct msi_domain_info dw_pcie_msi_domain_info = {
- .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
- MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX |
- MSI_FLAG_MULTI_PCI_MSI,
- .chip = &dw_pcie_msi_irq_chip,
+#define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
+ MSI_FLAG_USE_DEF_CHIP_OPS | \
+ MSI_FLAG_NO_AFFINITY | \
+ MSI_FLAG_PCI_MSI_MASK_PARENT)
+#define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \
+ MSI_FLAG_PCI_MSIX | \
+ MSI_GENERIC_FLAGS_MASK)
+
+static const struct msi_parent_ops dw_pcie_msi_parent_ops = {
+ .required_flags = DW_PCIE_MSI_FLAGS_REQUIRED,
+ .supported_flags = DW_PCIE_MSI_FLAGS_SUPPORTED,
+ .bus_select_token = DOMAIN_BUS_PCI_MSI,
+ .chip_flags = MSI_CHIP_FLAG_SET_ACK,
+ .prefix = "DW-",
+ .init_dev_msi_info = msi_lib_init_dev_msi_info,
};
/* MSI int handler */
@@ -227,26 +214,19 @@ static const struct irq_domain_ops dw_pc
int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
+ struct irq_domain_info info = {
+ .fwnode = of_node_to_fwnode(pci->dev->of_node),
+ .ops = &dw_pcie_msi_domain_ops,
+ .size = pp->num_vectors,
+ .host_data = pp,
+ };
- pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
- &dw_pcie_msi_domain_ops, pp);
+ pp->irq_domain = msi_create_parent_irq_domain(&info, &dw_pcie_msi_parent_ops);
if (!pp->irq_domain) {
dev_err(pci->dev, "Failed to create IRQ domain\n");
return -ENOMEM;
}
- irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
-
- pp->msi_domain = pci_msi_create_irq_domain(fwnode,
- &dw_pcie_msi_domain_info,
- pp->irq_domain);
- if (!pp->msi_domain) {
- dev_err(pci->dev, "Failed to create MSI domain\n");
- irq_domain_remove(pp->irq_domain);
- return -ENOMEM;
- }
-
return 0;
}
@@ -260,7 +240,6 @@ void dw_pcie_free_msi(struct dw_pcie_rp
NULL, NULL);
}
- irq_domain_remove(pp->msi_domain);
irq_domain_remove(pp->irq_domain);
}
EXPORT_SYMBOL_GPL(dw_pcie_free_msi);
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -368,7 +368,6 @@ struct dw_pcie_rp {
const struct dw_pcie_host_ops *ops;
int msi_irq[MAX_MSI_CTRLS];
struct irq_domain *irq_domain;
- struct irq_domain *msi_domain;
dma_addr_t msi_data;
struct irq_chip *msi_irq_chip;
u32 num_vectors;
target/linux/generic/backport-6.12/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch
+66
View File
@@ -0,0 +1,66 @@
From 455a65260f526cedd4680d4836ebdf2eaf1ab4c6 Mon Sep 17 00:00:00 2001
From: Tobias Schumacher <ts@linux.ibm.com>
Date: Thu, 4 Dec 2025 06:05:01 +0100
Subject: [PATCH] genirq: Change hwirq parameter to irq_hw_number_t
The irqdomain implementation internally represents hardware IRQs as
irq_hw_number_t, which is defined as unsigned long int. When providing
an irq_hw_number_t to the generic_handle_domain() functions that expect
and unsigned int hwirq, this can lead to a loss of information. Change
the hwirq parameter to irq_hw_number_t to support the full range of
hwirqs.
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Niklas Schnelle <schnelle@linux.ibm.com>
Reviewed-by: Farhan Ali <alifm@linux.ibm.com>
Signed-off-by: Tobias Schumacher <ts@linux.ibm.com>
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
---
include/linux/irqdesc.h | 6 +++---
kernel/irq/irqdesc.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
--- a/include/linux/irqdesc.h
+++ b/include/linux/irqdesc.h
@@ -183,9 +183,9 @@ int generic_handle_irq_safe(unsigned int
* and handle the result interrupt number. Return -EINVAL if
* conversion failed.
*/
-int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq);
-int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq);
-int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq);
+int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq);
+int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq);
+int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq);
#endif
/* Test to see if a driver has successfully requested an irq */
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -743,7 +743,7 @@ EXPORT_SYMBOL_GPL(generic_handle_irq_saf
* This function must be called from an IRQ context with irq regs
* initialized.
*/
-int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq)
+int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq)
{
return handle_irq_desc(irq_resolve_mapping(domain, hwirq));
}
@@ -761,7 +761,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_
* context). If the interrupt is marked as 'enforce IRQ-context only' then
* the function must be invoked from hard interrupt context.
*/
-int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq)
+int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq)
{
unsigned long flags;
int ret;
@@ -784,7 +784,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_
* This function must be called from an NMI context with irq regs
* initialized.
**/
-int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq)
+int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq)
{
WARN_ON_ONCE(!in_nmi());
return handle_irq_desc(irq_resolve_mapping(domain, hwirq));
target/linux/generic/backport-6.12/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch
+319
View File
@@ -0,0 +1,319 @@
From fcc1d0dabdb65ca069f77e5b76d3b20277be4a15 Mon Sep 17 00:00:00 2001
From: Radu Rendec <rrendec@redhat.com>
Date: Fri, 28 Nov 2025 16:20:53 -0500
Subject: [PATCH] genirq: Add interrupt redirection infrastructure
Add infrastructure to redirect interrupt handler execution to a
different CPU when the current CPU is not part of the interrupt's CPU
affinity mask.
This is primarily aimed at (de)multiplexed interrupts, where the child
interrupt handler runs in the context of the parent interrupt handler,
and therefore CPU affinity control for the child interrupt is typically
not available.
With the new infrastructure, the child interrupt is allowed to freely
change its affinity setting, independently of the parent. If the
interrupt handler happens to be triggered on an "incompatible" CPU (a
CPU that's not part of the child interrupt's affinity mask), the handler
is redirected and runs in IRQ work context on a "compatible" CPU.
No functional change is being made to any existing irqchip driver, and
irqchip drivers must be explicitly modified to use the newly added
infrastructure to support interrupt redirection.
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Radu Rendec <rrendec@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/
Link: https://patch.msgid.link/20251128212055.1409093-2-rrendec@redhat.com
---
include/linux/irq.h | 10 +++++
include/linux/irqdesc.h | 17 +++++++-
kernel/irq/chip.c | 22 ++++++++++-
kernel/irq/irqdesc.c | 86 ++++++++++++++++++++++++++++++++++++++++-
kernel/irq/manage.c | 15 ++++++-
5 files changed, 144 insertions(+), 6 deletions(-)
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -469,6 +469,8 @@ static inline irq_hw_number_t irqd_to_hw
* checks against the supplied affinity mask are not
* required. This is used for CPU hotplug where the
* target CPU is not yet set in the cpu_online_mask.
+ * @irq_pre_redirect: Optional function to be invoked before redirecting
+ * an interrupt via irq_work. Called only on CONFIG_SMP.
* @irq_retrigger: resend an IRQ to the CPU
* @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
* @irq_set_wake: enable/disable power-management wake-on of an IRQ
@@ -512,6 +514,7 @@ struct irq_chip {
void (*irq_eoi)(struct irq_data *data);
int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
+ void (*irq_pre_redirect)(struct irq_data *data);
int (*irq_retrigger)(struct irq_data *data);
int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
int (*irq_set_wake)(struct irq_data *data, unsigned int on);
@@ -692,6 +695,13 @@ extern int irq_chip_set_vcpu_affinity_pa
extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
extern int irq_chip_request_resources_parent(struct irq_data *data);
extern void irq_chip_release_resources_parent(struct irq_data *data);
+#ifdef CONFIG_SMP
+void irq_chip_pre_redirect_parent(struct irq_data *data);
+#endif
+#endif
+
+#ifdef CONFIG_SMP
+int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force);
#endif
/* Disable or mask interrupts during a kernel kexec */
--- a/include/linux/irqdesc.h
+++ b/include/linux/irqdesc.h
@@ -2,9 +2,10 @@
#ifndef _LINUX_IRQDESC_H
#define _LINUX_IRQDESC_H
-#include <linux/rcupdate.h>
+#include <linux/irq_work.h>
#include <linux/kobject.h>
#include <linux/mutex.h>
+#include <linux/rcupdate.h>
/*
* Core internal functions to deal with irq descriptors
@@ -30,6 +31,17 @@ struct irqstat {
};
/**
+ * struct irq_redirect - interrupt redirection metadata
+ * @work: Harg irq_work item for handler execution on a different CPU
+ * @target_cpu: CPU to run irq handler on in case the current CPU is not part
+ * of the irq affinity mask
+ */
+struct irq_redirect {
+ struct irq_work work;
+ unsigned int target_cpu;
+};
+
+/**
* struct irq_desc - interrupt descriptor
* @irq_common_data: per irq and chip data passed down to chip functions
* @kstat_irqs: irq stats per cpu
@@ -46,6 +58,7 @@ struct irqstat {
* @threads_handled: stats field for deferred spurious detection of threaded handlers
* @threads_handled_last: comparator field for deferred spurious detection of threaded handlers
* @lock: locking for SMP
+ * @redirect: Facility for redirecting interrupts via irq_work
* @affinity_hint: hint to user space for preferred irq affinity
* @affinity_notify: context for notification of affinity changes
* @pending_mask: pending rebalanced interrupts
@@ -84,6 +97,7 @@ struct irq_desc {
struct cpumask *percpu_enabled;
const struct cpumask *percpu_affinity;
#ifdef CONFIG_SMP
+ struct irq_redirect redirect;
const struct cpumask *affinity_hint;
struct irq_affinity_notify *affinity_notify;
#ifdef CONFIG_GENERIC_PENDING_IRQ
@@ -186,6 +200,7 @@ int generic_handle_irq_safe(unsigned int
int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq);
int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq);
int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq);
+bool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq);
#endif
/* Test to see if a driver has successfully requested an irq */
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -1196,7 +1196,7 @@ void irq_cpu_offline(void)
}
#endif
-#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
+#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
#ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS
/**
@@ -1301,6 +1301,15 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_ir
#endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */
+#ifdef CONFIG_SMP
+void irq_chip_pre_redirect_parent(struct irq_data *data)
+{
+ data = data->parent_data;
+ data->chip->irq_pre_redirect(data);
+}
+EXPORT_SYMBOL_GPL(irq_chip_pre_redirect_parent);
+#endif
+
/**
* irq_chip_set_parent_state - set the state of a parent interrupt.
*
@@ -1546,6 +1555,17 @@ void irq_chip_release_resources_parent(s
data->chip->irq_release_resources(data);
}
EXPORT_SYMBOL_GPL(irq_chip_release_resources_parent);
+#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
+
+#ifdef CONFIG_SMP
+int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force)
+{
+ struct irq_redirect *redir = &irq_data_to_desc(data)->redirect;
+
+ WRITE_ONCE(redir->target_cpu, cpumask_first(dest));
+ return IRQ_SET_MASK_OK;
+}
+EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity);
#endif
/**
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -77,8 +77,12 @@ static int alloc_masks(struct irq_desc *
return 0;
}
-static void desc_smp_init(struct irq_desc *desc, int node,
- const struct cpumask *affinity)
+static void irq_redirect_work(struct irq_work *work)
+{
+ handle_irq_desc(container_of(work, struct irq_desc, redirect.work));
+}
+
+static void desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity)
{
if (!affinity)
affinity = irq_default_affinity;
@@ -90,6 +94,7 @@ static void desc_smp_init(struct irq_des
#ifdef CONFIG_NUMA
desc->irq_common_data.node = node;
#endif
+ desc->redirect.work = IRQ_WORK_INIT_HARD(irq_redirect_work);
}
static void free_masks(struct irq_desc *desc)
@@ -789,6 +794,83 @@ int generic_handle_domain_nmi(struct irq
WARN_ON_ONCE(!in_nmi());
return handle_irq_desc(irq_resolve_mapping(domain, hwirq));
}
+
+#ifdef CONFIG_SMP
+static bool demux_redirect_remote(struct irq_desc *desc)
+{
+ guard(raw_spinlock)(&desc->lock);
+ const struct cpumask *m = irq_data_get_effective_affinity_mask(&desc->irq_data);
+ unsigned int target_cpu = READ_ONCE(desc->redirect.target_cpu);
+
+ if (desc->irq_data.chip->irq_pre_redirect)
+ desc->irq_data.chip->irq_pre_redirect(&desc->irq_data);
+
+ /*
+ * If the interrupt handler is already running on a CPU that's included
+ * in the interrupt's affinity mask, redirection is not necessary.
+ */
+ if (cpumask_test_cpu(smp_processor_id(), m))
+ return false;
+
+ /*
+ * The desc->action check protects against IRQ shutdown: __free_irq() sets
+ * desc->action to NULL while holding desc->lock, which we also hold.
+ *
+ * Calling irq_work_queue_on() here is safe w.r.t. CPU unplugging:
+ * - takedown_cpu() schedules multi_cpu_stop() on all active CPUs,
+ * including the one that's taken down.
+ * - multi_cpu_stop() acts like a barrier, which means all active
+ * CPUs go through MULTI_STOP_DISABLE_IRQ and disable hard IRQs
+ * *before* the dying CPU runs take_cpu_down() in MULTI_STOP_RUN.
+ * - Hard IRQs are re-enabled at the end of multi_cpu_stop(), *after*
+ * the dying CPU has run take_cpu_down() in MULTI_STOP_RUN.
+ * - Since we run in hard IRQ context, we run either before or after
+ * take_cpu_down() but never concurrently.
+ * - If we run before take_cpu_down(), the dying CPU hasn't been marked
+ * offline yet (it's marked via take_cpu_down() -> __cpu_disable()),
+ * so the WARN in irq_work_queue_on() can't occur.
+ * - Furthermore, the work item we queue will be flushed later via
+ * take_cpu_down() -> cpuhp_invoke_callback_range_nofail() ->
+ * smpcfd_dying_cpu() -> irq_work_run().
+ * - If we run after take_cpu_down(), target_cpu has been already
+ * updated via take_cpu_down() -> __cpu_disable(), which eventually
+ * calls irq_do_set_affinity() during IRQ migration. So, target_cpu
+ * no longer points to the dying CPU in this case.
+ */
+ if (desc->action)
+ irq_work_queue_on(&desc->redirect.work, target_cpu);
+
+ return true;
+}
+#else /* CONFIG_SMP */
+static bool demux_redirect_remote(struct irq_desc *desc)
+{
+ return false;
+}
+#endif
+
+/**
+ * generic_handle_demux_domain_irq - Invoke the handler for a hardware interrupt
+ * of a demultiplexing domain.
+ * @domain: The domain where to perform the lookup
+ * @hwirq: The hardware interrupt number to convert to a logical one
+ *
+ * Returns: True on success, or false if lookup has failed
+ */
+bool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq)
+{
+ struct irq_desc *desc = irq_resolve_mapping(domain, hwirq);
+
+ if (unlikely(!desc))
+ return false;
+
+ if (demux_redirect_remote(desc))
+ return true;
+
+ return !handle_irq_desc(desc);
+}
+EXPORT_SYMBOL_GPL(generic_handle_demux_domain_irq);
+
#endif
/* Dynamic interrupt handling */
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -35,6 +35,16 @@ static int __init setup_forced_irqthread
early_param("threadirqs", setup_forced_irqthreads);
#endif
+#ifdef CONFIG_SMP
+static inline void synchronize_irqwork(struct irq_desc *desc)
+{
+ /* Synchronize pending or on the fly redirect work */
+ irq_work_sync(&desc->redirect.work);
+}
+#else
+static inline void synchronize_irqwork(struct irq_desc *desc) { }
+#endif
+
static void __synchronize_hardirq(struct irq_desc *desc, bool sync_chip)
{
struct irq_data *irqd = irq_desc_get_irq_data(desc);
@@ -110,7 +120,9 @@ EXPORT_SYMBOL(synchronize_hardirq);
static void __synchronize_irq(struct irq_desc *desc)
{
+ synchronize_irqwork(desc);
__synchronize_hardirq(desc, true);
+
/*
* We made sure that no hardirq handler is running. Now verify that no
* threaded handlers are active.
@@ -220,8 +232,7 @@ static inline void irq_validate_effectiv
static DEFINE_PER_CPU(struct cpumask, __tmp_mask);
-int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask,
- bool force)
+int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
{
struct cpumask *tmp_mask = this_cpu_ptr(&__tmp_mask);
struct irq_desc *desc = irq_data_to_desc(data);
target/linux/generic/backport-6.12/908-2-v7.0-PCI-dwc-Code-cleanup.patch
+242
View File
@@ -0,0 +1,242 @@
From f1875091a01dd634ff5f8b6fc57ab874f755c415 Mon Sep 17 00:00:00 2001
From: Radu Rendec <rrendec@redhat.com>
Date: Fri, 28 Nov 2025 16:20:54 -0500
Subject: [PATCH] PCI: dwc: Code cleanup
Code cleanup with no functional changes. These changes were originally
made by Thomas Gleixner (see Link tag below) in a patch that was never
submitted as is. Other parts of that patch were eventually submitted as
commit 8e717112caf3 ("PCI: dwc: Switch to msi_create_parent_irq_domain()")
and the remaining parts are the code cleanup changes:
- Use guard()/scoped_guard() instead of open-coded lock/unlock.
- Return void in a few functions whose return value is never used.
- Simplify dw_handle_msi_irq() by using for_each_set_bit().
One notable deviation from the original patch is that it reverts back to a
simple 1 by 1 iteration over the controllers inside dw_handle_msi_irq. The
reason is that with the original changes, the IRQ offset was calculated
incorrectly.
This prepares the ground for enabling MSI affinity support, which was
originally part of that same series that Thomas Gleixner prepared.
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Radu Rendec <rrendec@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/
Link: https://patch.msgid.link/20251128212055.1409093-3-rrendec@redhat.com
---
.../pci/controller/dwc/pcie-designware-host.c | 98 ++++++-------------
drivers/pci/controller/dwc/pcie-designware.h | 7 +-
2 files changed, 34 insertions(+), 71 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -42,35 +42,25 @@ static const struct msi_parent_ops dw_pc
};
/* MSI int handler */
-irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
+void dw_handle_msi_irq(struct dw_pcie_rp *pp)
{
- int i, pos;
- unsigned long val;
- u32 status, num_ctrls;
- irqreturn_t ret = IRQ_NONE;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ unsigned int i, num_ctrls;
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
for (i = 0; i < num_ctrls; i++) {
- status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
- (i * MSI_REG_CTRL_BLOCK_SIZE));
+ unsigned int reg_off = i * MSI_REG_CTRL_BLOCK_SIZE;
+ unsigned int irq_off = i * MAX_MSI_IRQS_PER_CTRL;
+ unsigned long status, pos;
+
+ status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + reg_off);
if (!status)
continue;
- ret = IRQ_HANDLED;
- val = status;
- pos = 0;
- while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
- pos)) != MAX_MSI_IRQS_PER_CTRL) {
- generic_handle_domain_irq(pp->irq_domain,
- (i * MAX_MSI_IRQS_PER_CTRL) +
- pos);
- pos++;
- }
+ for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL)
+ generic_handle_domain_irq(pp->irq_domain, irq_off + pos);
}
-
- return ret;
}
/* Chained MSI interrupt service routine */
@@ -91,13 +81,10 @@ static void dw_pci_setup_msi_msg(struct
{
struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- u64 msi_target;
-
- msi_target = (u64)pp->msi_data;
+ u64 msi_target = (u64)pp->msi_data;
msg->address_lo = lower_32_bits(msi_target);
msg->address_hi = upper_32_bits(msi_target);
-
msg->data = d->hwirq;
dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
@@ -109,18 +96,14 @@ static void dw_pci_bottom_mask(struct ir
struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned int res, bit, ctrl;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&pp->lock, flags);
+ guard(raw_spinlock)(&pp->lock);
ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
pp->irq_mask[ctrl] |= BIT(bit);
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
-
- raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static void dw_pci_bottom_unmask(struct irq_data *d)
@@ -128,18 +111,14 @@ static void dw_pci_bottom_unmask(struct
struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned int res, bit, ctrl;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&pp->lock, flags);
+ guard(raw_spinlock)(&pp->lock);
ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
pp->irq_mask[ctrl] &= ~BIT(bit);
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
-
- raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static void dw_pci_bottom_ack(struct irq_data *d)
@@ -156,54 +135,42 @@ static void dw_pci_bottom_ack(struct irq
}
static struct irq_chip dw_pci_msi_bottom_irq_chip = {
- .name = "DWPCI-MSI",
- .irq_ack = dw_pci_bottom_ack,
- .irq_compose_msi_msg = dw_pci_setup_msi_msg,
- .irq_mask = dw_pci_bottom_mask,
- .irq_unmask = dw_pci_bottom_unmask,
+ .name = "DWPCI-MSI",
+ .irq_ack = dw_pci_bottom_ack,
+ .irq_compose_msi_msg = dw_pci_setup_msi_msg,
+ .irq_mask = dw_pci_bottom_mask,
+ .irq_unmask = dw_pci_bottom_unmask,
};
-static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
- unsigned int virq, unsigned int nr_irqs,
- void *args)
+static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *args)
{
struct dw_pcie_rp *pp = domain->host_data;
- unsigned long flags;
- u32 i;
int bit;
- raw_spin_lock_irqsave(&pp->lock, flags);
-
- bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
- order_base_2(nr_irqs));
-
- raw_spin_unlock_irqrestore(&pp->lock, flags);
+ scoped_guard (raw_spinlock_irq, &pp->lock) {
+ bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
+ order_base_2(nr_irqs));
+ }
if (bit < 0)
return -ENOSPC;
- for (i = 0; i < nr_irqs; i++)
- irq_domain_set_info(domain, virq + i, bit + i,
- pp->msi_irq_chip,
- pp, handle_edge_irq,
- NULL, NULL);
-
+ for (unsigned int i = 0; i < nr_irqs; i++) {
+ irq_domain_set_info(domain, virq + i, bit + i, pp->msi_irq_chip,
+ pp, handle_edge_irq, NULL, NULL);
+ }
return 0;
}
-static void dw_pcie_irq_domain_free(struct irq_domain *domain,
- unsigned int virq, unsigned int nr_irqs)
+static void dw_pcie_irq_domain_free(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs)
{
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
struct dw_pcie_rp *pp = domain->host_data;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&pp->lock, flags);
-
- bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
- order_base_2(nr_irqs));
- raw_spin_unlock_irqrestore(&pp->lock, flags);
+ guard(raw_spinlock_irq)(&pp->lock);
+ bitmap_release_region(pp->msi_irq_in_use, d->hwirq, order_base_2(nr_irqs));
}
static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
@@ -236,8 +203,7 @@ void dw_pcie_free_msi(struct dw_pcie_rp
for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
if (pp->msi_irq[ctrl] > 0)
- irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
- NULL, NULL);
+ irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL);
}
irq_domain_remove(pp->irq_domain);
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -676,7 +676,7 @@ static inline enum dw_pcie_ltssm dw_pcie
#ifdef CONFIG_PCIE_DW_HOST
int dw_pcie_suspend_noirq(struct dw_pcie *pci);
int dw_pcie_resume_noirq(struct dw_pcie *pci);
-irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
+void dw_handle_msi_irq(struct dw_pcie_rp *pp);
void dw_pcie_msi_init(struct dw_pcie_rp *pp);
int dw_pcie_msi_host_init(struct dw_pcie_rp *pp);
void dw_pcie_free_msi(struct dw_pcie_rp *pp);
@@ -697,10 +697,7 @@ static inline int dw_pcie_resume_noirq(s
return 0;
}
-static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
-{
- return IRQ_NONE;
-}
+static inline void dw_handle_msi_irq(struct dw_pcie_rp *pp) { }
static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp)
{ }
target/linux/generic/backport-6.12/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch
+92
View File
@@ -0,0 +1,92 @@
From eaf290c404f7c39f23292e9ce83b8b5b51ab598a Mon Sep 17 00:00:00 2001
From: Radu Rendec <rrendec@redhat.com>
Date: Fri, 28 Nov 2025 16:20:55 -0500
Subject: [PATCH] PCI: dwc: Enable MSI affinity support
Leverage the interrupt redirection infrastructure to enable CPU affinity
support for MSI interrupts. Since the parent interrupt affinity cannot
be changed, affinity control for the child interrupt (MSI) is achieved
by redirecting the handler to run in IRQ work context on the target CPU.
This patch was originally prepared by Thomas Gleixner (see Link tag below)
in a patch series that was never submitted as is, and only parts of that
series have made it upstream so far.
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Radu Rendec <rrendec@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/
Link: https://patch.msgid.link/20251128212055.1409093-4-rrendec@redhat.com
---
.../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++++++---
1 file changed, 28 insertions(+), 5 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -24,9 +24,27 @@
static struct pci_ops dw_pcie_ops;
static struct pci_ops dw_child_pcie_ops;
+#ifdef CONFIG_SMP
+static void dw_irq_noop(struct irq_data *d) { }
+#endif
+
+static bool dw_pcie_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
+ struct irq_domain *real_parent, struct msi_domain_info *info)
+{
+ if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
+ return false;
+
+#ifdef CONFIG_SMP
+ info->chip->irq_ack = dw_irq_noop;
+ info->chip->irq_pre_redirect = irq_chip_pre_redirect_parent;
+#else
+ info->chip->irq_ack = irq_chip_ack_parent;
+#endif
+ return true;
+}
+
#define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
MSI_FLAG_USE_DEF_CHIP_OPS | \
- MSI_FLAG_NO_AFFINITY | \
MSI_FLAG_PCI_MSI_MASK_PARENT)
#define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \
MSI_FLAG_PCI_MSIX | \
@@ -36,9 +54,8 @@ static const struct msi_parent_ops dw_pc
.required_flags = DW_PCIE_MSI_FLAGS_REQUIRED,
.supported_flags = DW_PCIE_MSI_FLAGS_SUPPORTED,
.bus_select_token = DOMAIN_BUS_PCI_MSI,
- .chip_flags = MSI_CHIP_FLAG_SET_ACK,
.prefix = "DW-",
- .init_dev_msi_info = msi_lib_init_dev_msi_info,
+ .init_dev_msi_info = dw_pcie_init_dev_msi_info,
};
/* MSI int handler */
@@ -59,7 +76,7 @@ void dw_handle_msi_irq(struct dw_pcie_rp
continue;
for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL)
- generic_handle_domain_irq(pp->irq_domain, irq_off + pos);
+ generic_handle_demux_domain_irq(pp->irq_domain, irq_off + pos);
}
}
@@ -136,10 +153,16 @@ static void dw_pci_bottom_ack(struct irq
static struct irq_chip dw_pci_msi_bottom_irq_chip = {
.name = "DWPCI-MSI",
- .irq_ack = dw_pci_bottom_ack,
.irq_compose_msi_msg = dw_pci_setup_msi_msg,
.irq_mask = dw_pci_bottom_mask,
.irq_unmask = dw_pci_bottom_unmask,
+#ifdef CONFIG_SMP
+ .irq_ack = dw_irq_noop,
+ .irq_pre_redirect = dw_pci_bottom_ack,
+ .irq_set_affinity = irq_chip_redirect_set_affinity,
+#else
+ .irq_ack = dw_pci_bottom_ack,
+#endif
};
static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
target/linux/generic/backport-6.12/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch
+56
View File
@@ -0,0 +1,56 @@
From df439718afaf23b5aa7b5711b6c14e87b5836cae Mon Sep 17 00:00:00 2001
From: Radu Rendec <rrendec@redhat.com>
Date: Mon, 12 Jan 2026 16:14:02 -0500
Subject: [PATCH] genirq: Update effective affinity for redirected
interrupts
For redirected interrupts, irq_chip_redirect_set_affinity() does not
update the effective affinity mask, which then triggers the warning in
irq_validate_effective_affinity(). Also, because the effective affinity
mask is empty, the cpumask_test_cpu(smp_processor_id(), m) condition in
demux_redirect_remote() is always false, and the interrupt is always
redirected, even if it's already running on the target CPU.
Set the effective affinity mask to be the same as the requested affinity
mask. It's worth noting that irq_do_set_affinity() filters out offline
CPUs before calling chip->irq_set_affinity() (unless `force` is set), so
the mask passed to irq_chip_redirect_set_affinity() is already filtered.
The solution is not ideal because it may lie about the effective
affinity of the demultiplexed ("child") interrupt. If the requested
affinity mask includes multiple CPUs, the effective affinity, in
reality, is the intersection between the requested mask and the
demultiplexing ("parent") interrupt's effective affinity mask, plus
the first CPU in the requested mask.
Accurately describing the effective affinity of the demultiplexed
interrupt is not trivial because it requires keeping track of the
demultiplexing interrupt's effective affinity. That is tricky in the
context of CPU hot(un)plugging, where interrupt migration ordering is
not guaranteed. The solution in the initial version of the fixed patch,
which stored the first CPU of the demultiplexing interrupt's effective
affinity in the `target_cpu` field, has its own drawbacks and
limitations.
Fixes: fcc1d0dabdb6 ("genirq: Add interrupt redirection infrastructure")
Reported-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Radu Rendec <rrendec@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260112211402.2927336-1-rrendec@redhat.com
Closes: https://lore.kernel.org/all/44509520-f29b-4b8a-8986-5eae3e022eb7@nvidia.com/
---
kernel/irq/chip.c | 2 ++
1 file changed, 2 insertions(+)
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -1563,6 +1563,8 @@ int irq_chip_redirect_set_affinity(struc
struct irq_redirect *redir = &irq_data_to_desc(data)->redirect;
WRITE_ONCE(redir->target_cpu, cpumask_first(dest));
+ irq_data_update_effective_affinity(data, dest);
+
return IRQ_SET_MASK_OK;
}
EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity);
target/linux/generic/backport-6.18/740-v6.19-r8152-Advertise-software-timestamp-information.patch
+27
View File
@@ -0,0 +1,27 @@
From a8e846b8d93de748485653dd8a6a8efd8f5d7613 Mon Sep 17 00:00:00 2001
From: Abhishek Rawal <rawal.abhishek92@gmail.com>
Date: Tue, 14 Oct 2025 11:22:33 +0530
Subject: [PATCH] r8152: Advertise software timestamp information.
Driver calls skb_tx_timestamp(skb) in rtl8152_start_xmit(), but does not advertise the capability in ethtool.
Advertise software timestamp capabilities on struct ethtool_ops.
Signed-off-by: Abhishek Rawal <rawal.abhishek92@gmail.com>
Reviewed-by: Jamie Bainbridge <jamie.bainbridge@gmail.com>
Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Link: https://patch.msgid.link/20251014055234.46527-1-rawal.abhishek92@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/usb/r8152.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -9314,6 +9314,7 @@ static const struct ethtool_ops ops = {
.set_ringparam = rtl8152_set_ringparam,
.get_pauseparam = rtl8152_get_pauseparam,
.set_pauseparam = rtl8152_set_pauseparam,
+ .get_ts_info = ethtool_op_get_ts_info,
};
static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
target/linux/generic/backport-6.18/741-v7.1-r8152-Add-2500baseT-EEE-status-configuration-support.patch
+148
View File
@@ -0,0 +1,148 @@
From e8e83b67960c20a9e60d4181631509d59f03488b Mon Sep 17 00:00:00 2001
From: Birger Koblitz <mail@birger-koblitz.de>
Date: Tue, 24 Feb 2026 18:40:14 +0100
Subject: [PATCH] r8152: Add 2500baseT EEE status/configuration support
The r8152 driver supports the RTL8156, which is a 2.5Gbit Ethernet controller for
USB 3.0, for which support is added for configuring and displaying the EEE
advertisement status for 2.5GBit connections.
The patch also corrects the determination of whether EEE is active to include
the 2.5GBit connection status and make the determination dependent not on the
desired speed configuration (tp->speed), but on the actual speed used by
the controller. For consistency, this is corrected also for the RTL8152/3.
This was tested on an Edimax EU-4307 V1.0 USB-Ethernet adapter with RTL8156,
and a SECOMP Value 12.99.1115 USB-C 3.1 Ethernet converter with RTL8153.
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
Link: https://patch.msgid.link/20260224-b4-eee2g5-v2-1-cf5c83df036e@birger-koblitz.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/usb/r8152.c | 50 ++++++++++++++++++++++++++++++++++-------
1 file changed, 42 insertions(+), 8 deletions(-)
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -213,6 +213,7 @@
#define OCP_EEE_LPABLE 0xa5d2
#define OCP_10GBT_CTRL 0xa5d4
#define OCP_10GBT_STAT 0xa5d6
+#define OCP_EEE_LPABLE2 0xa6d0
#define OCP_EEE_ADV2 0xa6d4
#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
#define OCP_PHY_PATCH_STAT 0xb800
@@ -954,6 +955,7 @@ struct r8152 {
u16 ocp_base;
u16 speed;
u16 eee_adv;
+ u16 eee_adv2;
u8 *intr_buff;
u8 version;
u8 duplex;
@@ -5399,7 +5401,7 @@ static void r8156_eee_en(struct r8152 *t
config = ocp_reg_read(tp, OCP_EEE_ADV2);
- if (enable)
+ if (enable && (tp->eee_adv2 & MDIO_EEE_2_5GT))
config |= MDIO_EEE_2_5GT;
else
config &= ~MDIO_EEE_2_5GT;
@@ -8929,7 +8931,8 @@ static void rtl8152_get_strings(struct n
static int r8152_get_eee(struct r8152 *tp, struct ethtool_keee *eee)
{
- __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(common) = {};
+ u16 speed = rtl8152_get_speed(tp);
u16 val;
val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
@@ -8943,8 +8946,14 @@ static int r8152_get_eee(struct r8152 *t
eee->eee_enabled = tp->eee_en;
- linkmode_and(common, eee->advertised, eee->lp_advertised);
- eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common);
+ if (speed & _1000bps)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, common);
+ if (speed & _100bps)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, common);
+
+ linkmode_and(common, common, eee->advertised);
+ linkmode_and(common, common, eee->lp_advertised);
+ eee->eee_active = !linkmode_empty(common);
return 0;
}
@@ -8955,7 +8964,10 @@ static int r8152_set_eee(struct r8152 *t
tp->eee_en = eee->eee_enabled;
tp->eee_adv = val;
-
+ if (tp->support_2500full) {
+ val = linkmode_to_mii_eee_cap2_t(eee->advertised);
+ tp->eee_adv2 = val;
+ }
rtl_eee_enable(tp, tp->eee_en);
return 0;
@@ -8963,7 +8975,8 @@ static int r8152_set_eee(struct r8152 *t
static int r8153_get_eee(struct r8152 *tp, struct ethtool_keee *eee)
{
- __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(common) = {};
+ u16 speed = rtl8152_get_speed(tp);
u16 val;
val = ocp_reg_read(tp, OCP_EEE_ABLE);
@@ -8975,10 +8988,29 @@ static int r8153_get_eee(struct r8152 *t
val = ocp_reg_read(tp, OCP_EEE_LPABLE);
mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val);
+ if (tp->support_2500full) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported);
+
+ val = ocp_reg_read(tp, OCP_EEE_ADV2);
+ mii_eee_cap2_mod_linkmode_adv_t(eee->advertised, val);
+
+ val = ocp_reg_read(tp, OCP_EEE_LPABLE2);
+ mii_eee_cap2_mod_linkmode_adv_t(eee->lp_advertised, val);
+
+ if (speed & _2500bps)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, common);
+ }
+
eee->eee_enabled = tp->eee_en;
- linkmode_and(common, eee->advertised, eee->lp_advertised);
- eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common);
+ if (speed & _1000bps)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, common);
+ if (speed & _100bps)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, common);
+
+ linkmode_and(common, common, eee->advertised);
+ linkmode_and(common, common, eee->lp_advertised);
+ eee->eee_active = !linkmode_empty(common);
return 0;
}
@@ -9519,6 +9551,7 @@ static int rtl_ops_init(struct r8152 *tp
case RTL_VER_11:
tp->eee_en = true;
tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
+ tp->eee_adv2 = MDIO_EEE_2_5GT;
fallthrough;
case RTL_VER_10:
ops->init = r8156_init;
@@ -9544,6 +9577,7 @@ static int rtl_ops_init(struct r8152 *tp
case RTL_VER_15:
tp->eee_en = true;
tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
+ tp->eee_adv2 = MDIO_EEE_2_5GT;
ops->init = r8156b_init;
ops->enable = rtl8156b_enable;
ops->disable = rtl8153_disable;
target/linux/generic/backport-6.18/742-v7.1-r8152-fix-incorrect-register-write-to-USB_UPHY_XTAL.patch
+31
View File
@@ -0,0 +1,31 @@
From 48afd5124fd6129c46fd12cb06155384b1c4a0c4 Mon Sep 17 00:00:00 2001
From: Chih Kai Hsu <hsu.chih.kai@realtek.com>
Date: Thu, 26 Mar 2026 15:39:23 +0800
Subject: [PATCH] r8152: fix incorrect register write to USB_UPHY_XTAL
The old code used ocp_write_byte() to clear the OOBS_POLLING bit
(BIT(8)) in the USB_UPHY_XTAL register, but this doesn't correctly
clear a bit in the upper byte of the 16-bit register.
Fix this by using ocp_write_word() instead.
Fixes: 195aae321c82 ("r8152: support new chips")
Signed-off-by: Chih Kai Hsu <hsu.chih.kai@realtek.com>
Reviewed-by: Hayes Wang <hayeswang@realtek.com>
Link: https://patch.msgid.link/20260326073925.32976-454-nic_swsd@realtek.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
drivers/net/usb/r8152.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -3898,7 +3898,7 @@ static void r8156_ups_en(struct r8152 *t
case RTL_VER_15:
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
ocp_data &= ~OOBS_POLLING;
- ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
break;
default:
break;
target/linux/generic/backport-6.18/743-v7.1-r8152-add-helper-functions-for-PLA-USB-OCP-registers.patch
+2182
View File
File diff suppressed because it is too large Load Diff
target/linux/generic/backport-6.18/744-v7.1-r8152-add-helper-functions-for-PHY-OCP-registers.patch
+1127
View File
File diff suppressed because it is too large Load Diff
target/linux/generic/backport-6.18/745-v7.1-r8152-Add-helper-functions-for-SRAM2.patch
+252
View File
@@ -0,0 +1,252 @@
From 86f5dd4e0ff282a0acf1f058e947fd5f4ba58a9d Mon Sep 17 00:00:00 2001
From: Chih Kai Hsu <hsu.chih.kai@realtek.com>
Date: Wed, 1 Apr 2026 19:55:41 +0800
Subject: [PATCH] r8152: Add helper functions for SRAM2
Add the following helper functions for SRAM2 access to simplify the code
and improve readability:
- sram2_write() - write data to SRAM2 address
- sram2_read() - read data from SRAM2 address
- sram2_write_w0w1() - read-modify-write operation
Signed-off-by: Chih Kai Hsu <hsu.chih.kai@realtek.com>
Reviewed-by: Hayes Wang <hayeswang@realtek.com>
Link: https://patch.msgid.link/20260401115542.34601-1-nic_swsd@realtek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/usb/r8152.c | 178 +++++++++++++++++-----------------------
1 file changed, 75 insertions(+), 103 deletions(-)
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -219,6 +219,8 @@
#define OCP_PHY_PATCH_STAT 0xb800
#define OCP_PHY_PATCH_CMD 0xb820
#define OCP_PHY_LOCK 0xb82e
+#define OCP_SRAM2_ADDR 0xb87c
+#define OCP_SRAM2_DATA 0xb87e
#define OCP_ADC_IOFFSET 0xbcfc
#define OCP_ADC_CFG 0xbc06
#define OCP_SYSCLK_CFG 0xc416
@@ -1770,6 +1772,27 @@ static void sram_set_bits(struct r8152 *
sram_write_w0w1(tp, addr, 0, set);
}
+static void sram2_write(struct r8152 *tp, u16 addr, u16 data)
+{
+ ocp_reg_write(tp, OCP_SRAM2_ADDR, addr);
+ ocp_reg_write(tp, OCP_SRAM2_DATA, data);
+}
+
+static u16 sram2_read(struct r8152 *tp, u16 addr)
+{
+ ocp_reg_write(tp, OCP_SRAM2_ADDR, addr);
+ return ocp_reg_read(tp, OCP_SRAM2_DATA);
+}
+
+static void sram2_write_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set)
+{
+ u16 data;
+
+ data = sram2_read(tp, addr);
+ data = (data & ~clear) | set;
+ ocp_reg_write(tp, OCP_SRAM2_DATA, data);
+}
+
static void r8152_mdio_clr_bit(struct r8152 *tp, u16 addr, u16 clear)
{
int data;
@@ -7201,16 +7224,12 @@ static void r8156_hw_phy_cfg(struct r815
ocp_reg_write(tp, 0xad4c, 0x00a8);
ocp_reg_write(tp, 0xac5c, 0x01ff);
ocp_reg_w0w1(tp, 0xac8a, 0xf0, BIT(4) | BIT(5));
- ocp_reg_write(tp, 0xb87c, 0x8157);
- ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0500);
- ocp_reg_write(tp, 0xb87c, 0x8159);
- ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0700);
+ sram2_write_w0w1(tp, 0x8157, 0xff00, 0x0500);
+ sram2_write_w0w1(tp, 0x8159, 0xff00, 0x0700);
/* AAGC */
- ocp_reg_write(tp, 0xb87c, 0x80a2);
- ocp_reg_write(tp, 0xb87e, 0x0153);
- ocp_reg_write(tp, 0xb87c, 0x809c);
- ocp_reg_write(tp, 0xb87e, 0x0153);
+ sram2_write(tp, 0x80a2, 0x0153);
+ sram2_write(tp, 0x809c, 0x0153);
/* EEE parameter */
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
@@ -7408,82 +7427,48 @@ static void r8156b_hw_phy_cfg(struct r81
ocp_reg_write(tp, 0xacc8, 0xa0d3);
ocp_reg_write(tp, 0xad08, 0x0007);
- ocp_reg_write(tp, 0xb87c, 0x8560);
- ocp_reg_write(tp, 0xb87e, 0x19cc);
- ocp_reg_write(tp, 0xb87c, 0x8562);
- ocp_reg_write(tp, 0xb87e, 0x19cc);
- ocp_reg_write(tp, 0xb87c, 0x8564);
- ocp_reg_write(tp, 0xb87e, 0x19cc);
- ocp_reg_write(tp, 0xb87c, 0x8566);
- ocp_reg_write(tp, 0xb87e, 0x147d);
- ocp_reg_write(tp, 0xb87c, 0x8568);
- ocp_reg_write(tp, 0xb87e, 0x147d);
- ocp_reg_write(tp, 0xb87c, 0x856a);
- ocp_reg_write(tp, 0xb87e, 0x147d);
- ocp_reg_write(tp, 0xb87c, 0x8ffe);
- ocp_reg_write(tp, 0xb87e, 0x0907);
- ocp_reg_write(tp, 0xb87c, 0x80d6);
- ocp_reg_write(tp, 0xb87e, 0x2801);
- ocp_reg_write(tp, 0xb87c, 0x80f2);
- ocp_reg_write(tp, 0xb87e, 0x2801);
- ocp_reg_write(tp, 0xb87c, 0x80f4);
- ocp_reg_write(tp, 0xb87e, 0x6077);
+ sram2_write(tp, 0x8560, 0x19cc);
+ sram2_write(tp, 0x8562, 0x19cc);
+ sram2_write(tp, 0x8564, 0x19cc);
+ sram2_write(tp, 0x8566, 0x147d);
+ sram2_write(tp, 0x8568, 0x147d);
+ sram2_write(tp, 0x856a, 0x147d);
+ sram2_write(tp, 0x8ffe, 0x0907);
+ sram2_write(tp, 0x80d6, 0x2801);
+ sram2_write(tp, 0x80f2, 0x2801);
+ sram2_write(tp, 0x80f4, 0x6077);
ocp_reg_write(tp, 0xb506, 0x01e7);
- ocp_reg_write(tp, 0xb87c, 0x8013);
- ocp_reg_write(tp, 0xb87e, 0x0700);
- ocp_reg_write(tp, 0xb87c, 0x8fb9);
- ocp_reg_write(tp, 0xb87e, 0x2801);
- ocp_reg_write(tp, 0xb87c, 0x8fba);
- ocp_reg_write(tp, 0xb87e, 0x0100);
- ocp_reg_write(tp, 0xb87c, 0x8fbc);
- ocp_reg_write(tp, 0xb87e, 0x1900);
- ocp_reg_write(tp, 0xb87c, 0x8fbe);
- ocp_reg_write(tp, 0xb87e, 0xe100);
- ocp_reg_write(tp, 0xb87c, 0x8fc0);
- ocp_reg_write(tp, 0xb87e, 0x0800);
- ocp_reg_write(tp, 0xb87c, 0x8fc2);
- ocp_reg_write(tp, 0xb87e, 0xe500);
- ocp_reg_write(tp, 0xb87c, 0x8fc4);
- ocp_reg_write(tp, 0xb87e, 0x0f00);
- ocp_reg_write(tp, 0xb87c, 0x8fc6);
- ocp_reg_write(tp, 0xb87e, 0xf100);
- ocp_reg_write(tp, 0xb87c, 0x8fc8);
- ocp_reg_write(tp, 0xb87e, 0x0400);
- ocp_reg_write(tp, 0xb87c, 0x8fca);
- ocp_reg_write(tp, 0xb87e, 0xf300);
- ocp_reg_write(tp, 0xb87c, 0x8fcc);
- ocp_reg_write(tp, 0xb87e, 0xfd00);
- ocp_reg_write(tp, 0xb87c, 0x8fce);
- ocp_reg_write(tp, 0xb87e, 0xff00);
- ocp_reg_write(tp, 0xb87c, 0x8fd0);
- ocp_reg_write(tp, 0xb87e, 0xfb00);
- ocp_reg_write(tp, 0xb87c, 0x8fd2);
- ocp_reg_write(tp, 0xb87e, 0x0100);
- ocp_reg_write(tp, 0xb87c, 0x8fd4);
- ocp_reg_write(tp, 0xb87e, 0xf400);
- ocp_reg_write(tp, 0xb87c, 0x8fd6);
- ocp_reg_write(tp, 0xb87e, 0xff00);
- ocp_reg_write(tp, 0xb87c, 0x8fd8);
- ocp_reg_write(tp, 0xb87e, 0xf600);
+ sram2_write(tp, 0x8013, 0x0700);
+ sram2_write(tp, 0x8fb9, 0x2801);
+ sram2_write(tp, 0x8fba, 0x0100);
+ sram2_write(tp, 0x8fbc, 0x1900);
+ sram2_write(tp, 0x8fbe, 0xe100);
+ sram2_write(tp, 0x8fc0, 0x0800);
+ sram2_write(tp, 0x8fc2, 0xe500);
+ sram2_write(tp, 0x8fc4, 0x0f00);
+ sram2_write(tp, 0x8fc6, 0xf100);
+ sram2_write(tp, 0x8fc8, 0x0400);
+ sram2_write(tp, 0x8fca, 0xf300);
+ sram2_write(tp, 0x8fcc, 0xfd00);
+ sram2_write(tp, 0x8fce, 0xff00);
+ sram2_write(tp, 0x8fd0, 0xfb00);
+ sram2_write(tp, 0x8fd2, 0x0100);
+ sram2_write(tp, 0x8fd4, 0xf400);
+ sram2_write(tp, 0x8fd6, 0xff00);
+ sram2_write(tp, 0x8fd8, 0xf600);
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG,
EN_XG_LIP | EN_G_LIP);
- ocp_reg_write(tp, 0xb87c, 0x813d);
- ocp_reg_write(tp, 0xb87e, 0x390e);
- ocp_reg_write(tp, 0xb87c, 0x814f);
- ocp_reg_write(tp, 0xb87e, 0x790e);
- ocp_reg_write(tp, 0xb87c, 0x80b0);
- ocp_reg_write(tp, 0xb87e, 0x0f31);
+ sram2_write(tp, 0x813d, 0x390e);
+ sram2_write(tp, 0x814f, 0x790e);
+ sram2_write(tp, 0x80b0, 0x0f31);
ocp_reg_set_bits(tp, 0xbf4c, BIT(1));
ocp_reg_set_bits(tp, 0xbcca, BIT(9) | BIT(8));
- ocp_reg_write(tp, 0xb87c, 0x8141);
- ocp_reg_write(tp, 0xb87e, 0x320e);
- ocp_reg_write(tp, 0xb87c, 0x8153);
- ocp_reg_write(tp, 0xb87e, 0x720e);
- ocp_reg_write(tp, 0xb87c, 0x8529);
- ocp_reg_write(tp, 0xb87e, 0x050e);
+ sram2_write(tp, 0x8141, 0x320e);
+ sram2_write(tp, 0x8153, 0x720e);
+ sram2_write(tp, 0x8529, 0x050e);
ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN);
sram_write(tp, 0x816c, 0xc4a0);
@@ -7495,27 +7480,17 @@ static void r8156b_hw_phy_cfg(struct r81
sram_write(tp, 0x8ff1, 0x0404);
ocp_reg_write(tp, 0xbf4a, 0x001b);
- ocp_reg_write(tp, 0xb87c, 0x8033);
- ocp_reg_write(tp, 0xb87e, 0x7c13);
- ocp_reg_write(tp, 0xb87c, 0x8037);
- ocp_reg_write(tp, 0xb87e, 0x7c13);
- ocp_reg_write(tp, 0xb87c, 0x803b);
- ocp_reg_write(tp, 0xb87e, 0xfc32);
- ocp_reg_write(tp, 0xb87c, 0x803f);
- ocp_reg_write(tp, 0xb87e, 0x7c13);
- ocp_reg_write(tp, 0xb87c, 0x8043);
- ocp_reg_write(tp, 0xb87e, 0x7c13);
- ocp_reg_write(tp, 0xb87c, 0x8047);
- ocp_reg_write(tp, 0xb87e, 0x7c13);
-
- ocp_reg_write(tp, 0xb87c, 0x8145);
- ocp_reg_write(tp, 0xb87e, 0x370e);
- ocp_reg_write(tp, 0xb87c, 0x8157);
- ocp_reg_write(tp, 0xb87e, 0x770e);
- ocp_reg_write(tp, 0xb87c, 0x8169);
- ocp_reg_write(tp, 0xb87e, 0x0d0a);
- ocp_reg_write(tp, 0xb87c, 0x817b);
- ocp_reg_write(tp, 0xb87e, 0x1d0a);
+ sram2_write(tp, 0x8033, 0x7c13);
+ sram2_write(tp, 0x8037, 0x7c13);
+ sram2_write(tp, 0x803b, 0xfc32);
+ sram2_write(tp, 0x803f, 0x7c13);
+ sram2_write(tp, 0x8043, 0x7c13);
+ sram2_write(tp, 0x8047, 0x7c13);
+
+ sram2_write(tp, 0x8145, 0x370e);
+ sram2_write(tp, 0x8157, 0x770e);
+ sram2_write(tp, 0x8169, 0x0d0a);
+ sram2_write(tp, 0x817b, 0x1d0a);
sram_write_w0w1(tp, 0x8217, 0xff00, 0x5000);
sram_write_w0w1(tp, 0x821a, 0xff00, 0x5000);
@@ -7580,12 +7555,9 @@ static void r8156b_hw_phy_cfg(struct r81
fallthrough;
case RTL_VER_15:
/* EEE parameter */
- ocp_reg_write(tp, 0xb87c, 0x80f5);
- ocp_reg_write(tp, 0xb87e, 0x760e);
- ocp_reg_write(tp, 0xb87c, 0x8107);
- ocp_reg_write(tp, 0xb87e, 0x360e);
- ocp_reg_write(tp, 0xb87c, 0x8551);
- ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0800);
+ sram2_write(tp, 0x80f5, 0x760e);
+ sram2_write(tp, 0x8107, 0x360e);
+ sram2_write_w0w1(tp, 0x8551, 0xff00, 0x0800);
/* ADC_PGA parameter */
ocp_reg_w0w1(tp, 0xbf00, 0xe000, 0xa000);
target/linux/generic/backport-6.18/746-v7.1-r8152-Add-support-for-5Gbit-Link-Speeds-and-EEE.patch
+235
View File
@@ -0,0 +1,235 @@
From ebe5fd2ed20af5ae176dd41dd4a85a3cdc738b8a Mon Sep 17 00:00:00 2001
From: Birger Koblitz <mail@birger-koblitz.de>
Date: Sat, 4 Apr 2026 09:57:42 +0200
Subject: [PATCH] r8152: Add support for 5Gbit Link Speeds and EEE
The RTL8157 supports 5GBit Link speeds. Add support for this speed
in the setup and setting/getting through ethtool. Also add 5GBit EEE.
Add functionality for setup and ethtool get/set methods.
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
Link: https://patch.msgid.link/20260404-rtl8157_next-v7-1-039121318f23@birger-koblitz.de
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
drivers/net/usb/r8152.c | 100 ++++++++++++++++++++++++++++++++--------
1 file changed, 82 insertions(+), 18 deletions(-)
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -612,6 +612,7 @@ enum spd_duplex {
FORCE_100M_FULL,
FORCE_1000M_FULL,
NWAY_2500M_FULL,
+ NWAY_5000M_FULL,
};
/* OCP_ALDPS_CONFIG */
@@ -733,6 +734,7 @@ enum spd_duplex {
#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
enum rtl_register_content {
+ _5000bps = BIT(12),
_2500bps = BIT(10),
_1250bps = BIT(9),
_500bps = BIT(8),
@@ -746,6 +748,7 @@ enum rtl_register_content {
};
#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
+#define is_speed_5000(_speed) (((_speed) & (_5000bps | LINK_STATUS)) == (_5000bps | LINK_STATUS))
#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
#define RTL8152_MAX_TX 4
@@ -952,6 +955,7 @@ struct r8152 {
unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
u32 support_2500full:1;
+ u32 support_5000full:1;
u32 lenovo_macpassthru:1;
u32 dell_tb_rx_agg_bug:1;
u16 ocp_base;
@@ -1202,6 +1206,7 @@ enum tx_csum_stat {
#define RTL_ADVERTISED_1000_HALF BIT(4)
#define RTL_ADVERTISED_1000_FULL BIT(5)
#define RTL_ADVERTISED_2500_FULL BIT(6)
+#define RTL_ADVERTISED_5000_FULL BIT(7)
/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
* The RTL chips use a 64 element hash table based on the Ethernet CRC.
@@ -5427,12 +5432,23 @@ static void r8153_eee_en(struct r8152 *t
static void r8156_eee_en(struct r8152 *tp, bool enable)
{
+ u16 config;
+
r8153_eee_en(tp, enable);
+ config = ocp_reg_read(tp, OCP_EEE_ADV2);
+
if (enable && (tp->eee_adv2 & MDIO_EEE_2_5GT))
- ocp_reg_set_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT);
+ config |= MDIO_EEE_2_5GT;
else
- ocp_reg_clr_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT);
+ config &= ~MDIO_EEE_2_5GT;
+
+ if (enable && (tp->eee_adv2 & MDIO_EEE_5GT))
+ config |= MDIO_EEE_5GT;
+ else
+ config &= ~MDIO_EEE_5GT;
+
+ ocp_reg_write(tp, OCP_EEE_ADV2, config);
}
static void rtl_eee_enable(struct r8152 *tp, bool enable)
@@ -6196,9 +6212,13 @@ static int rtl8152_set_speed(struct r815
if (tp->support_2500full)
support |= RTL_ADVERTISED_2500_FULL;
+
+ if (tp->support_5000full)
+ support |= RTL_ADVERTISED_5000_FULL;
}
- if (!(advertising & support))
+ advertising &= support;
+ if (!advertising)
return -EINVAL;
orig = r8152_mdio_read(tp, MII_ADVERTISE);
@@ -6241,15 +6261,20 @@ static int rtl8152_set_speed(struct r815
r8152_mdio_write(tp, MII_CTRL1000, new1);
}
- if (tp->support_2500full) {
+ if (tp->support_2500full || tp->support_5000full) {
orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
- new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
+ new1 = orig & ~(MDIO_AN_10GBT_CTRL_ADV2_5G | MDIO_AN_10GBT_CTRL_ADV5G);
if (advertising & RTL_ADVERTISED_2500_FULL) {
new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
tp->ups_info.speed_duplex = NWAY_2500M_FULL;
}
+ if (advertising & RTL_ADVERTISED_5000_FULL) {
+ new1 |= MDIO_AN_10GBT_CTRL_ADV5G;
+ tp->ups_info.speed_duplex = NWAY_5000M_FULL;
+ }
+
if (orig != new1)
ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
}
@@ -8227,17 +8252,38 @@ int rtl8152_get_link_ksettings(struct ne
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
cmd->link_modes.supported, tp->support_2500full);
- if (tp->support_2500full) {
- linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
- cmd->link_modes.advertising,
- ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
-
- linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
- cmd->link_modes.lp_advertising,
- ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+ cmd->link_modes.supported, tp->support_5000full);
+
+ if (tp->support_2500full || tp->support_5000full) {
+ u16 ocp_10gbt_ctrl = ocp_reg_read(tp, OCP_10GBT_CTRL);
+ u16 ocp_10gbt_stat = ocp_reg_read(tp, OCP_10GBT_STAT);
+
+ if (tp->support_2500full) {
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+ cmd->link_modes.advertising,
+ ocp_10gbt_ctrl & MDIO_AN_10GBT_CTRL_ADV2_5G);
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+ cmd->link_modes.lp_advertising,
+ ocp_10gbt_stat & MDIO_AN_10GBT_STAT_LP2_5G);
+
+ if (is_speed_2500(rtl8152_get_speed(tp)))
+ cmd->base.speed = SPEED_2500;
+ }
+
+ if (tp->support_5000full) {
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+ cmd->link_modes.advertising,
+ ocp_10gbt_ctrl & MDIO_AN_10GBT_CTRL_ADV5G);
- if (is_speed_2500(rtl8152_get_speed(tp)))
- cmd->base.speed = SPEED_2500;
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+ cmd->link_modes.lp_advertising,
+ ocp_10gbt_stat & MDIO_AN_10GBT_STAT_LP5G);
+
+ if (is_speed_5000(rtl8152_get_speed(tp)))
+ cmd->base.speed = SPEED_5000;
+ }
}
mutex_unlock(&tp->control);
@@ -8287,6 +8333,10 @@ static int rtl8152_set_link_ksettings(st
cmd->link_modes.advertising))
advertising |= RTL_ADVERTISED_2500_FULL;
+ if (test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+ cmd->link_modes.advertising))
+ advertising |= RTL_ADVERTISED_5000_FULL;
+
mutex_lock(&tp->control);
ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
@@ -8404,7 +8454,7 @@ static int r8152_set_eee(struct r8152 *t
tp->eee_en = eee->eee_enabled;
tp->eee_adv = val;
- if (tp->support_2500full) {
+ if (tp->support_2500full || tp->support_5000full) {
val = linkmode_to_mii_eee_cap2_t(eee->advertised);
tp->eee_adv2 = val;
}
@@ -8428,19 +8478,28 @@ static int r8153_get_eee(struct r8152 *t
val = ocp_reg_read(tp, OCP_EEE_LPABLE);
mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val);
- if (tp->support_2500full) {
- linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported);
-
+ if (tp->support_2500full || tp->support_5000full) {
val = ocp_reg_read(tp, OCP_EEE_ADV2);
mii_eee_cap2_mod_linkmode_adv_t(eee->advertised, val);
val = ocp_reg_read(tp, OCP_EEE_LPABLE2);
mii_eee_cap2_mod_linkmode_adv_t(eee->lp_advertised, val);
+ }
+
+ if (tp->support_2500full) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported);
if (speed & _2500bps)
linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, common);
}
+ if (tp->support_5000full) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, eee->supported);
+
+ if (speed & _5000bps)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, common);
+ }
+
eee->eee_enabled = tp->eee_en;
if (speed & _1000bps)
@@ -9381,6 +9440,11 @@ static int rtl8152_probe_once(struct usb
} else {
tp->speed = SPEED_1000;
}
+ if (tp->support_5000full &&
+ tp->udev->speed >= USB_SPEED_SUPER) {
+ tp->speed = SPEED_5000;
+ tp->advertising |= RTL_ADVERTISED_5000_FULL;
+ }
tp->advertising |= RTL_ADVERTISED_1000_FULL;
}
tp->duplex = DUPLEX_FULL;
target/linux/generic/backport-6.18/747-v7.1-r8152-Add-support-for-the-RTL8157-hardware.patch
+1553
View File
File diff suppressed because it is too large Load Diff
target/linux/generic/backport-6.18/907-v6.19-genirq-Change-hwirq-parameter-to-irq_hw_number_t.patch
+66
View File
@@ -0,0 +1,66 @@
From 455a65260f526cedd4680d4836ebdf2eaf1ab4c6 Mon Sep 17 00:00:00 2001
From: Tobias Schumacher <ts@linux.ibm.com>
Date: Thu, 4 Dec 2025 06:05:01 +0100
Subject: [PATCH] genirq: Change hwirq parameter to irq_hw_number_t
The irqdomain implementation internally represents hardware IRQs as
irq_hw_number_t, which is defined as unsigned long int. When providing
an irq_hw_number_t to the generic_handle_domain() functions that expect
and unsigned int hwirq, this can lead to a loss of information. Change
the hwirq parameter to irq_hw_number_t to support the full range of
hwirqs.
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Niklas Schnelle <schnelle@linux.ibm.com>
Reviewed-by: Farhan Ali <alifm@linux.ibm.com>
Signed-off-by: Tobias Schumacher <ts@linux.ibm.com>
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
---
include/linux/irqdesc.h | 6 +++---
kernel/irq/irqdesc.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
--- a/include/linux/irqdesc.h
+++ b/include/linux/irqdesc.h
@@ -183,9 +183,9 @@ int generic_handle_irq_safe(unsigned int
* and handle the result interrupt number. Return -EINVAL if
* conversion failed.
*/
-int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq);
-int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq);
-int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq);
+int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq);
+int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq);
+int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq);
#endif
/* Test to see if a driver has successfully requested an irq */
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -720,7 +720,7 @@ EXPORT_SYMBOL_GPL(generic_handle_irq_saf
* This function must be called from an IRQ context with irq regs
* initialized.
*/
-int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq)
+int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq)
{
return handle_irq_desc(irq_resolve_mapping(domain, hwirq));
}
@@ -738,7 +738,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_
* context). If the interrupt is marked as 'enforce IRQ-context only' then
* the function must be invoked from hard interrupt context.
*/
-int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq)
+int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq)
{
unsigned long flags;
int ret;
@@ -761,7 +761,7 @@ EXPORT_SYMBOL_GPL(generic_handle_domain_
* This function must be called from an NMI context with irq regs
* initialized.
**/
-int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq)
+int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq)
{
WARN_ON_ONCE(!in_nmi());
return handle_irq_desc(irq_resolve_mapping(domain, hwirq));
target/linux/generic/backport-6.18/908-1-v7.0-genirq-Add-interrupt-redirection-infrastructure.patch
+319
View File
@@ -0,0 +1,319 @@
From fcc1d0dabdb65ca069f77e5b76d3b20277be4a15 Mon Sep 17 00:00:00 2001
From: Radu Rendec <rrendec@redhat.com>
Date: Fri, 28 Nov 2025 16:20:53 -0500
Subject: [PATCH] genirq: Add interrupt redirection infrastructure
Add infrastructure to redirect interrupt handler execution to a
different CPU when the current CPU is not part of the interrupt's CPU
affinity mask.
This is primarily aimed at (de)multiplexed interrupts, where the child
interrupt handler runs in the context of the parent interrupt handler,
and therefore CPU affinity control for the child interrupt is typically
not available.
With the new infrastructure, the child interrupt is allowed to freely
change its affinity setting, independently of the parent. If the
interrupt handler happens to be triggered on an "incompatible" CPU (a
CPU that's not part of the child interrupt's affinity mask), the handler
is redirected and runs in IRQ work context on a "compatible" CPU.
No functional change is being made to any existing irqchip driver, and
irqchip drivers must be explicitly modified to use the newly added
infrastructure to support interrupt redirection.
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Radu Rendec <rrendec@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/
Link: https://patch.msgid.link/20251128212055.1409093-2-rrendec@redhat.com
---
include/linux/irq.h | 10 +++++
include/linux/irqdesc.h | 17 +++++++-
kernel/irq/chip.c | 22 ++++++++++-
kernel/irq/irqdesc.c | 86 ++++++++++++++++++++++++++++++++++++++++-
kernel/irq/manage.c | 15 ++++++-
5 files changed, 144 insertions(+), 6 deletions(-)
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -459,6 +459,8 @@ static inline irq_hw_number_t irqd_to_hw
* checks against the supplied affinity mask are not
* required. This is used for CPU hotplug where the
* target CPU is not yet set in the cpu_online_mask.
+ * @irq_pre_redirect: Optional function to be invoked before redirecting
+ * an interrupt via irq_work. Called only on CONFIG_SMP.
* @irq_retrigger: resend an IRQ to the CPU
* @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
* @irq_set_wake: enable/disable power-management wake-on of an IRQ
@@ -503,6 +505,7 @@ struct irq_chip {
void (*irq_eoi)(struct irq_data *data);
int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
+ void (*irq_pre_redirect)(struct irq_data *data);
int (*irq_retrigger)(struct irq_data *data);
int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
int (*irq_set_wake)(struct irq_data *data, unsigned int on);
@@ -688,6 +691,13 @@ extern int irq_chip_set_vcpu_affinity_pa
extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
extern int irq_chip_request_resources_parent(struct irq_data *data);
extern void irq_chip_release_resources_parent(struct irq_data *data);
+#ifdef CONFIG_SMP
+void irq_chip_pre_redirect_parent(struct irq_data *data);
+#endif
+#endif
+
+#ifdef CONFIG_SMP
+int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force);
#endif
/* Disable or mask interrupts during a kernel kexec */
--- a/include/linux/irqdesc.h
+++ b/include/linux/irqdesc.h
@@ -2,9 +2,10 @@
#ifndef _LINUX_IRQDESC_H
#define _LINUX_IRQDESC_H
-#include <linux/rcupdate.h>
+#include <linux/irq_work.h>
#include <linux/kobject.h>
#include <linux/mutex.h>
+#include <linux/rcupdate.h>
/*
* Core internal functions to deal with irq descriptors
@@ -30,6 +31,17 @@ struct irqstat {
};
/**
+ * struct irq_redirect - interrupt redirection metadata
+ * @work: Harg irq_work item for handler execution on a different CPU
+ * @target_cpu: CPU to run irq handler on in case the current CPU is not part
+ * of the irq affinity mask
+ */
+struct irq_redirect {
+ struct irq_work work;
+ unsigned int target_cpu;
+};
+
+/**
* struct irq_desc - interrupt descriptor
* @irq_common_data: per irq and chip data passed down to chip functions
* @kstat_irqs: irq stats per cpu
@@ -46,6 +58,7 @@ struct irqstat {
* @threads_handled: stats field for deferred spurious detection of threaded handlers
* @threads_handled_last: comparator field for deferred spurious detection of threaded handlers
* @lock: locking for SMP
+ * @redirect: Facility for redirecting interrupts via irq_work
* @affinity_hint: hint to user space for preferred irq affinity
* @affinity_notify: context for notification of affinity changes
* @pending_mask: pending rebalanced interrupts
@@ -84,6 +97,7 @@ struct irq_desc {
struct cpumask *percpu_enabled;
const struct cpumask *percpu_affinity;
#ifdef CONFIG_SMP
+ struct irq_redirect redirect;
const struct cpumask *affinity_hint;
struct irq_affinity_notify *affinity_notify;
#ifdef CONFIG_GENERIC_PENDING_IRQ
@@ -186,6 +200,7 @@ int generic_handle_irq_safe(unsigned int
int generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq);
int generic_handle_domain_irq_safe(struct irq_domain *domain, irq_hw_number_t hwirq);
int generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq);
+bool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq);
#endif
/* Test to see if a driver has successfully requested an irq */
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -1143,7 +1143,7 @@ void irq_cpu_offline(void)
}
#endif
-#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
+#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
#ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS
/**
@@ -1215,6 +1215,15 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_ir
#endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */
+#ifdef CONFIG_SMP
+void irq_chip_pre_redirect_parent(struct irq_data *data)
+{
+ data = data->parent_data;
+ data->chip->irq_pre_redirect(data);
+}
+EXPORT_SYMBOL_GPL(irq_chip_pre_redirect_parent);
+#endif
+
/**
* irq_chip_set_parent_state - set the state of a parent interrupt.
*
@@ -1497,6 +1506,17 @@ void irq_chip_release_resources_parent(s
data->chip->irq_release_resources(data);
}
EXPORT_SYMBOL_GPL(irq_chip_release_resources_parent);
+#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
+
+#ifdef CONFIG_SMP
+int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force)
+{
+ struct irq_redirect *redir = &irq_data_to_desc(data)->redirect;
+
+ WRITE_ONCE(redir->target_cpu, cpumask_first(dest));
+ return IRQ_SET_MASK_OK;
+}
+EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity);
#endif
/**
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -78,8 +78,12 @@ static int alloc_masks(struct irq_desc *
return 0;
}
-static void desc_smp_init(struct irq_desc *desc, int node,
- const struct cpumask *affinity)
+static void irq_redirect_work(struct irq_work *work)
+{
+ handle_irq_desc(container_of(work, struct irq_desc, redirect.work));
+}
+
+static void desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity)
{
if (!affinity)
affinity = irq_default_affinity;
@@ -91,6 +95,7 @@ static void desc_smp_init(struct irq_des
#ifdef CONFIG_NUMA
desc->irq_common_data.node = node;
#endif
+ desc->redirect.work = IRQ_WORK_INIT_HARD(irq_redirect_work);
}
static void free_masks(struct irq_desc *desc)
@@ -766,6 +771,83 @@ int generic_handle_domain_nmi(struct irq
WARN_ON_ONCE(!in_nmi());
return handle_irq_desc(irq_resolve_mapping(domain, hwirq));
}
+
+#ifdef CONFIG_SMP
+static bool demux_redirect_remote(struct irq_desc *desc)
+{
+ guard(raw_spinlock)(&desc->lock);
+ const struct cpumask *m = irq_data_get_effective_affinity_mask(&desc->irq_data);
+ unsigned int target_cpu = READ_ONCE(desc->redirect.target_cpu);
+
+ if (desc->irq_data.chip->irq_pre_redirect)
+ desc->irq_data.chip->irq_pre_redirect(&desc->irq_data);
+
+ /*
+ * If the interrupt handler is already running on a CPU that's included
+ * in the interrupt's affinity mask, redirection is not necessary.
+ */
+ if (cpumask_test_cpu(smp_processor_id(), m))
+ return false;
+
+ /*
+ * The desc->action check protects against IRQ shutdown: __free_irq() sets
+ * desc->action to NULL while holding desc->lock, which we also hold.
+ *
+ * Calling irq_work_queue_on() here is safe w.r.t. CPU unplugging:
+ * - takedown_cpu() schedules multi_cpu_stop() on all active CPUs,
+ * including the one that's taken down.
+ * - multi_cpu_stop() acts like a barrier, which means all active
+ * CPUs go through MULTI_STOP_DISABLE_IRQ and disable hard IRQs
+ * *before* the dying CPU runs take_cpu_down() in MULTI_STOP_RUN.
+ * - Hard IRQs are re-enabled at the end of multi_cpu_stop(), *after*
+ * the dying CPU has run take_cpu_down() in MULTI_STOP_RUN.
+ * - Since we run in hard IRQ context, we run either before or after
+ * take_cpu_down() but never concurrently.
+ * - If we run before take_cpu_down(), the dying CPU hasn't been marked
+ * offline yet (it's marked via take_cpu_down() -> __cpu_disable()),
+ * so the WARN in irq_work_queue_on() can't occur.
+ * - Furthermore, the work item we queue will be flushed later via
+ * take_cpu_down() -> cpuhp_invoke_callback_range_nofail() ->
+ * smpcfd_dying_cpu() -> irq_work_run().
+ * - If we run after take_cpu_down(), target_cpu has been already
+ * updated via take_cpu_down() -> __cpu_disable(), which eventually
+ * calls irq_do_set_affinity() during IRQ migration. So, target_cpu
+ * no longer points to the dying CPU in this case.
+ */
+ if (desc->action)
+ irq_work_queue_on(&desc->redirect.work, target_cpu);
+
+ return true;
+}
+#else /* CONFIG_SMP */
+static bool demux_redirect_remote(struct irq_desc *desc)
+{
+ return false;
+}
+#endif
+
+/**
+ * generic_handle_demux_domain_irq - Invoke the handler for a hardware interrupt
+ * of a demultiplexing domain.
+ * @domain: The domain where to perform the lookup
+ * @hwirq: The hardware interrupt number to convert to a logical one
+ *
+ * Returns: True on success, or false if lookup has failed
+ */
+bool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq)
+{
+ struct irq_desc *desc = irq_resolve_mapping(domain, hwirq);
+
+ if (unlikely(!desc))
+ return false;
+
+ if (demux_redirect_remote(desc))
+ return true;
+
+ return !handle_irq_desc(desc);
+}
+EXPORT_SYMBOL_GPL(generic_handle_demux_domain_irq);
+
#endif
/* Dynamic interrupt handling */
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -35,6 +35,16 @@ static int __init setup_forced_irqthread
early_param("threadirqs", setup_forced_irqthreads);
#endif
+#ifdef CONFIG_SMP
+static inline void synchronize_irqwork(struct irq_desc *desc)
+{
+ /* Synchronize pending or on the fly redirect work */
+ irq_work_sync(&desc->redirect.work);
+}
+#else
+static inline void synchronize_irqwork(struct irq_desc *desc) { }
+#endif
+
static int __irq_get_irqchip_state(struct irq_data *d, enum irqchip_irq_state which, bool *state);
static void __synchronize_hardirq(struct irq_desc *desc, bool sync_chip)
@@ -107,7 +117,9 @@ EXPORT_SYMBOL(synchronize_hardirq);
static void __synchronize_irq(struct irq_desc *desc)
{
+ synchronize_irqwork(desc);
__synchronize_hardirq(desc, true);
+
/*
* We made sure that no hardirq handler is running. Now verify that no
* threaded handlers are active.
@@ -217,8 +229,7 @@ static inline void irq_validate_effectiv
static DEFINE_PER_CPU(struct cpumask, __tmp_mask);
-int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask,
- bool force)
+int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
{
struct cpumask *tmp_mask = this_cpu_ptr(&__tmp_mask);
struct irq_desc *desc = irq_data_to_desc(data);
target/linux/generic/backport-6.18/908-2-v7.0-PCI-dwc-Code-cleanup.patch
+242
View File
@@ -0,0 +1,242 @@
From f1875091a01dd634ff5f8b6fc57ab874f755c415 Mon Sep 17 00:00:00 2001
From: Radu Rendec <rrendec@redhat.com>
Date: Fri, 28 Nov 2025 16:20:54 -0500
Subject: [PATCH] PCI: dwc: Code cleanup
Code cleanup with no functional changes. These changes were originally
made by Thomas Gleixner (see Link tag below) in a patch that was never
submitted as is. Other parts of that patch were eventually submitted as
commit 8e717112caf3 ("PCI: dwc: Switch to msi_create_parent_irq_domain()")
and the remaining parts are the code cleanup changes:
- Use guard()/scoped_guard() instead of open-coded lock/unlock.
- Return void in a few functions whose return value is never used.
- Simplify dw_handle_msi_irq() by using for_each_set_bit().
One notable deviation from the original patch is that it reverts back to a
simple 1 by 1 iteration over the controllers inside dw_handle_msi_irq. The
reason is that with the original changes, the IRQ offset was calculated
incorrectly.
This prepares the ground for enabling MSI affinity support, which was
originally part of that same series that Thomas Gleixner prepared.
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Radu Rendec <rrendec@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/
Link: https://patch.msgid.link/20251128212055.1409093-3-rrendec@redhat.com
---
.../pci/controller/dwc/pcie-designware-host.c | 98 ++++++-------------
drivers/pci/controller/dwc/pcie-designware.h | 7 +-
2 files changed, 34 insertions(+), 71 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -46,35 +46,25 @@ static const struct msi_parent_ops dw_pc
};
/* MSI int handler */
-irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
+void dw_handle_msi_irq(struct dw_pcie_rp *pp)
{
- int i, pos;
- unsigned long val;
- u32 status, num_ctrls;
- irqreturn_t ret = IRQ_NONE;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ unsigned int i, num_ctrls;
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
for (i = 0; i < num_ctrls; i++) {
- status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
- (i * MSI_REG_CTRL_BLOCK_SIZE));
+ unsigned int reg_off = i * MSI_REG_CTRL_BLOCK_SIZE;
+ unsigned int irq_off = i * MAX_MSI_IRQS_PER_CTRL;
+ unsigned long status, pos;
+
+ status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + reg_off);
if (!status)
continue;
- ret = IRQ_HANDLED;
- val = status;
- pos = 0;
- while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
- pos)) != MAX_MSI_IRQS_PER_CTRL) {
- generic_handle_domain_irq(pp->irq_domain,
- (i * MAX_MSI_IRQS_PER_CTRL) +
- pos);
- pos++;
- }
+ for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL)
+ generic_handle_domain_irq(pp->irq_domain, irq_off + pos);
}
-
- return ret;
}
/* Chained MSI interrupt service routine */
@@ -95,13 +85,10 @@ static void dw_pci_setup_msi_msg(struct
{
struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- u64 msi_target;
-
- msi_target = (u64)pp->msi_data;
+ u64 msi_target = (u64)pp->msi_data;
msg->address_lo = lower_32_bits(msi_target);
msg->address_hi = upper_32_bits(msi_target);
-
msg->data = d->hwirq;
dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
@@ -113,18 +100,14 @@ static void dw_pci_bottom_mask(struct ir
struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned int res, bit, ctrl;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&pp->lock, flags);
+ guard(raw_spinlock)(&pp->lock);
ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
pp->irq_mask[ctrl] |= BIT(bit);
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
-
- raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static void dw_pci_bottom_unmask(struct irq_data *d)
@@ -132,18 +115,14 @@ static void dw_pci_bottom_unmask(struct
struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned int res, bit, ctrl;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&pp->lock, flags);
+ guard(raw_spinlock)(&pp->lock);
ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
pp->irq_mask[ctrl] &= ~BIT(bit);
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
-
- raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static void dw_pci_bottom_ack(struct irq_data *d)
@@ -160,54 +139,42 @@ static void dw_pci_bottom_ack(struct irq
}
static struct irq_chip dw_pci_msi_bottom_irq_chip = {
- .name = "DWPCI-MSI",
- .irq_ack = dw_pci_bottom_ack,
- .irq_compose_msi_msg = dw_pci_setup_msi_msg,
- .irq_mask = dw_pci_bottom_mask,
- .irq_unmask = dw_pci_bottom_unmask,
+ .name = "DWPCI-MSI",
+ .irq_ack = dw_pci_bottom_ack,
+ .irq_compose_msi_msg = dw_pci_setup_msi_msg,
+ .irq_mask = dw_pci_bottom_mask,
+ .irq_unmask = dw_pci_bottom_unmask,
};
-static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
- unsigned int virq, unsigned int nr_irqs,
- void *args)
+static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *args)
{
struct dw_pcie_rp *pp = domain->host_data;
- unsigned long flags;
- u32 i;
int bit;
- raw_spin_lock_irqsave(&pp->lock, flags);
-
- bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
- order_base_2(nr_irqs));
-
- raw_spin_unlock_irqrestore(&pp->lock, flags);
+ scoped_guard (raw_spinlock_irq, &pp->lock) {
+ bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
+ order_base_2(nr_irqs));
+ }
if (bit < 0)
return -ENOSPC;
- for (i = 0; i < nr_irqs; i++)
- irq_domain_set_info(domain, virq + i, bit + i,
- pp->msi_irq_chip,
- pp, handle_edge_irq,
- NULL, NULL);
-
+ for (unsigned int i = 0; i < nr_irqs; i++) {
+ irq_domain_set_info(domain, virq + i, bit + i, pp->msi_irq_chip,
+ pp, handle_edge_irq, NULL, NULL);
+ }
return 0;
}
-static void dw_pcie_irq_domain_free(struct irq_domain *domain,
- unsigned int virq, unsigned int nr_irqs)
+static void dw_pcie_irq_domain_free(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs)
{
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
struct dw_pcie_rp *pp = domain->host_data;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&pp->lock, flags);
-
- bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
- order_base_2(nr_irqs));
- raw_spin_unlock_irqrestore(&pp->lock, flags);
+ guard(raw_spinlock_irq)(&pp->lock);
+ bitmap_release_region(pp->msi_irq_in_use, d->hwirq, order_base_2(nr_irqs));
}
static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
@@ -240,8 +207,7 @@ void dw_pcie_free_msi(struct dw_pcie_rp
for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
if (pp->msi_irq[ctrl] > 0)
- irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
- NULL, NULL);
+ irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL);
}
irq_domain_remove(pp->irq_domain);
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -810,7 +810,7 @@ static inline enum dw_pcie_ltssm dw_pcie
#ifdef CONFIG_PCIE_DW_HOST
int dw_pcie_suspend_noirq(struct dw_pcie *pci);
int dw_pcie_resume_noirq(struct dw_pcie *pci);
-irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
+void dw_handle_msi_irq(struct dw_pcie_rp *pp);
void dw_pcie_msi_init(struct dw_pcie_rp *pp);
int dw_pcie_msi_host_init(struct dw_pcie_rp *pp);
void dw_pcie_free_msi(struct dw_pcie_rp *pp);
@@ -831,10 +831,7 @@ static inline int dw_pcie_resume_noirq(s
return 0;
}
-static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
-{
- return IRQ_NONE;
-}
+static inline void dw_handle_msi_irq(struct dw_pcie_rp *pp) { }
static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp)
{ }
target/linux/generic/backport-6.18/908-3-v7.0-PCI-dwc-Enable-MSI-affinity-support.patch
+92
View File
@@ -0,0 +1,92 @@
From eaf290c404f7c39f23292e9ce83b8b5b51ab598a Mon Sep 17 00:00:00 2001
From: Radu Rendec <rrendec@redhat.com>
Date: Fri, 28 Nov 2025 16:20:55 -0500
Subject: [PATCH] PCI: dwc: Enable MSI affinity support
Leverage the interrupt redirection infrastructure to enable CPU affinity
support for MSI interrupts. Since the parent interrupt affinity cannot
be changed, affinity control for the child interrupt (MSI) is achieved
by redirecting the handler to run in IRQ work context on the target CPU.
This patch was originally prepared by Thomas Gleixner (see Link tag below)
in a patch series that was never submitted as is, and only parts of that
series have made it upstream so far.
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Radu Rendec <rrendec@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/
Link: https://patch.msgid.link/20251128212055.1409093-4-rrendec@redhat.com
---
.../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++++++---
1 file changed, 28 insertions(+), 5 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -26,9 +26,27 @@ static struct pci_ops dw_pcie_ops;
static struct pci_ops dw_pcie_ecam_ops;
static struct pci_ops dw_child_pcie_ops;
+#ifdef CONFIG_SMP
+static void dw_irq_noop(struct irq_data *d) { }
+#endif
+
+static bool dw_pcie_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
+ struct irq_domain *real_parent, struct msi_domain_info *info)
+{
+ if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
+ return false;
+
+#ifdef CONFIG_SMP
+ info->chip->irq_ack = dw_irq_noop;
+ info->chip->irq_pre_redirect = irq_chip_pre_redirect_parent;
+#else
+ info->chip->irq_ack = irq_chip_ack_parent;
+#endif
+ return true;
+}
+
#define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
MSI_FLAG_USE_DEF_CHIP_OPS | \
- MSI_FLAG_NO_AFFINITY | \
MSI_FLAG_PCI_MSI_MASK_PARENT)
#define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \
MSI_FLAG_PCI_MSIX | \
@@ -40,9 +58,8 @@ static const struct msi_parent_ops dw_pc
.required_flags = DW_PCIE_MSI_FLAGS_REQUIRED,
.supported_flags = DW_PCIE_MSI_FLAGS_SUPPORTED,
.bus_select_token = DOMAIN_BUS_PCI_MSI,
- .chip_flags = MSI_CHIP_FLAG_SET_ACK,
.prefix = "DW-",
- .init_dev_msi_info = msi_lib_init_dev_msi_info,
+ .init_dev_msi_info = dw_pcie_init_dev_msi_info,
};
/* MSI int handler */
@@ -63,7 +80,7 @@ void dw_handle_msi_irq(struct dw_pcie_rp
continue;
for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL)
- generic_handle_domain_irq(pp->irq_domain, irq_off + pos);
+ generic_handle_demux_domain_irq(pp->irq_domain, irq_off + pos);
}
}
@@ -140,10 +157,16 @@ static void dw_pci_bottom_ack(struct irq
static struct irq_chip dw_pci_msi_bottom_irq_chip = {
.name = "DWPCI-MSI",
- .irq_ack = dw_pci_bottom_ack,
.irq_compose_msi_msg = dw_pci_setup_msi_msg,
.irq_mask = dw_pci_bottom_mask,
.irq_unmask = dw_pci_bottom_unmask,
+#ifdef CONFIG_SMP
+ .irq_ack = dw_irq_noop,
+ .irq_pre_redirect = dw_pci_bottom_ack,
+ .irq_set_affinity = irq_chip_redirect_set_affinity,
+#else
+ .irq_ack = dw_pci_bottom_ack,
+#endif
};
static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
target/linux/generic/backport-6.18/909-v7.0-genirq-Update-effective-affinity-for-redirected-inte.patch
+56
View File
@@ -0,0 +1,56 @@
From df439718afaf23b5aa7b5711b6c14e87b5836cae Mon Sep 17 00:00:00 2001
From: Radu Rendec <rrendec@redhat.com>
Date: Mon, 12 Jan 2026 16:14:02 -0500
Subject: [PATCH] genirq: Update effective affinity for redirected
interrupts
For redirected interrupts, irq_chip_redirect_set_affinity() does not
update the effective affinity mask, which then triggers the warning in
irq_validate_effective_affinity(). Also, because the effective affinity
mask is empty, the cpumask_test_cpu(smp_processor_id(), m) condition in
demux_redirect_remote() is always false, and the interrupt is always
redirected, even if it's already running on the target CPU.
Set the effective affinity mask to be the same as the requested affinity
mask. It's worth noting that irq_do_set_affinity() filters out offline
CPUs before calling chip->irq_set_affinity() (unless `force` is set), so
the mask passed to irq_chip_redirect_set_affinity() is already filtered.
The solution is not ideal because it may lie about the effective
affinity of the demultiplexed ("child") interrupt. If the requested
affinity mask includes multiple CPUs, the effective affinity, in
reality, is the intersection between the requested mask and the
demultiplexing ("parent") interrupt's effective affinity mask, plus
the first CPU in the requested mask.
Accurately describing the effective affinity of the demultiplexed
interrupt is not trivial because it requires keeping track of the
demultiplexing interrupt's effective affinity. That is tricky in the
context of CPU hot(un)plugging, where interrupt migration ordering is
not guaranteed. The solution in the initial version of the fixed patch,
which stored the first CPU of the demultiplexing interrupt's effective
affinity in the `target_cpu` field, has its own drawbacks and
limitations.
Fixes: fcc1d0dabdb6 ("genirq: Add interrupt redirection infrastructure")
Reported-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Radu Rendec <rrendec@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260112211402.2927336-1-rrendec@redhat.com
Closes: https://lore.kernel.org/all/44509520-f29b-4b8a-8986-5eae3e022eb7@nvidia.com/
---
kernel/irq/chip.c | 2 ++
1 file changed, 2 insertions(+)
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -1514,6 +1514,8 @@ int irq_chip_redirect_set_affinity(struc
struct irq_redirect *redir = &irq_data_to_desc(data)->redirect;
WRITE_ONCE(redir->target_cpu, cpumask_first(dest));
+ irq_data_update_effective_affinity(data, dest);
+
return IRQ_SET_MASK_OK;
}
EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity);
target/linux/generic/files/drivers/net/phy/rtl8261n/phy_patch.c
-15
View File
@@ -98,11 +98,6 @@ static int32 _phy_patch_process(uint32 unit, rtk_port_t port, uint8 portOffset,
return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK;
}
rtk_hwpatch_t rtl826XB_patch_rtk_conf[] = {
{RTK_PATCH_OP_PSDS0 , 0xff , 0x07 , 0x10 , 15, 0, 0x80aa, RTK_PATCH_CMP_WC , 0, 0, 0, 0},
{RTK_PATCH_OP_PSDS0 , 0xff , 0x06 , 0x12 , 15, 0, 0x5078, RTK_PATCH_CMP_WC , 0, 0, 0, 0},
};
/* Function Name:
* phy_patch
* Description:
@@ -175,16 +170,6 @@ int32 phy_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode
break;
}
}
#ifdef CONFIG_MACH_REALTEK_RTL
ret = _phy_patch_process(unit, port, portOffset, rtl826XB_patch_rtk_conf, sizeof(rtl826XB_patch_rtk_conf), patch_mode);
if (ret == RT_ERR_CHECK_FAILED)
chk_ret = ret;
else if (ret != RT_ERR_OK)
{
RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", unit, port, patch_mode, i, patch_type, ret);
return ret;
}
#endif
return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK;
}
target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c
+1 -3
View File
@@ -78,12 +78,10 @@ static int rtkphy_config_init(struct phy_device *phydev)
case REALTEK_PHY_ID_RTL8264B:
case REALTEK_PHY_ID_RTL8264:
phydev_info(phydev, "%s:%u [RTL8261N/RTL8264/RTL826XB] phy_id: 0x%X PHYAD:%d\n", __FUNCTION__, __LINE__, phydev->drv->phy_id, phydev->mdio.addr);
#ifdef CONFIG_MACH_REALTEK_RTL
return 0;
#endif
#if 1 /* toggle reset */
phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 1);
mdelay(30);
phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 0);
mdelay(30);
#endif
target/linux/generic/hack-6.18/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
+4 -4
View File
@@ -15,7 +15,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -116,6 +116,29 @@
@@ -120,6 +120,29 @@
#define AQR107_OP_IN_PROG_SLEEP 1000
#define AQR107_OP_IN_PROG_TIMEOUT 100000
@@ -45,7 +45,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
static int aqr107_get_sset_count(struct phy_device *phydev)
{
return AQR107_SGMII_STAT_SZ;
@@ -250,6 +273,51 @@ static int aqr_config_aneg(struct phy_de
@@ -264,6 +287,51 @@ static int aqr_config_aneg(struct phy_de
return genphy_c45_check_and_restart_aneg(phydev, changed);
}
@@ -97,7 +97,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
static int aqr_config_intr(struct phy_device *phydev)
{
bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
@@ -1338,7 +1406,7 @@ static struct phy_driver aqr_driver[] =
@@ -1356,7 +1424,7 @@ static struct phy_driver aqr_driver[] =
.name = "Aquantia AQR112",
.probe = aqr107_probe,
.config_init = aqr_gen3_config_init,
@@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
.config_intr = aqr_config_intr,
.handle_interrupt = aqr_handle_interrupt,
.get_tunable = aqr107_get_tunable,
@@ -1364,7 +1432,7 @@ static struct phy_driver aqr_driver[] =
@@ -1382,7 +1450,7 @@ static struct phy_driver aqr_driver[] =
.name = "Aquantia AQR412",
.probe = aqr107_probe,
.config_init = aqr_gen3_config_init,
target/linux/generic/hack-6.18/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
+1 -1
View File
@@ -14,7 +14,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -306,10 +306,16 @@ static int aqr_config_aneg_set_prot(stru
@@ -320,10 +320,16 @@ static int aqr_config_aneg_set_prot(stru
phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
aquantia_syscfg[if_type].start_rate);
target/linux/generic/hack-6.18/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
+54 -26
View File
@@ -12,52 +12,80 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -34,6 +34,8 @@
#define PHY_ID_AQR115 0x31c31c63
#define PHY_ID_AQR115C 0x31c31c33
#define PHY_ID_AQR813 0x31c31cb2
@@ -26,6 +26,8 @@
#define PHY_ID_AQR111 0x03a1b610
#define PHY_ID_AQR111B0 0x03a1b612
#define PHY_ID_AQR112 0x03a1b662
+#define PHY_ID_AQR112C 0x03a1b790
+#define PHY_ID_AQR112R 0x31c31d12
#define MDIO_PHYXS_VEND_PROV2 0xc441
#define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3)
@@ -1634,6 +1636,30 @@ static struct phy_driver aqr_driver[] =
.inband_caps = aqr_gen2_inband_caps,
#define PHY_ID_AQR412 0x03a1b6f2
#define PHY_ID_AQR412C 0x03a1b712
#define PHY_ID_AQR113 0x31c31c40
@@ -1452,6 +1454,58 @@ static struct phy_driver aqr_driver[] =
.config_inband = aqr_gen2_config_inband,
},
+{
{
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C),
+ .name = "Aquantia AQR112C",
+ .probe = aqr107_probe,
+ .config_aneg = aqr_config_aneg,
+ .config_init = aqr_gen3_config_init,
+ .config_aneg = aqr_config_aneg_set_prot,
+ .config_intr = aqr_config_intr,
+ .handle_interrupt = aqr_handle_interrupt,
+ .read_status = aqr_read_status,
+ .get_sset_count = aqr107_get_sset_count,
+ .get_tunable = aqr107_get_tunable,
+ .set_tunable = aqr107_set_tunable,
+ .suspend = aqr_gen1_suspend,
+ .resume = aqr_gen1_resume,
+ .read_status = aqr_gen2_read_status,
+ .get_rate_matching = aqr_gen2_get_rate_matching,
+ .get_sset_count = aqr107_get_sset_count,
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
+ .led_brightness_set = aqr_phy_led_brightness_set,
+ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
+ .led_hw_control_set = aqr_phy_led_hw_control_set,
+ .led_hw_control_get = aqr_phy_led_hw_control_get,
+ .led_polarity_set = aqr_phy_led_polarity_set,
+ .inband_caps = aqr_gen2_inband_caps,
+ .config_inband = aqr_gen2_config_inband,
+},
+{
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R),
+ .name = "Aquantia AQR112R",
+ .probe = aqr107_probe,
+ .config_aneg = aqr_config_aneg_set_prot,
+ .config_init = aqr_gen3_config_init,
+ .config_aneg = aqr_config_aneg_set_prot,
+ .config_intr = aqr_config_intr,
+ .handle_interrupt = aqr_handle_interrupt,
+ .read_status = aqr_read_status,
+ .get_sset_count = aqr107_get_sset_count,
+ .get_tunable = aqr107_get_tunable,
+ .set_tunable = aqr107_set_tunable,
+ .suspend = aqr_gen1_suspend,
+ .resume = aqr_gen1_resume,
+ .read_status = aqr_gen2_read_status,
+ .get_rate_matching = aqr_gen2_get_rate_matching,
+ .get_sset_count = aqr107_get_sset_count,
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
+ .led_brightness_set = aqr_phy_led_brightness_set,
+ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
+ .led_hw_control_set = aqr_phy_led_hw_control_set,
+ .led_hw_control_get = aqr_phy_led_hw_control_get,
+ .led_polarity_set = aqr_phy_led_polarity_set,
+ .inband_caps = aqr_gen2_inband_caps,
+ .config_inband = aqr_gen2_config_inband,
+},
};
module_phy_driver(aqr_driver);
@@ -1657,6 +1683,8 @@ static const struct mdio_device_id __may
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR115) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+{
PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
.name = "Aquantia AQR412",
.probe = aqr107_probe,
@@ -1693,6 +1747,8 @@ static const struct mdio_device_id __may
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
{ }
};
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
target/linux/generic/hack-6.18/760-net-usb-r8152-add-LED-configuration-from-OF.patch
+8 -8
View File
@@ -22,8 +22,8 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
#include <linux/crc32.h>
#include <linux/if_vlan.h>
#include <linux/uaccess.h>
@@ -7019,6 +7020,22 @@ static void rtl_tally_reset(struct r8152
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
@@ -7193,6 +7194,22 @@ static void rtl_tally_reset(struct r8152
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RSTTALLY, TALLY_RESET);
}
+static int r8152_led_configuration(struct r8152 *tp)
@@ -45,16 +45,16 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
static void r8152b_init(struct r8152 *tp)
{
u32 ocp_data;
@@ -7060,6 +7077,8 @@ static void r8152b_init(struct r8152 *tp
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
@@ -7225,6 +7242,8 @@ static void r8152b_init(struct r8152 *tp
/* enable rx aggregation */
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL,
RX_AGG_DISABLE | RX_ZERO_EN);
+
+ r8152_led_configuration(tp);
}
static void r8153_init(struct r8152 *tp)
@@ -7200,6 +7219,8 @@ static void r8153_init(struct r8152 *tp)
@@ -7342,6 +7361,8 @@ static void r8153_init(struct r8152 *tp)
tp->coalesce = COALESCE_SLOW;
break;
}
@@ -63,7 +63,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
}
static void r8153b_init(struct r8152 *tp)
@@ -7282,6 +7303,8 @@ static void r8153b_init(struct r8152 *tp
@@ -7412,6 +7433,8 @@ static void r8153b_init(struct r8152 *tp
rtl_tally_reset(tp);
tp->coalesce = 15000; /* 15 us */
target/linux/generic/pending-6.12/720-07-net-phy-realtek-disable-MDIO-broadcast.patch
+18 -4
View File
@@ -21,13 +21,27 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
#define RTL8366RB_POWER_SAVE 0x15
#define RTL8366RB_POWER_SAVE_ON BIT(12)
@@ -1358,7 +1359,8 @@ static int rtl822x_init_phycr1(struct ph
@@ -1351,14 +1352,21 @@ static int rtl822xb_write_mmd(struct phy
static int rtl822x_init_phycr1(struct phy_device *phydev, bool no_aldps)
{
struct rtl822x_priv *priv = phydev->priv;
+ u16 mask = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN;
u16 val = 0;
+ /* The controller in some SFP modules uses MDIO address 0 to access the
+ * PHY. Leave the MDIO broadcast configuration bit alone for SFP
+ * modules, as it won't cause any issues there anyways.
+ */
+ if (!phydev->is_on_sfp_module)
+ mask |= RTL8221B_PHYCR1_PHYAD_0_EN;
+
if (priv->enable_aldps && !no_aldps)
val = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN;
return phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL8221B_PHYCR1,
RTL8221B_PHYCR1_ALDPS_EN |
- RTL8221B_PHYCR1_ALDPS_EN |
- RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN, val);
+ RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN |
+ RTL8221B_PHYCR1_PHYAD_0_EN, val);
+ mask, val);
}
static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1)
target/linux/generic/pending-6.12/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch
+1 -1
View File
@@ -11,7 +11,7 @@ interface mode if the PHY is connected using Clause-45 MDIO.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- a/drivers/net/phy/realtek/realtek_main.c
+++ b/drivers/net/phy/realtek/realtek_main.c
@@ -1387,7 +1387,7 @@ static int rtl822x_set_serdes_option_mod
@@ -1393,7 +1393,7 @@ static int rtl822x_set_serdes_option_mod
return 0;
/* determine SerDes option mode */
target/linux/generic/pending-6.18/715-net-phy-aquantia-add-support-for-CUX3410.patch
+102
View File
@@ -0,0 +1,102 @@
From c52f17573b48bdb09be946ba5d70c206ef9b2ab0 Mon Sep 17 00:00:00 2001
From: Chad Monroe <chad@monroe.io>
Date: Fri, 11 Oct 2024 16:41:37 -0700
Subject: [PATCH] net: phy: aquantia: add support for CUX3410
Add support for Marvell CUX3410. This PHY is nearly identical to
the AQR113C but without MACsec, SyncE and PTP support.
Signed-off-by: Chad Monroe <chad@monroe.io>
---
drivers/net/phy/aquantia/aquantia_main.c | 45 ++++++++++++++++++++++++
1 file changed, 45 insertions(+)
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -34,6 +34,7 @@
#define PHY_ID_AQR115 0x31c31c63
#define PHY_ID_AQR115C 0x31c31c33
#define PHY_ID_AQR813 0x31c31cb2
+#define PHY_ID_CUX3410 0x31c31dd3
#define MDIO_PHYXS_VEND_PROV2 0xc441
#define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3)
@@ -50,6 +51,9 @@
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF 9
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
+#define MDIO_PHYXS_TX_RSVD_VEND_PROV2 0xc441
+#define MDIO_PHYXS_TX_RSVD_VEND_PROV2_ANEG BIT(3)
+
#define MDIO_AN_VEND_PROV 0xc400
#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
@@ -195,6 +199,16 @@ static int aqr_set_mdix(struct phy_devic
MDIO_AN_RESVD_VEND_PROV_MDIX_MASK, val);
}
+static int aqr107_config_usx_aneg_en(struct phy_device *phydev)
+{
+ u16 val;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_TX_RSVD_VEND_PROV2);
+ val |= MDIO_PHYXS_TX_RSVD_VEND_PROV2_ANEG;
+
+ return phy_write_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_TX_RSVD_VEND_PROV2, val);
+}
+
static int aqr_config_aneg(struct phy_device *phydev)
{
bool changed = false;
@@ -806,6 +820,10 @@ static int aqr_gen1_config_init(struct p
if (ret)
return ret;
+ ret = aqr107_config_usx_aneg_en(phydev);
+ if (ret)
+ phydev_err(phydev, "USX autonegotiation disabled, ret: %d\n", ret);
+
ret = aqr107_config_mdi(phydev);
if (ret)
return ret;
@@ -1560,6 +1578,32 @@ static struct phy_driver aqr_driver[] =
.inband_caps = aqr_gen2_inband_caps,
.config_inband = aqr_gen2_config_inband,
},
+{
+ PHY_ID_MATCH_MODEL(PHY_ID_CUX3410),
+ .name = "Aquantia CUX3410",
+ .probe = aqr107_probe,
+ .get_rate_matching = aqr_gen2_get_rate_matching,
+ .config_init = aqr_gen4_config_init,
+ .config_aneg = aqr_config_aneg,
+ .config_intr = aqr_config_intr,
+ .handle_interrupt = aqr_handle_interrupt,
+ .read_status = aqr_gen2_read_status,
+ .get_tunable = aqr107_get_tunable,
+ .set_tunable = aqr107_set_tunable,
+ .suspend = aqr_gen1_suspend,
+ .resume = aqr_gen1_resume,
+ .get_sset_count = aqr107_get_sset_count,
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
+ .led_brightness_set = aqr_phy_led_brightness_set,
+ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
+ .led_hw_control_set = aqr_phy_led_hw_control_set,
+ .led_hw_control_get = aqr_phy_led_hw_control_get,
+ .led_polarity_set = aqr_phy_led_polarity_set,
+ .inband_caps = aqr_gen2_inband_caps,
+ .config_inband = aqr_gen2_config_inband,
+},
};
module_phy_driver(aqr_driver);
@@ -1583,6 +1627,7 @@ static const struct mdio_device_id __may
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR115) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_CUX3410) },
{ }
};
target/linux/generic/pending-6.18/720-07-net-phy-realtek-disable-MDIO-broadcast.patch
+18 -4
View File
@@ -21,13 +21,27 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
#define RTL8366RB_POWER_SAVE 0x15
#define RTL8366RB_POWER_SAVE_ON BIT(12)
@@ -1358,7 +1359,8 @@ static int rtl822x_init_phycr1(struct ph
@@ -1351,14 +1352,21 @@ static int rtl822xb_write_mmd(struct phy
static int rtl822x_init_phycr1(struct phy_device *phydev, bool no_aldps)
{
struct rtl822x_priv *priv = phydev->priv;
+ u16 mask = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN;
u16 val = 0;
+ /* The controller in some SFP modules uses MDIO address 0 to access the
+ * PHY. Leave the MDIO broadcast configuration bit alone for SFP
+ * modules, as it won't cause any issues there anyways.
+ */
+ if (!phydev->is_on_sfp_module)
+ mask |= RTL8221B_PHYCR1_PHYAD_0_EN;
+
if (priv->enable_aldps && !no_aldps)
val = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN;
return phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL8221B_PHYCR1,
RTL8221B_PHYCR1_ALDPS_EN |
- RTL8221B_PHYCR1_ALDPS_EN |
- RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN, val);
+ RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN |
+ RTL8221B_PHYCR1_PHYAD_0_EN, val);
+ mask, val);
}
static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1)
target/linux/generic/pending-6.18/720-08-net-phy-realtek-rate-adapter-in-C22-mode.patch
+1 -1
View File
@@ -11,7 +11,7 @@ interface mode if the PHY is connected using Clause-45 MDIO.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- a/drivers/net/phy/realtek/realtek_main.c
+++ b/drivers/net/phy/realtek/realtek_main.c
@@ -1387,7 +1387,7 @@ static int rtl822x_set_serdes_option_mod
@@ -1393,7 +1393,7 @@ static int rtl822x_set_serdes_option_mod
return 0;
/* determine SerDes option mode */
target/linux/generic/pending-6.18/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch
+8 -5
View File
@@ -1,7 +1,7 @@
From 029c59b9e92776ed1b8f586055d5813132e32f47 Mon Sep 17 00:00:00 2001
From 3bc50ced1c42f0a31173eb65a61307d657109382 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 12 Dec 2023 03:47:31 +0000
Subject: [PATCH 2/4] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
Subject: [PATCH 1/2] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
PCS
MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
@@ -12,13 +12,13 @@ interface modes are also available.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
.../bindings/net/pcs/mediatek,usxgmii.yaml | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
.../bindings/net/pcs/mediatek,usxgmii.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
@@ -0,0 +1,60 @@
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
@@ -63,6 +63,9 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ - clocks
+ - resets
+
+allOf:
+ - $ref: /schemas/phy/phy-common-props.yaml#
+
+additionalProperties: false
+
+examples:
target/linux/generic/pending-6.18/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch
+60 -9
View File
@@ -1,7 +1,7 @@
From c33cd256420ed08ffbedf39971882acc60dc184e Mon Sep 17 00:00:00 2001
From e9d2999f5d9d8e1b895350c569e930918b41ce92 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 12 Dec 2023 03:47:47 +0000
Subject: [PATCH 3/4] net: pcs: add driver for MediaTek USXGMII PCS
Subject: [PATCH 2/2] net: pcs: add driver for MediaTek USXGMII PCS
Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
USXGMII, 10GBase-R and 5GBase-R interface modes.
@@ -9,11 +9,11 @@ USXGMII, 10GBase-R and 5GBase-R interface modes.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
MAINTAINERS | 2 +
drivers/net/pcs/Kconfig | 12 +
drivers/net/pcs/Kconfig | 13 +
drivers/net/pcs/Kconfig.orig | 55 ++++
drivers/net/pcs/Makefile | 1 +
drivers/net/pcs/pcs-mtk-usxgmii.c | 440 ++++++++++++++++++++++++++++++
5 files changed, 510 insertions(+)
drivers/net/pcs/pcs-mtk-usxgmii.c | 490 ++++++++++++++++++++++++++++++
5 files changed, 561 insertions(+)
create mode 100644 drivers/net/pcs/Kconfig.orig
create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
@@ -31,7 +31,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
M: Daniel Golle <daniel@makrotopia.org>
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -33,6 +33,18 @@ config PCS_MTK_LYNXI
@@ -33,6 +33,19 @@ config PCS_MTK_LYNXI
This module provides helpers to phylink for managing the LynxI PCS
which is part of MediaTek's SoC and Ethernet switch ICs.
@@ -39,6 +39,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ tristate "MediaTek USXGMII PCS"
+ select FWNODE_PCS
+ select PCS_MTK_LYNXI
+ select PHY_COMMON_PROPS
+ select PHYLINK
+ imply PHY_MTK_PEXTP
+ help
@@ -118,7 +119,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
--- /dev/null
+++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
@@ -0,0 +1,440 @@
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 MediaTek Inc.
@@ -135,6 +136,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phy/phy-common-props.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
@@ -176,6 +178,12 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+#define USXGMII_LPA GENMASK(15, 0)
+#define USXGMII_LPA_LATCH BIT(31)
+
+/* Register to control SerDes lane polarity */
+#define RG_PHY_TOP_CTRL0 0x82c
+#define USXGMII_PN_SWAP_MASK GENMASK(1, 0)
+#define USXGMII_PN_SWAP_RX BIT(1)
+#define USXGMII_PN_SWAP_TX BIT(0)
+
+/* Register to read PCS link status */
+#define RG_PCS_RX_STATUS0 0x904
+#define RG_PCS_RX_STATUS_UPDATE BIT(16)
@@ -187,6 +195,8 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ * @base: IO memory to access PCS hardware
+ * @clk: Pointer to USXGMII clk
+ * @reset: Pointer to USXGMII reset control
+ * @fwnode: Firmware node of the PCS, used to look up
+ * rx-polarity / tx-polarity properties
+ * @interface: Currently selected interface mode
+ * @neg_mode: Currently used phylink neg_mode
+ * @node: List node
@@ -198,6 +208,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ struct clk *clk;
+ struct reset_control *reset;
+ struct phy *xfi_tphy;
+ struct fwnode_handle *fwnode;
+ phy_interface_t interface;
+ unsigned int neg_mode;
+ struct list_head node;
@@ -232,6 +243,36 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ mdelay(10);
+}
+
+static int mtk_usxgmii_config_polarity(struct mtk_usxgmii_pcs *mpcs,
+ phy_interface_t interface)
+{
+ unsigned int pol;
+ u32 val = 0;
+ int ret;
+
+ if (!mpcs->fwnode)
+ return 0;
+
+ ret = phy_get_rx_polarity(mpcs->fwnode, phy_modes(interface),
+ BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT),
+ PHY_POL_NORMAL, &pol);
+ if (ret)
+ return ret;
+ if (pol == PHY_POL_INVERT)
+ val |= USXGMII_PN_SWAP_RX;
+
+ ret = phy_get_tx_polarity(mpcs->fwnode, phy_modes(interface),
+ BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT),
+ PHY_POL_NORMAL, &pol);
+ if (ret)
+ return ret;
+ if (pol == PHY_POL_INVERT)
+ val |= USXGMII_PN_SWAP_TX;
+
+ mtk_m32(mpcs, RG_PHY_TOP_CTRL0, USXGMII_PN_SWAP_MASK, val);
+ return 0;
+}
+
+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
@@ -240,6 +281,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
+ bool mode_changed = false;
+ int ret;
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
@@ -278,6 +320,10 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ phy_reset(mpcs->xfi_tphy);
+ mtk_usxgmii_reset(mpcs);
+
+ ret = mtk_usxgmii_config_polarity(mpcs, interface);
+ if (ret)
+ return ret;
+
+ /* Setup USXGMII AN ctrl */
+ mtk_m32(mpcs, RG_PCS_AN_CTRL0,
+ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
@@ -467,11 +513,13 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_5GBASER:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ return LINK_INBAND_ENABLE;
+
+ case PHY_INTERFACE_MODE_5GBASER:
+ case PHY_INTERFACE_MODE_10GBASER:
+ return LINK_INBAND_DISABLE;
+
+ default:
+ return 0;
+ }
@@ -505,6 +553,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ mpcs->pcs.poll = true;
+ mpcs->interface = PHY_INTERFACE_MODE_NA;
+ mpcs->neg_mode = -1;
+ mpcs->fwnode = fwnode_handle_get(dev_fwnode(dev));
+
+ __set_bit(PHY_INTERFACE_MODE_5GBASER, mpcs->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, mpcs->pcs.supported_interfaces);
@@ -538,6 +587,8 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ rtnl_lock();
+ phylink_release_pcs(&mpcs->pcs);
+ rtnl_unlock();
+
+ fwnode_handle_put(mpcs->fwnode);
+};
+
+static const struct of_device_id mtk_usxgmii_of_mtable[] = {
target/linux/mediatek/Makefile
+1 -2
View File
@@ -8,8 +8,7 @@ BOARDNAME:=MediaTek ARM
SUBTARGETS:=filogic mt7622 mt7623 mt7629
FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb
KERNEL_PATCHVER:=6.12
KERNEL_TESTING_PATCHVER:=6.18
KERNEL_PATCHVER:=6.18
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax-s.dts
+16
View File
@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "mt7981b-zbtlink-zbt-z8106ax.dtsi"
/ {
model = "Zbtlink ZBT-Z8106AX-S";
compatible = "zbtlink,zbt-z8106ax-s", "mediatek,mt7981b";
};
&port_4 {
/* The 4th port must be defined but isn't usable in model S, so we set it to disabled. */
status = "disabled";
};
target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8106ax.dtsi
+1 -1
View File
@@ -189,7 +189,7 @@
label = "lan4";
};
port@4 {
port_4: port@4 {
reg = <4>;
label = "wwan";
};
target/linux/mediatek/dts/mt7988a-arcadyan-mozart.dts
+3 -2
View File
@@ -5,6 +5,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
/ {
compatible = "arcadyan,mozart", "mediatek,mt7988a";
@@ -71,11 +72,11 @@
};
&usxgmiisys0 {
mediatek,pnswap-rx;
rx-polarity = <PHY_POL_INVERT>;
};
&usxgmiisys1 {
mediatek,pnswap-rx;
rx-polarity = <PHY_POL_INVERT>;
};
&mdio_bus {
target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso
-34
View File
@@ -1,34 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&gmac1>;
__overlay__ {
phy-mode = "2500base-x";
phy-handle = <&phy5>;
};
};
fragment@1 {
target = <&mdio_bus>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
reset-delay-us = <600>;
reset-post-delay-us = <20000>;
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
};
};
target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso
-35
View File
@@ -1,35 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&sw_p5>;
__overlay__ {
phy-mode = "2500base-x";
phy-handle = <&phy5>;
status = "okay";
};
};
fragment@1 {
target = <&mdio_bus>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
reset-delay-us = <600>;
reset-post-delay-us = <20000>;
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
};
};
target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso
-76
View File
@@ -1,76 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&chosen>;
rootdisk-spim-nand = <&ubi_rootdisk>;
};
fragment@1 {
target = <&spi0>;
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spi_nand: spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
compatible = "linux,ubi";
volumes {
ubi_rootdisk: ubi-volume-fit {
volname = "fit";
};
};
};
};
};
};
};
fragment@2 {
target = <&wifi>;
__overlay__ {
mediatek,mtd-eeprom = <&factory 0x0>;
status = "okay";
};
};
};
target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts
-189
View File
@@ -1,189 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7981b.dtsi"
/ {
model = "MediaTek MT7981 RFB";
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
aliases {
serial0 = &uart0;
};
chosen: chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/fit0 rootwait";
};
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
device_type = "memory";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "gmii";
phy-handle = <&int_gbe_phy>;
};
};
&mdio_bus {
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
&crypto {
status = "okay";
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
sw_p5: port@5 {
reg = <5>;
label = "lan5";
status = "disabled";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&xhci {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};
target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-50
View File
@@ -1,50 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
#include "mt7986a-rfb.dtsi"
/ {
compatible = "mediatek,mt7986a-rfb-snand";
};
&spi0 {
status = "okay";
spi_nand: spi_nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
};
};
};
};
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};
target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
-49
View File
@@ -1,49 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
#include "mt7986a-rfb.dtsi"
/ {
compatible = "mediatek,mt7986a-rfb-snor";
};
&spi0 {
status = "okay";
spi_nor: spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@00000 {
label = "BL2";
reg = <0x00000 0x0040000>;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x0010000>;
};
factory: partition@50000 {
label = "Factory";
reg = <0x50000 0x00B0000>;
};
partition@100000 {
label = "FIP";
reg = <0x100000 0x0080000>;
};
partition@180000 {
label = "firmware";
reg = <0x180000 0xE00000>;
};
};
};
};
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};
target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
-391
View File
@@ -1,391 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "mt7986a.dtsi"
/ {
model = "MediaTek MT7986a RFB";
compatible = "mediatek,mt7986a-rfb";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
device_type = "memory";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&mdio {
phy5: phy@5 {
compatible = "ethernet-phy-id67c9.de0a";
reg = <5>;
reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
reset-deassert-us = <20000>;
};
phy6: phy@6 {
compatible = "ethernet-phy-id67c9.de0a";
reg = <6>;
};
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
&crypto {
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
spic_pins_g2: spic-pins-29-to-32 {
mux {
function = "spi";
groups = "spi1_2";
};
};
spi_flash_pins: spi-flash-pins-33-to-38 {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-disable; /* bias-disable */
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-disable; /* bias-disable */
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2";
};
};
wf_2g_5g_pins: wf_2g_5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <MTK_DRIVE_4mA>;
};
};
wf_dbdc_pins: wf_dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <MTK_DRIVE_4mA>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins_g2>;
status = "okay";
proslic_spi: proslic_spi@0 {
compatible = "silabs,proslic_spi";
reg = <0>;
spi-max-frequency = <10000000>;
spi-cpha = <1>;
spi-cpol = <1>;
channel_count = <1>;
debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
};
};
&gmac1 {
phy-mode = "2500base-x";
phy-connection-type = "2500base-x";
phy-handle = <&phy6>;
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "lan6";
phy-mode = "2500base-x";
phy-handle = <&phy5>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};
target/linux/mediatek/files-6.12/drivers/mfd/airoha-an8855.c
-278
View File
@@ -1,278 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* MFD driver for Airoha AN8855 Switch
*/
#include <linux/mfd/airoha-an8855-mfd.h>
#include <linux/mfd/core.h>
#include <linux/mdio.h>
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/regmap.h>
static const struct mfd_cell an8855_mfd_devs[] = {
{
.name = "an8855-efuse",
.of_compatible = "airoha,an8855-efuse",
}, {
.name = "an8855-switch",
.of_compatible = "airoha,an8855-switch",
}, {
.name = "an8855-mdio",
.of_compatible = "airoha,an8855-mdio",
}
};
int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id,
u8 page) __must_hold(&priv->bus->mdio_lock)
{
struct mii_bus *bus = priv->bus;
int ret;
ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page);
if (ret < 0)
dev_err_ratelimited(&bus->dev,
"failed to set an8855 mii page\n");
/* Cache current page if next mii read/write is for switch */
priv->current_page = page;
return ret < 0 ? ret : 0;
}
EXPORT_SYMBOL_GPL(an8855_mii_set_page);
static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,
u32 *val) __must_hold(&bus->mdio_lock)
{
int lo, hi, ret;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
AN8855_PBUS_MODE_ADDR_FIXED);
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,
upper_16_bits(reg));
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,
lower_16_bits(reg));
if (ret < 0)
goto err;
hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);
if (hi < 0) {
ret = hi;
goto err;
}
lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);
if (lo < 0) {
ret = lo;
goto err;
}
*val = ((u16)hi << 16) | ((u16)lo & 0xffff);
return 0;
err:
dev_err_ratelimited(&bus->dev,
"failed to read an8855 register\n");
return ret;
}
static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
{
struct an8855_mfd_priv *priv = ctx;
struct mii_bus *bus = priv->bus;
u16 addr = priv->switch_addr;
int ret;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
if (ret < 0)
goto exit;
ret = an8855_mii_read32(bus, addr, reg, val);
exit:
mutex_unlock(&bus->mdio_lock);
return ret < 0 ? ret : 0;
}
static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,
u32 val) __must_hold(&bus->mdio_lock)
{
int ret;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
AN8855_PBUS_MODE_ADDR_FIXED);
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,
upper_16_bits(reg));
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,
lower_16_bits(reg));
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,
upper_16_bits(val));
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,
lower_16_bits(val));
if (ret < 0)
goto err;
return 0;
err:
dev_err_ratelimited(&bus->dev,
"failed to write an8855 register\n");
return ret;
}
static int
an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)
{
struct an8855_mfd_priv *priv = ctx;
struct mii_bus *bus = priv->bus;
u16 addr = priv->switch_addr;
int ret;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
if (ret < 0)
goto exit;
ret = an8855_mii_write32(bus, addr, reg, val);
exit:
mutex_unlock(&bus->mdio_lock);
return ret < 0 ? ret : 0;
}
static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,
uint32_t write_val)
{
struct an8855_mfd_priv *priv = ctx;
struct mii_bus *bus = priv->bus;
u16 addr = priv->switch_addr;
u32 val;
int ret;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
if (ret < 0)
goto exit;
ret = an8855_mii_read32(bus, addr, reg, &val);
if (ret < 0)
goto exit;
val &= ~mask;
val |= write_val;
ret = an8855_mii_write32(bus, addr, reg, val);
exit:
mutex_unlock(&bus->mdio_lock);
return ret < 0 ? ret : 0;
}
static const struct regmap_range an8855_readable_ranges[] = {
regmap_reg_range(0x10000000, 0x10000fff), /* SCU */
regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */
regmap_reg_range(0x10002000, 0x10002fff), /* MCU */
regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */
regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */
regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */
regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */
regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */
regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */
regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */
regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */
regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */
regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */
regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */
regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */
regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */
regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */
regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */
regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */
regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */
regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */
regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */
regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */
regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */
};
static const struct regmap_access_table an8855_readable_table = {
.yes_ranges = an8855_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),
};
static const struct regmap_config an8855_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0xbfffffff,
.reg_read = an8855_regmap_read,
.reg_write = an8855_regmap_write,
.reg_update_bits = an8855_regmap_update_bits,
.disable_locking = true,
.rd_table = &an8855_readable_table,
};
static int an8855_mfd_probe(struct mdio_device *mdiodev)
{
struct an8855_mfd_priv *priv;
struct regmap *regmap;
priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->bus = mdiodev->bus;
priv->dev = &mdiodev->dev;
priv->switch_addr = mdiodev->addr;
/* no DMA for mdiobus, mute warning for DMA mask not set */
priv->dev->dma_mask = &priv->dev->coherent_dma_mask;
regmap = devm_regmap_init(priv->dev, NULL, priv,
&an8855_regmap_config);
if (IS_ERR(regmap))
dev_err_probe(priv->dev, PTR_ERR(priv->dev),
"regmap initialization failed\n");
dev_set_drvdata(&mdiodev->dev, priv);
return devm_mfd_add_devices(priv->dev, PLATFORM_DEVID_AUTO, an8855_mfd_devs,
ARRAY_SIZE(an8855_mfd_devs), NULL, 0,
NULL);
}
static const struct of_device_id an8855_mfd_of_match[] = {
{ .compatible = "airoha,an8855-mfd" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, an8855_mfd_of_match);
static struct mdio_driver an8855_mfd_driver = {
.probe = an8855_mfd_probe,
.mdiodrv.driver = {
.name = "an8855",
.of_match_table = an8855_mfd_of_match,
},
};
mdio_module_driver(an8855_mfd_driver);
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_DESCRIPTION("Driver for Airoha AN8855 MFD");
MODULE_LICENSE("GPL");
target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.c
-2307
View File
File diff suppressed because it is too large Load Diff
target/linux/mediatek/files-6.12/drivers/net/dsa/an8855.h
-783
View File
@@ -1,783 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2023 Min Yao <min.yao@airoha.com>
* Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
*/
#ifndef __AN8855_H
#define __AN8855_H
#include <linux/bitfield.h>
#define AN8855_NUM_PORTS 6
#define AN8855_CPU_PORT 5
#define AN8855_NUM_FDB_RECORDS 2048
#define AN8855_GPHY_SMI_ADDR_DEFAULT 1
#define AN8855_PORT_VID_DEFAULT 0
#define MTK_TAG_LEN 4
#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN)
#define AN8855_L2_AGING_MS_CONSTANT 1024
#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0)
/* AN8855_SCU 0x10000000 */
#define AN8855_RG_GPIO_LED_MODE 0x10000054
#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4)))
#define AN8855_RG_INTB_MODE 0x10000080
#define AN8855_RG_RGMII_TXCK_C 0x100001d0
#define AN8855_PKG_SEL 0x10000094
#define AN8855_PAG_SEL_AN8855H 0x2
/* Register for hw trap status */
#define AN8855_HWTRAP 0x1000009c
#define AN8855_RG_GPIO_L_INV 0x10000010
#define AN8855_RG_GPIO_CTRL 0x1000a300
#define AN8855_RG_GPIO_DATA 0x1000a304
#define AN8855_RG_GPIO_OE 0x1000a314
#define AN8855_CREV 0x10005000
#define AN8855_ID 0x8855
/* Register for system reset */
#define AN8855_RST_CTRL 0x100050c0
#define AN8855_SYS_CTRL_SYS_RST BIT(31)
#define AN8855_INT_MASK 0x100050f0
#define AN8855_INT_SYS BIT(15)
#define AN8855_RG_CLK_CPU_ICG 0x10005034
#define AN8855_MCU_ENABLE BIT(3)
#define AN8855_RG_TIMER_CTL 0x1000a100
#define AN8855_WDOG_ENABLE BIT(25)
#define AN8855_RG_GDMP_RAM 0x10010000
/* Registers to mac forward control for unknown frames */
#define AN8855_MFC 0x10200010
#define AN8855_CPU_EN BIT(15)
#define AN8855_CPU_PORT_IDX GENMASK(12, 8)
#define AN8855_PAC 0x10200024
#define AN8855_TAG_PAE_MANG_FR BIT(30)
#define AN8855_TAG_PAE_BPDU_FR BIT(28)
#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25)
#define AN8855_TAG_PAE_LKY_VLAN BIT(24)
#define AN8855_TAG_PAE_PRI_HIGH BIT(23)
#define AN8855_TAG_PAE_MIR GENMASK(20, 19)
#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16)
#define AN8855_PAE_MANG_FR BIT(14)
#define AN8855_PAE_BPDU_FR BIT(12)
#define AN8855_PAE_EG_TAG GENMASK(11, 9)
#define AN8855_PAE_LKY_VLAN BIT(8)
#define AN8855_PAE_PRI_HIGH BIT(7)
#define AN8855_PAE_MIR GENMASK(4, 3)
#define AN8855_PAE_PORT_FW GENMASK(2, 0)
#define AN8855_RGAC1 0x10200028
#define AN8855_R02_MANG_FR BIT(30)
#define AN8855_R02_BPDU_FR BIT(28)
#define AN8855_R02_EG_TAG GENMASK(27, 25)
#define AN8855_R02_LKY_VLAN BIT(24)
#define AN8855_R02_PRI_HIGH BIT(23)
#define AN8855_R02_MIR GENMASK(20, 19)
#define AN8855_R02_PORT_FW GENMASK(18, 16)
#define AN8855_R01_MANG_FR BIT(14)
#define AN8855_R01_BPDU_FR BIT(12)
#define AN8855_R01_EG_TAG GENMASK(11, 9)
#define AN8855_R01_LKY_VLAN BIT(8)
#define AN8855_R01_PRI_HIGH BIT(7)
#define AN8855_R01_MIR GENMASK(4, 3)
#define AN8855_R01_PORT_FW GENMASK(2, 0)
#define AN8855_RGAC2 0x1020002c
#define AN8855_R0E_MANG_FR BIT(30)
#define AN8855_R0E_BPDU_FR BIT(28)
#define AN8855_R0E_EG_TAG GENMASK(27, 25)
#define AN8855_R0E_LKY_VLAN BIT(24)
#define AN8855_R0E_PRI_HIGH BIT(23)
#define AN8855_R0E_MIR GENMASK(20, 19)
#define AN8855_R0E_PORT_FW GENMASK(18, 16)
#define AN8855_R03_MANG_FR BIT(14)
#define AN8855_R03_BPDU_FR BIT(12)
#define AN8855_R03_EG_TAG GENMASK(11, 9)
#define AN8855_R03_LKY_VLAN BIT(8)
#define AN8855_R03_PRI_HIGH BIT(7)
#define AN8855_R03_MIR GENMASK(4, 3)
#define AN8855_R03_PORT_FW GENMASK(2, 0)
#define AN8855_AAC 0x102000a0
#define AN8855_MAC_AUTO_FLUSH BIT(28)
/* Control Address Table Age time.
* (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT
*/
#define AN8855_AGE_CNT GENMASK(20, 12)
/* Value in seconds. Value is always incremented of 1 */
#define AN8855_AGE_UNIT GENMASK(10, 0)
/* Registers for ARL Unknown Unicast Forward control */
#define AN8855_UNUF 0x102000b4
/* Registers for ARL Unknown Multicast Forward control */
#define AN8855_UNMF 0x102000b8
/* Registers for ARL Broadcast forward control */
#define AN8855_BCF 0x102000bc
/* Registers for port address age disable */
#define AN8855_AGDIS 0x102000c0
/* Registers for mirror port control */
#define AN8855_MIR 0x102000cc
#define AN8855_MIRROR_EN BIT(7)
#define AN8855_MIRROR_PORT GENMASK(4, 0)
/* Registers for BPDU and PAE frame control*/
#define AN8855_BPC 0x102000d0
#define AN8855_BPDU_MANG_FR BIT(14)
#define AN8855_BPDU_BPDU_FR BIT(12)
#define AN8855_BPDU_EG_TAG GENMASK(11, 9)
#define AN8855_BPDU_LKY_VLAN BIT(8)
#define AN8855_BPDU_PRI_HIGH BIT(7)
#define AN8855_BPDU_MIR GENMASK(4, 3)
#define AN8855_BPDU_PORT_FW GENMASK(2, 0)
/* Registers for IP Unknown Multicast Forward control */
#define AN8855_UNIPMF 0x102000dc
enum an8855_bpdu_port_fw {
AN8855_BPDU_FOLLOW_MFC = 0,
AN8855_BPDU_CPU_EXCLUDE = 4,
AN8855_BPDU_CPU_INCLUDE = 5,
AN8855_BPDU_CPU_ONLY = 6,
AN8855_BPDU_DROP = 7,
};
/* Register for address table control */
#define AN8855_ATC 0x10200300
#define AN8855_ATC_BUSY BIT(31)
#define AN8855_ATC_HASH GENMASK(24, 16)
#define AN8855_ATC_HIT GENMASK(15, 12)
#define AN8855_ATC_MAT_MASK GENMASK(11, 7)
#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x)
#define AN8855_ATC_SAT GENMASK(5, 4)
#define AN8855_ATC_CMD GENMASK(2, 0)
enum an8855_fdb_mat_cmds {
AND8855_FDB_MAT_ALL = 0,
AND8855_FDB_MAT_MAC, /* All MAC address */
AND8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */
AND8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */
AND8855_FDB_MAT_DIP, /* All DIP/GA address */
AND8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */
AND8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */
AND8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */
AND8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */
AND8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */
AND8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */
AND8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */
AND8855_FDB_MAT_MAC_PORT, /* All MAC address with port */
AND8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */
AND8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */
AND8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */
AND8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */
/* All MAC address with MAC type (dynamic or static) with CVID */
AND8855_FDB_MAT_MAC_TYPE_CVID,
/* All MAC address with MAC type (dynamic or static) with Filter ID */
AND8855_FDB_MAT_MAC_TYPE_FID,
/* All MAC address with MAC type (dynamic or static) with port */
AND8855_FDB_MAT_MAC_TYPE_PORT,
};
enum an8855_fdb_cmds {
AN8855_FDB_READ = 0,
AN8855_FDB_WRITE = 1,
AN8855_FDB_FLUSH = 2,
AN8855_FDB_START = 4,
AN8855_FDB_NEXT = 5,
};
/* Registers for address table access */
#define AN8855_ATA1 0x10200304
#define AN8855_ATA1_MAC0 GENMASK(31, 24)
#define AN8855_ATA1_MAC1 GENMASK(23, 16)
#define AN8855_ATA1_MAC2 GENMASK(15, 8)
#define AN8855_ATA1_MAC3 GENMASK(7, 0)
#define AN8855_ATA2 0x10200308
#define AN8855_ATA2_MAC4 GENMASK(31, 24)
#define AN8855_ATA2_MAC5 GENMASK(23, 16)
#define AN8855_ATA2_UNAUTH BIT(10)
#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */
#define AN8855_ATA2_AGE GENMASK(8, 0)
/* Register for address table write data */
#define AN8855_ATWD 0x10200324
#define AN8855_ATWD_FID GENMASK(31, 28)
#define AN8855_ATWD_VID GENMASK(27, 16)
#define AN8855_ATWD_IVL BIT(15)
#define AN8855_ATWD_EG_TAG GENMASK(14, 12)
#define AN8855_ATWD_SA_MIR GENMASK(9, 8)
#define AN8855_ATWD_SA_FWD GENMASK(7, 5)
#define AN8855_ATWD_UPRI GENMASK(4, 2)
#define AN8855_ATWD_LEAKY BIT(1)
#define AN8855_ATWD_VLD BIT(0) /* vid LOAD */
#define AN8855_ATWD2 0x10200328
#define AN8855_ATWD2_PORT GENMASK(7, 0)
/* Registers for table search read address */
#define AN8855_ATRDS 0x10200330
#define AN8855_ATRD_SEL GENMASK(1, 0)
#define AN8855_ATRD0 0x10200334
#define AN8855_ATRD0_FID GENMASK(28, 25)
#define AN8855_ATRD0_VID GENMASK(21, 10)
#define AN8855_ATRD0_IVL BIT(9)
#define AN8855_ATRD0_TYPE GENMASK(4, 3)
#define AN8855_ATRD0_ARP GENMASK(2, 1)
#define AN8855_ATRD0_LIVE BIT(0)
#define AN8855_ATRD1 0x10200338
#define AN8855_ATRD1_MAC4 GENMASK(31, 24)
#define AN8855_ATRD1_MAC5 GENMASK(23, 16)
#define AN8855_ATRD1_AGING GENMASK(11, 3)
#define AN8855_ATRD2 0x1020033c
#define AN8855_ATRD2_MAC0 GENMASK(31, 24)
#define AN8855_ATRD2_MAC1 GENMASK(23, 16)
#define AN8855_ATRD2_MAC2 GENMASK(15, 8)
#define AN8855_ATRD2_MAC3 GENMASK(7, 0)
#define AN8855_ATRD3 0x10200340
#define AN8855_ATRD3_PORTMASK GENMASK(7, 0)
enum an8855_fdb_type {
AN8855_MAC_TB_TY_MAC = 0,
AN8855_MAC_TB_TY_DIP = 1,
AN8855_MAC_TB_TY_DIP_SIP = 2,
};
/* Register for vlan table control */
#define AN8855_VTCR 0x10200600
#define AN8855_VTCR_BUSY BIT(31)
#define AN8855_VTCR_FUNC GENMASK(15, 12)
#define AN8855_VTCR_VID GENMASK(11, 0)
enum an8855_vlan_cmd {
/* Read/Write the specified VID entry from VAWD register based
* on VID.
*/
AN8855_VTCR_RD_VID = 0,
AN8855_VTCR_WR_VID = 1,
};
/* Register for setup vlan write data */
#define AN8855_VAWD0 0x10200604
/* VLAN Member Control */
#define AN8855_VA0_PORT GENMASK(31, 26)
/* Egress Tag Control */
#define AN8855_VA0_ETAG GENMASK(23, 12)
#define AN8855_VA0_ETAG_PORT GENMASK(13, 12)
#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2)
#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \
AN8855_VA0_ETAG_PORT_SHIFT(port))
#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \
AN8855_VA0_ETAG_PORT_SHIFT(port))
#define AN8855_VA0_EG_CON BIT(11)
#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */
#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */
#define AN8855_VA0_FID GENMASK(4, 1)
#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */
#define AN8855_VAWD1 0x10200608
#define AN8855_VA1_PORT_STAG BIT(1)
enum an8855_fid {
AN8855_FID_STANDALONE = 0,
AN8855_FID_BRIDGED = 1,
};
/* Same register field of VAWD0 */
#define AN8855_VARD0 0x10200618
enum an8855_vlan_egress_attr {
AN8855_VLAN_EGRESS_UNTAG = 0,
AN8855_VLAN_EGRESS_TAG = 2,
AN8855_VLAN_EGRESS_STACK = 3,
};
/* Register for port STP state control */
#define AN8855_SSP_P(x) (0x10208000 + ((x) * 0x200))
/* Up to 16 FID supported, each with the same mask */
#define AN8855_FID_PST GENMASK(1, 0)
#define AN8855_FID_PST_SHIFT(fid) (2 * (fid))
#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \
AN8855_FID_PST_SHIFT(fid))
#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \
AN8855_FID_PST_SHIFT(fid))
enum an8855_stp_state {
AN8855_STP_DISABLED = 0,
AN8855_STP_BLOCKING = 1,
AN8855_STP_LISTENING = AN8855_STP_BLOCKING,
AN8855_STP_LEARNING = 2,
AN8855_STP_FORWARDING = 3
};
/* Register for port control */
#define AN8855_PCR_P(x) (0x10208004 + ((x) * 0x200))
#define AN8855_EG_TAG GENMASK(29, 28)
#define AN8855_PORT_PRI GENMASK(26, 24)
#define AN8855_PORT_TX_MIR BIT(20)
#define AN8855_PORT_RX_MIR BIT(16)
#define AN8855_PORT_VLAN GENMASK(1, 0)
enum an8855_port_mode {
/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
AN8855_PORT_MATRIX_MODE = 0,
/* Fallback Mode: Forward received frames with ingress ports that do
* not belong to the VLAN member. Frames whose VID is not listed on
* the VLAN table are forwarded by the PCR_MATRIX members.
*/
AN8855_PORT_FALLBACK_MODE = 1,
/* Check Mode: Forward received frames whose ingress do not
* belong to the VLAN member. Discard frames if VID ismiddes on the
* VLAN table.
*/
AN8855_PORT_CHECK_MODE = 2,
/* Security Mode: Discard any frame due to ingress membership
* violation or VID missed on the VLAN table.
*/
AN8855_PORT_SECURITY_MODE = 3,
};
/* Register for port security control */
#define AN8855_PSC_P(x) (0x1020800c + ((x) * 0x200))
#define AN8855_SA_DIS BIT(4)
/* Register for port vlan control */
#define AN8855_PVC_P(x) (0x10208010 + ((x) * 0x200))
#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11)
#define AN8855_PVC_EG_TAG GENMASK(10, 8)
#define AN8855_VLAN_ATTR GENMASK(7, 6)
#define AN8855_PORT_SPEC_TAG BIT(5)
#define AN8855_ACC_FRM GENMASK(1, 0)
enum an8855_vlan_port_eg_tag {
AN8855_VLAN_EG_DISABLED = 0,
AN8855_VLAN_EG_CONSISTENT = 1,
AN8855_VLAN_EG_UNTAGGED = 4,
AN8855_VLAN_EG_SWAP = 5,
AN8855_VLAN_EG_TAGGED = 6,
AN8855_VLAN_EG_STACK = 7,
};
enum an8855_vlan_port_attr {
AN8855_VLAN_USER = 0,
AN8855_VLAN_STACK = 1,
AN8855_VLAN_TRANSPARENT = 3,
};
enum an8855_vlan_port_acc_frm {
AN8855_VLAN_ACC_ALL = 0,
AN8855_VLAN_ACC_TAGGED = 1,
AN8855_VLAN_ACC_UNTAGGED = 2,
};
#define AN8855_PPBV1_P(x) (0x10208014 + ((x) * 0x200))
#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0)
#define AN8855_PORTMATRIX_P(x) (0x10208044 + ((x) * 0x200))
#define AN8855_PORTMATRIX GENMASK(5, 0)
/* Port matrix without the CPU port that should never be removed */
#define AN8855_USER_PORTMATRIX GENMASK(4, 0)
/* Register for port PVID */
#define AN8855_PVID_P(x) (0x10208048 + ((x) * 0x200))
#define AN8855_G0_PORT_VID GENMASK(11, 0)
/* Register for port MAC control register */
#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200))
#define AN8855_PMCR_FORCE_MODE BIT(31)
#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28)
#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4)
#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3)
#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2)
#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
#define AN8855_PMCR_FORCE_FDX BIT(25)
#define AN8855_PMCR_FORCE_LNK BIT(24)
#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20)
#define AN8855_PMCR_EXT_PHY BIT(19)
#define AN8855_PMCR_MAC_MODE BIT(18)
#define AN8855_PMCR_TX_EN BIT(16)
#define AN8855_PMCR_RX_EN BIT(15)
#define AN8855_PMCR_BACKOFF_EN BIT(12)
#define AN8855_PMCR_BACKPR_EN BIT(11)
#define AN8855_PMCR_FORCE_EEE5G BIT(9)
#define AN8855_PMCR_FORCE_EEE2P5G BIT(8)
#define AN8855_PMCR_FORCE_EEE1G BIT(7)
#define AN8855_PMCR_FORCE_EEE100 BIT(6)
#define AN8855_PMCR_TX_FC_EN BIT(5)
#define AN8855_PMCR_RX_FC_EN BIT(4)
#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200)
#define AN8855_PMSR_SPEED GENMASK(30, 28)
#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4)
#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3)
#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2)
#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1)
#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0)
#define AN8855_PMSR_DPX BIT(25)
#define AN8855_PMSR_LNK BIT(24)
#define AN8855_PMSR_EEE1G BIT(7)
#define AN8855_PMSR_EEE100M BIT(6)
#define AN8855_PMSR_RX_FC BIT(5)
#define AN8855_PMSR_TX_FC BIT(4)
#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200)
#define AN8855_LPI_MODE_EN BIT(31)
#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16)
#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8)
#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0)
#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200)
#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0)
#define AN8855_GMACCR 0x10213e00
#define AN8855_MAX_RX_JUMBO GENMASK(7, 4)
/* 2K for 0x0, 0x1, 0x2 */
#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0)
#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3)
#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4)
#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5)
#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6)
#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7)
#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8)
#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)
#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0)
#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0)
#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1)
#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2)
#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3)
#define AN8855_CKGCR 0x10213e1c
#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14)
#define AN8855_CKG_LNKDN_PORT_STOP BIT(1)
#define AN8855_CKG_LNKDN_GLB_STOP BIT(0)
/* Register for MIB */
#define AN8855_PORT_MIB_COUNTER(x) (0x10214000 + (x) * 0x200)
/* Each define is an offset of AN8855_PORT_MIB_COUNTER */
#define AN8855_PORT_MIB_TX_DROP 0x00
#define AN8855_PORT_MIB_TX_CRC_ERR 0x04
#define AN8855_PORT_MIB_TX_UNICAST 0x08
#define AN8855_PORT_MIB_TX_MULTICAST 0x0c
#define AN8855_PORT_MIB_TX_BROADCAST 0x10
#define AN8855_PORT_MIB_TX_COLLISION 0x14
#define AN8855_PORT_MIB_TX_SINGLE_COLLISION 0x18
#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c
#define AN8855_PORT_MIB_TX_DEFERRED 0x20
#define AN8855_PORT_MIB_TX_LATE_COLLISION 0x24
#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28
#define AN8855_PORT_MIB_TX_PAUSE 0x2c
#define AN8855_PORT_MIB_TX_PKT_SZ_64 0x30
#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34
#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38
#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3
#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40
#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 0x44
#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX 0x48
#define AN8855_PORT_MIB_TX_BYTES 0x4c /* 64 bytes */
#define AN8855_PORT_MIB_TX_OVERSIZE_DROP 0x54
#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES 0x58 /* 64 bytes */
#define AN8855_PORT_MIB_RX_DROP 0x80
#define AN8855_PORT_MIB_RX_FILTERING 0x84
#define AN8855_PORT_MIB_RX_UNICAST 0x88
#define AN8855_PORT_MIB_RX_MULTICAST 0x8c
#define AN8855_PORT_MIB_RX_BROADCAST 0x90
#define AN8855_PORT_MIB_RX_ALIGN_ERR 0x94
#define AN8855_PORT_MIB_RX_CRC_ERR 0x98
#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR 0x9c
#define AN8855_PORT_MIB_RX_FRAG_ERR 0xa0
#define AN8855_PORT_MIB_RX_OVER_SZ_ERR 0xa4
#define AN8855_PORT_MIB_RX_JABBER_ERR 0xa8
#define AN8855_PORT_MIB_RX_PAUSE 0xac
#define AN8855_PORT_MIB_RX_PKT_SZ_64 0xb0
#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 0xb4
#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 0xb8
#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 0xbc
#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xc0
#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 0xc4
#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX 0xc8
#define AN8855_PORT_MIB_RX_BYTES 0xcc /* 64 bytes */
#define AN8855_PORT_MIB_RX_CTRL_DROP 0xd4
#define AN8855_PORT_MIB_RX_INGRESS_DROP 0xd8
#define AN8855_PORT_MIB_RX_ARL_DROP 0xdc
#define AN8855_PORT_MIB_FLOW_CONTROL_DROP 0xe0
#define AN8855_PORT_MIB_WRED_DROP 0xe4
#define AN8855_PORT_MIB_MIRROR_DROP 0xe8
#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES 0xec /* 64 bytes */
#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP 0xf4
#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP 0xf8
#define AN8855_PORT_MIB_PORT_CONTROL_DROP 0xfc
#define AN8855_MIB_CCR 0x10213e30
#define AN8855_CCR_MIB_ENABLE BIT(31)
#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7)
#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6)
#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5)
#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4)
#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3)
#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2)
#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1)
#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0)
#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \
AN8855_CCR_RX_OCT_CNT_GOOD | \
AN8855_CCR_RX_OCT_CNT_BAD | \
AN8855_CCR_TX_OCT_CNT_GOOD | \
AN8855_CCR_TX_OCT_CNT_BAD | \
AN8855_CCR_RX_OCT_CNT_BAD_2 | \
AN8855_CCR_TX_OCT_CNT_BAD_2)
#define AN8855_MIB_CLR 0x10213e34
#define AN8855_MIB_PORT6_CLR BIT(6)
#define AN8855_MIB_PORT5_CLR BIT(5)
#define AN8855_MIB_PORT4_CLR BIT(4)
#define AN8855_MIB_PORT3_CLR BIT(3)
#define AN8855_MIB_PORT2_CLR BIT(2)
#define AN8855_MIB_PORT1_CLR BIT(1)
#define AN8855_MIB_PORT0_CLR BIT(0)
/* HSGMII/SGMII Configuration register */
/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */
#define AN8855_SGMII_REG_AN0 0x10220000
/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */
/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */
#define AN8855_SGMII_REG_AN_13 0x10220034
#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8)
#define AN8855_SGMII_IF_MODE GENMASK(5, 0)
#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060
#define AN8855_RG_FORCE_AN_DONE BIT(0)
/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */
#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00
#define AN8855_RG_TBI_10B_MODE BIT(30)
#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24
#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0)
/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */
#define AN8855_SGMII_STS_CTRL_0 0x10224018
#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4)
#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3)
#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2)
#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1)
#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0)
#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2)
#define AN8855_MSG_RX_CTRL_0 0x10224100
#define AN8855_MSG_RX_LIK_STS_0 0x10224514
#define AN8855_RG_DPX_STS_P3 BIT(24)
#define AN8855_RG_DPX_STS_P2 BIT(16)
#define AN8855_RG_EEE1G_STS_P1 BIT(12)
#define AN8855_RG_DPX_STS_P1 BIT(8)
#define AN8855_RG_TXFC_STS_P0 BIT(2)
#define AN8855_RG_RXFC_STS_P0 BIT(1)
#define AN8855_RG_DPX_STS_P0 BIT(0)
#define AN8855_MSG_RX_LIK_STS_2 0x1022451c
#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11)
#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10)
#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9)
#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7)
#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6)
#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5)
#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3)
#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2)
#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1)
#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0)
#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520
#define AN8855_RG_FORCE_TXC_SEL BIT(4)
/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */
#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8
/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */
#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000
#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27)
#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26)
#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4)
#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0)
#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100
#define AN8855_RG_P0_DIS_MII_MODE BIT(31)
#define AN8855_RG_P0_MII_MODE BIT(28)
#define AN8855_RG_P0_MII_RA_RX_EN BIT(3)
#define AN8855_RG_P0_MII_RA_TX_EN BIT(2)
#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1)
#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0)
#define AN8855_MII_RA_AN_ENABLE 0x10226300
#define AN8855_RG_P0_RA_AN_EN BIT(0)
/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */
#define AN8855_QP_CK_RST_CTRL_4 0x1022a310
#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324
#define AN8855_RG_SGMII_MODE GENMASK(5, 4)
#define AN8855_RG_SGMII_AN_EN BIT(0)
#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330
#define AN8855_RG_TPHY_SPEED GENMASK(3, 2)
/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */
#define AN8855_USGMII_CTRL_0 0x1022c000
/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */
#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100
#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12)
#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124
#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0)
#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208
#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16)
#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230
#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0)
#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c
#define AN8855_RG_LCPLL_NCPO_CHG BIT(24)
#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248
#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)
#define AN8855_INTF_CTRL_8 0x1022e320
#define AN8855_INTF_CTRL_9 0x1022e324
#define AN8855_INTF_CTRL_10 0x1022e328
#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29)
#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24)
#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21)
#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16)
#define AN8855_INTF_CTRL_11 0x1022e32c
#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6)
#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0)
#define AN8855_PLL_CTRL_0 0x1022e400
#define AN8855_RG_PHYA_AUTO_INIT BIT(0)
#define AN8855_PLL_CTRL_2 0x1022e408
#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30)
#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29)
#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28)
#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27)
#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26)
#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24)
#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22)
#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20)
#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16)
#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14)
#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12)
#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8)
#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6)
#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2)
#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0)
#define AN8855_PLL_CTRL_3 0x1022e40c
#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16)
#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0)
#define AN8855_PLL_CTRL_4 0x1022e410
#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2)
#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0)
#define AN8855_PLL_CK_CTRL_0 0x1022e414
#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9)
#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8)
#define AN8855_RX_DLY_0 0x1022e614
#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8)
#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0)
#define AN8855_RX_CTRL_2 0x1022e630
#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16)
#define AN8855_RX_CTRL_5 0x1022e63c
#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10)
#define AN8855_RX_CTRL_6 0x1022e640
#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0)
#define AN8855_RX_CTRL_7 0x1022e644
#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0)
#define AN8855_RX_CTRL_8 0x1022e648
#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16)
#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0)
#define AN8855_RX_CTRL_26 0x1022e690
#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26)
#define AN8855_RG_LINK_NE_EN BIT(24)
#define AN8855_RG_LINK_ERRO_EN BIT(23)
#define AN8855_RX_CTRL_42 0x1022e6d0
#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0)
/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */
#define AN8855_RG_QP_RX_DAC_EN 0x1022f000
#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16)
#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004
#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11)
#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008
#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24)
#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20)
#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c
#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4)
#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014
#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29)
#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25)
#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018
#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24)
#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8)
#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c
#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30)
#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6)
#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0)
#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020
#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16)
#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13)
#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6)
#define AN8855_RG_QP_TX_MODE 0x1022f028
#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16)
#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0)
#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c
#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040
#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4)
#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3)
/* AN8855_ETHER_SYS_BASE 0x1028c800 */
#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848
#define MIB_DESC(_s, _o, _n) \
{ \
.size = (_s), \
.offset = (_o), \
.name = (_n), \
}
struct an8855_mib_desc {
unsigned int size;
unsigned int offset;
const char *name;
};
struct an8855_fdb {
u16 vid;
u8 port_mask;
u16 aging;
u8 mac[6];
bool noarp;
u8 live;
u8 type;
u8 fid;
u8 ivl;
};
struct an8855_priv {
struct device *dev;
struct dsa_switch *ds;
struct regmap *regmap;
struct gpio_desc *reset_gpio;
/* Protect ATU or VLAN table access */
struct mutex reg_mutex;
struct phylink_pcs pcs;
u8 mirror_rx;
u8 mirror_tx;
u8 port_isolated_map;
bool phy_require_calib;
};
#endif /* __AN8855_H */
target/linux/mediatek/files-6.12/drivers/net/mdio/mdio-an8855.c
-113
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@@ -1,113 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* MDIO passthrough driver for Airoha AN8855 Switch
*/
#include <linux/mfd/airoha-an8855-mfd.h>
#include <linux/module.h>
#include <linux/of_mdio.h>
#include <linux/platform_device.h>
static int an855_phy_restore_page(struct an8855_mfd_priv *priv,
int phy) __must_hold(&priv->bus->mdio_lock)
{
/* Check PHY page only for addr shared with switch */
if (phy != priv->switch_addr)
return 0;
/* Don't restore page if it's not set to switch page */
if (priv->current_page != FIELD_GET(AN8855_PHY_PAGE,
AN8855_PHY_PAGE_EXTENDED_4))
return 0;
/* Restore page to 0, PHY might change page right after but that
* will be ignored as it won't be a switch page.
*/
return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
}
static int an8855_phy_read(struct mii_bus *bus, int phy, int regnum)
{
struct an8855_mfd_priv *priv = bus->priv;
struct mii_bus *real_bus = priv->bus;
int ret;
mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an855_phy_restore_page(priv, phy);
if (ret)
goto exit;
ret = __mdiobus_read(real_bus, phy, regnum);
exit:
mutex_unlock(&real_bus->mdio_lock);
return ret;
}
static int an8855_phy_write(struct mii_bus *bus, int phy, int regnum, u16 val)
{
struct an8855_mfd_priv *priv = bus->priv;
struct mii_bus *real_bus = priv->bus;
int ret;
mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an855_phy_restore_page(priv, phy);
if (ret)
goto exit;
ret = __mdiobus_write(real_bus, phy, regnum, val);
exit:
mutex_unlock(&real_bus->mdio_lock);
return ret;
}
static int an8855_mdio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct an8855_mfd_priv *priv;
struct mii_bus *bus;
int ret;
/* Get priv of MFD */
priv = dev_get_drvdata(dev->parent);
bus = devm_mdiobus_alloc(dev);
if (!bus)
return -ENOMEM;
bus->priv = priv;
bus->name = KBUILD_MODNAME "-mii";
snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d",
priv->switch_addr);
bus->parent = dev;
bus->read = an8855_phy_read;
bus->write = an8855_phy_write;
ret = devm_of_mdiobus_register(dev, bus, dev->of_node);
if (ret)
return dev_err_probe(dev, ret, "failed to register MDIO bus\n");
return ret;
}
static const struct of_device_id an8855_mdio_of_match[] = {
{ .compatible = "airoha,an8855-mdio", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, an8855_mdio_of_match);
static struct platform_driver an8855_mdio_driver = {
.probe = an8855_mdio_probe,
.driver = {
.name = "an8855-mdio",
.of_match_table = an8855_mdio_of_match,
},
};
module_platform_driver(an8855_mdio_driver);
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_DESCRIPTION("Driver for AN8855 MDIO passthrough");
MODULE_LICENSE("GPL");
target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c
-267
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@@ -1,267 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
*/
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/phy.h>
#define AN8855_PHY_SELECT_PAGE 0x1f
#define AN8855_PHY_PAGE GENMASK(2, 0)
#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
/* MII Registers Page 1 */
#define AN8855_PHY_EXT_REG_14 0x14
#define AN8855_PHY_EN_DOWN_SHIFT BIT(4)
/* R50 Calibration regs in MDIO_MMD_VEND1 */
#define AN8855_PHY_R500HM_RSEL_TX_AB 0x174
#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15)
#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8)
#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7)
#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0)
#define AN8855_PHY_R500HM_RSEL_TX_CD 0x175
#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15)
#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8)
#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7)
#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0)
#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24)
/* PHY TX PAIR DELAY SELECT Register */
#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013
#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE GENMASK(14, 12)
#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_B_GBE GENMASK(10, 8)
#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE GENMASK(6, 4)
#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_D_GBE GENMASK(2, 0)
/* PHY ADC Register */
#define AN8855_PHY_RXADC_CTRL 0x0d8
#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A BIT(12)
#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_B BIT(8)
#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C BIT(4)
#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_D BIT(0)
#define AN8855_PHY_RXADC_REV_0 0x0d9
#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8)
#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0)
#define AN8855_PHY_RXADC_REV_1 0x0da
#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8)
#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0)
#define AN8855_PHY_ID 0xc0ff0410
#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0)
struct air_an8855_priv {
u8 calibration_data[4];
};
static const u8 dsa_r50ohm_table[] = {
127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
127, 127, 127, 127, 127, 127, 127, 126, 122, 117,
112, 109, 104, 101, 97, 94, 90, 88, 84, 80,
78, 74, 72, 68, 66, 64, 61, 58, 56, 53,
51, 48, 47, 44, 42, 40, 38, 36, 34, 32,
31, 28, 27, 24, 24, 22, 20, 18, 16, 16,
14, 12, 11, 9
};
static int en8855_get_r50ohm_val(struct device *dev, const char *calib_name,
u8 *dest)
{
u32 shift_sel, val;
int ret;
int i;
ret = nvmem_cell_read_u32(dev, calib_name, &val);
if (ret)
return ret;
shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val);
for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++)
if (dsa_r50ohm_table[i] == shift_sel)
break;
if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table))
*dest = dsa_r50ohm_table[25];
else
*dest = dsa_r50ohm_table[i - 8];
return 0;
}
static int an8855_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
struct device_node *node = dev->of_node;
struct air_an8855_priv *priv;
/* If we don't have a node, skip calib */
if (!node)
return 0;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
phydev->priv = priv;
return 0;
}
static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
{
int val;
val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
if (val < 0)
return val;
*data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
DOWNSHIFT_DEV_DISABLE;
return 0;
}
static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
{
u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
ds);
}
static int an8855_config_init(struct phy_device *phydev)
{
struct air_an8855_priv *priv = phydev->priv;
struct device *dev = &phydev->mdio.dev;
int ret;
/* Enable HW auto downshift */
ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
if (ret)
return ret;
/* Apply calibration values, if needed.
* AN8855_PHY_FLAGS_EN_CALIBRATION signal this.
*/
if (priv && phydev->dev_flags & AN8855_PHY_FLAGS_EN_CALIBRATION) {
u8 *calibration_data = priv->calibration_data;
ret = en8855_get_r50ohm_val(dev, "tx_a", &calibration_data[0]);
if (ret)
return ret;
ret = en8855_get_r50ohm_val(dev, "tx_b", &calibration_data[1]);
if (ret)
return ret;
ret = en8855_get_r50ohm_val(dev, "tx_c", &calibration_data[2]);
if (ret)
return ret;
ret = en8855_get_r50ohm_val(dev, "tx_d", &calibration_data[3]);
if (ret)
return ret;
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_AB,
AN8855_PHY_R50OHM_RSEL_TX_A | AN8855_PHY_R50OHM_RSEL_TX_B,
FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A, calibration_data[0]) |
FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B, calibration_data[1]));
if (ret)
return ret;
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_CD,
AN8855_PHY_R50OHM_RSEL_TX_C | AN8855_PHY_R50OHM_RSEL_TX_D,
FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C, calibration_data[2]) |
FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D, calibration_data[3]));
if (ret)
return ret;
}
/* Apply values to reduce signal noise */
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,
FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE, 0x4) |
FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE, 0x4));
if (ret)
return ret;
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL,
AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A |
AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C);
if (ret)
return ret;
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0,
FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1));
if (ret)
return ret;
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1,
FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1));
if (ret)
return ret;
return 0;
}
static int an8855_get_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return an8855_get_downshift(phydev, data);
default:
return -EOPNOTSUPP;
}
}
static int an8855_set_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, const void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return an8855_set_downshift(phydev, *(const u8 *)data);
default:
return -EOPNOTSUPP;
}
}
static int an8855_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, AN8855_PHY_SELECT_PAGE);
}
static int an8855_write_page(struct phy_device *phydev, int page)
{
return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page);
}
static struct phy_driver an8855_driver[] = {
{
PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
.name = "Airoha AN8855 internal PHY",
/* PHY_GBIT_FEATURES */
.flags = PHY_IS_INTERNAL,
.probe = an8855_probe,
.config_init = an8855_config_init,
.soft_reset = genphy_soft_reset,
.get_tunable = an8855_get_tunable,
.set_tunable = an8855_set_tunable,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_page = an8855_read_page,
.write_page = an8855_write_page,
}, };
module_phy_driver(an8855_driver);
static const struct mdio_device_id __maybe_unused an8855_tbl[] = {
{ PHY_ID_MATCH_EXACT(AN8855_PHY_ID) },
{ }
};
MODULE_DEVICE_TABLE(mdio, an8855_tbl);
MODULE_DESCRIPTION("Airoha AN8855 PHY driver");
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_LICENSE("GPL");
target/linux/mediatek/files-6.12/drivers/nvmem/an8855-efuse.c
-63
View File
@@ -1,63 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Airoha AN8855 Switch EFUSE Driver
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define AN8855_EFUSE_CELL 50
#define AN8855_EFUSE_DATA0 0x1000a500
#define AN8855_EFUSE_R50O GENMASK(30, 24)
static int an8855_efuse_read(void *context, unsigned int offset,
void *val, size_t bytes)
{
struct regmap *regmap = context;
return regmap_bulk_read(regmap, AN8855_EFUSE_DATA0 + offset,
val, bytes / sizeof(u32));
}
static int an8855_efuse_probe(struct platform_device *pdev)
{
struct nvmem_config an8855_nvmem_config = {
.name = "an8855-efuse",
.size = AN8855_EFUSE_CELL * sizeof(u32),
.stride = sizeof(u32),
.word_size = sizeof(u32),
.reg_read = an8855_efuse_read,
};
struct device *dev = &pdev->dev;
struct nvmem_device *nvmem;
/* Assign NVMEM priv to MFD regmap */
an8855_nvmem_config.priv = dev_get_regmap(dev->parent, NULL);
an8855_nvmem_config.dev = dev;
nvmem = devm_nvmem_register(dev, &an8855_nvmem_config);
return PTR_ERR_OR_ZERO(nvmem);
}
static const struct of_device_id an8855_efuse_of_match[] = {
{ .compatible = "airoha,an8855-efuse", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, an8855_efuse_of_match);
static struct platform_driver an8855_efuse_driver = {
.probe = an8855_efuse_probe,
.driver = {
.name = "an8855-efuse",
.of_match_table = an8855_efuse_of_match,
},
};
module_platform_driver(an8855_efuse_driver);
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_DESCRIPTION("Driver for AN8855 Switch EFUSE");
MODULE_LICENSE("GPL");
target/linux/mediatek/files-6.12/include/linux/mfd/airoha-an8855-mfd.h
-41
View File
@@ -1,41 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* MFD driver for Airoha AN8855 Switch
*/
#ifndef _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H
#define _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H
#include <linux/bitfield.h>
/* MII Registers */
#define AN8855_PHY_SELECT_PAGE 0x1f
#define AN8855_PHY_PAGE GENMASK(2, 0)
#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
/* MII Registers Page 4 */
#define AN8855_PBUS_MODE 0x10
#define AN8855_PBUS_MODE_ADDR_FIXED 0x0
#define AN8855_PBUS_MODE_ADDR_INCR BIT(15)
#define AN8855_PBUS_WR_ADDR_HIGH 0x11
#define AN8855_PBUS_WR_ADDR_LOW 0x12
#define AN8855_PBUS_WR_DATA_HIGH 0x13
#define AN8855_PBUS_WR_DATA_LOW 0x14
#define AN8855_PBUS_RD_ADDR_HIGH 0x15
#define AN8855_PBUS_RD_ADDR_LOW 0x16
#define AN8855_PBUS_RD_DATA_HIGH 0x17
#define AN8855_PBUS_RD_DATA_LOW 0x18
struct an8855_mfd_priv {
struct device *dev;
struct mii_bus *bus;
unsigned int switch_addr;
u16 current_page;
};
int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id,
u8 page);
#endif
target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
+1
View File
@@ -350,6 +350,7 @@ zbtlink,zbt-z8103ax|\
zbtlink,zbt-z8103ax-c)
ucidef_set_led_netdev "wan" "wan" "green:wan" "eth1" "link tx rx"
;;
zbtlink,zbt-z8106ax-s|\
zbtlink,zbt-z8106ax-t)
ucidef_set_led_netdev "wan" "wan" "amber:wan" "eth1" "link tx rx"
ucidef_set_led_netdev "mobile" "mobile" "green:mobile" "wwan" "link tx rx"
target/linux/mediatek/filogic/base-files/etc/board.d/02_network
+2 -1
View File
@@ -82,7 +82,8 @@ mediatek_setup_interfaces()
unielec,u7981-01*|\
wavlink,wl-wn536ax6-a|\
zbtlink,zbt-z8102ax|\
zbtlink,zbt-z8102ax-v2)
zbtlink,zbt-z8102ax-v2|\
zbtlink,zbt-z8106ax-s)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "eth1"
;;
zbtlink,zbt-z8106ax-t)
target/linux/mediatek/filogic/base-files/etc/board.d/03_gpio_switches
+1
View File
@@ -21,6 +21,7 @@ zbtlink,zbt-z8102ax-v2)
ucidef_add_gpio_switch "sim1" "SIM 1" "sim1" "1"
ucidef_add_gpio_switch "sim2" "SIM 2" "sim2" "1"
;;
zbtlink,zbt-z8106ax-s|\
zbtlink,zbt-z8106ax-t)
ucidef_add_gpio_switch "4g" "Power modem" "4g" "1"
ucidef_add_gpio_switch "sim" "SIM" "sim" "1"
target/linux/mediatek/filogic/config-6.12
-534
View File
@@ -1,534 +0,0 @@
CONFIG_64BIT=y
# CONFIG_AHCI_MTK is not set
CONFIG_AIROHA_EN8801SC_PHY=y
CONFIG_AIR_AN8855_PHY=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PKEY_BITS=3
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANTS_EXECMEM_LATE=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PLATFORM_DEVICES=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_52 is not set
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=y
CONFIG_ARM_MEDIATEK_CPUFREQ=y
CONFIG_ARM_PMU=y
CONFIG_ARM_PMUV3=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ATA=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_NOTIFIERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_BUFFER_HEAD=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_OVERRIDE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
# CONFIG_COMMON_CLK_MT2712 is not set
# CONFIG_COMMON_CLK_MT6779 is not set
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT6797 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
CONFIG_COMMON_CLK_MT7981=y
CONFIG_COMMON_CLK_MT7981_ETHSYS=y
CONFIG_COMMON_CLK_MT7986=y
CONFIG_COMMON_CLK_MT7986_ETHSYS=y
CONFIG_COMMON_CLK_MT7987=y
CONFIG_COMMON_CLK_MT7988=y
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8183 is not set
# CONFIG_COMMON_CLK_MT8186 is not set
# CONFIG_COMMON_CLK_MT8195 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
# CONFIG_COMPAT_32BIT_TIME is not set
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRC16=y
CONFIG_CRC_CCITT=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_MISC=y
CONFIG_DEVFREQ_GOV_PASSIVE=y
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DMADEVICES=y
CONFIG_DMATEST=y
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_ENGINE_RAID=y
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OF=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUNCTION_ALIGNMENT=4
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_GRO_CELLS=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
# CONFIG_IDPF is not set
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MSI_LIB=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JUMP_LABEL=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_SMARTRG_LED=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LRU_GEN_WALKS_MMU=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAXLINEAR_GPHY=y
CONFIG_MDIO_AN8855=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEDIATEK_2P5GE_PHY=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MEDIATEK_GE_SOC_PHY=y
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
CONFIG_MFD_AIROHA_AN8855=y
CONFIG_MFD_CORE=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_MTK=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_MEDIATEK=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MTK=y
CONFIG_MTD_NAND_MTK_BMT=y
CONFIG_MTD_PARSER_TRX=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_MSTC_BOOT=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_NVMEM=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_VIRT_CONCAT=y
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_CPUX_TIMER=y
# CONFIG_MTK_CQDMA is not set
CONFIG_MTK_HSDMA=y
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_LVTS_THERMAL=y
CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
CONFIG_MTK_NET_PHYLIB=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_REGULATOR_COUPLER=y
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
# CONFIG_MTK_SOCINFO is not set
CONFIG_MTK_SOC_THERMAL=y
# CONFIG_MTK_SVS is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_NET_AIROHA is not set
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_AN8855=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
CONFIG_NET_DSA_MT7530_MMIO=y
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_AN8855_EFUSE=y
CONFIG_NVMEM_BLOCK=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_LAYOUT_ADTRAN=y
CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y
CONFIG_NVMEM_MTK_EFUSE=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
CONFIG_PCIEASPM_PERFORMANCE=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIE_MEDIATEK is not set
CONFIG_PCIE_MEDIATEK_GEN3=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PCS_MTK_USXGMII=y
CONFIG_PERF_EVENTS=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHY_MTK_DP is not set
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
CONFIG_PHY_MTK_XFI_TPHY=y
CONFIG_PHY_MTK_XSPHY=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_MT2712 is not set
# CONFIG_PINCTRL_MT6765 is not set
# CONFIG_PINCTRL_MT6795 is not set
# CONFIG_PINCTRL_MT6797 is not set
# CONFIG_PINCTRL_MT7622 is not set
CONFIG_PINCTRL_MT7981=y
CONFIG_PINCTRL_MT7986=y
CONFIG_PINCTRL_MT7987=y
CONFIG_PINCTRL_MT7988=y
# CONFIG_PINCTRL_MT8173 is not set
# CONFIG_PINCTRL_MT8183 is not set
# CONFIG_PINCTRL_MT8186 is not set
# CONFIG_PINCTRL_MT8188 is not set
# CONFIG_PINCTRL_MT8516 is not set
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_OPP=y
CONFIG_POLYNOMIAL=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_SUPPLY=y
CONFIG_PRINTK_TIME=y
CONFIG_PSTORE=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_RAM=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
# CONFIG_RAVE_SP_CORE is not set
CONFIG_REALTEK_PHY=y
CONFIG_REALTEK_PHY_HWMON=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MT6380=y
CONFIG_REGULATOR_RT5190A=y
CONFIG_RELOCATABLE=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_TI_SYSCON=y
CONFIG_RFS_ACCEL=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MT7622=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTL8261N_PHY=y
# CONFIG_RTL8367S_GSW is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_MC=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
# CONFIG_SPI_MTK_NOR is not set
CONFIG_SPI_MTK_SNFI=y
CONFIG_SPLIT_PMD_PTLOCKS=y
CONFIG_SPLIT_PTE_PTLOCKS=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
# CONFIG_TEST_FPU is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UIMAGE_FIT_BLK=y
# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
CONFIG_USB_SUPPORT=y
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_VDSO_GETRANDOM=y
CONFIG_VMAP_STACK=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_SYSFS=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
target/linux/mediatek/image/filogic.mk
+21 -1
View File
@@ -3658,6 +3658,25 @@ define Device/zbtlink_zbt-z8103ax-c
endef
TARGET_DEVICES += zbtlink_zbt-z8103ax-c
define Device/zbtlink_zbt-z8106ax-s
DEVICE_VENDOR := Zbtlink
DEVICE_MODEL := ZBT-Z8106AX-S
SUPPORTED_DEVICES += zbtlink,z8106ax-2sim
DEVICE_DTS := mt7981b-zbtlink-zbt-z8106ax-s
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware \
kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option automount
KERNEL_IN_UBI := 1
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 65536k
IMAGES += factory.bin
IMAGE/factory.bin := append-ubi | check-size $$(IMAGE_SIZE)
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += zbtlink_zbt-z8106ax-s
define Device/zbtlink_zbt-z8106ax-t
DEVICE_VENDOR := Zbtlink
DEVICE_MODEL := ZBT-Z8106AX-T
@@ -3666,7 +3685,8 @@ define Device/zbtlink_zbt-z8106ax-t
SUPPORTED_DEVICES += zbtlink,z8106ax-2sim
DEVICE_DTS := mt7981b-zbtlink-zbt-z8106ax-t
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option
DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware \
kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option automount
KERNEL_IN_UBI := 1
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
target/linux/mediatek/mt7622/config-6.12
-516
View File
@@ -1,516 +0,0 @@
CONFIG_64BIT=y
# CONFIG_AHCI_MTK is not set
# CONFIG_AIROHA_EN8801SC_PHY is not set
# CONFIG_AIR_AN8855_PHY is not set
CONFIG_AQUANTIA_PHY=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PKEY_BITS=3
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANTS_EXECMEM_LATE=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PLATFORM_DEVICES=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_52 is not set
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_MEDIATEK_CPUFREQ=y
CONFIG_ARM_PMU=y
CONFIG_ARM_PMUV3=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ATA=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_NOTIFIERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_BUFFER_HEAD=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
CONFIG_COMMON_CLK_MT2712=y
# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
# CONFIG_COMMON_CLK_MT6779 is not set
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT6797 is not set
CONFIG_COMMON_CLK_MT7622=y
CONFIG_COMMON_CLK_MT7622_AUDSYS=y
CONFIG_COMMON_CLK_MT7622_ETHSYS=y
CONFIG_COMMON_CLK_MT7622_HIFSYS=y
# CONFIG_COMMON_CLK_MT7981 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7987 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8183 is not set
# CONFIG_COMMON_CLK_MT8186 is not set
# CONFIG_COMMON_CLK_MT8195 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRC16=y
CONFIG_CRC_CCITT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_MISC=y
CONFIG_DMADEVICES=y
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OF=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUNCTION_ALIGNMENT=4
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIO_CDEV=y
CONFIG_GRO_CELLS=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
# CONFIG_IDPF is not set
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INTEL_XWAY_PHY=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MSI_LIB=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JUMP_LABEL=y
CONFIG_LEDS_SMARTRG_LED=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LRU_GEN_WALKS_MMU=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAXLINEAR_GPHY=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MEDIATEK_2P5GE_PHY is not set
CONFIG_MEDIATEK_GE_PHY=y
# CONFIG_MEDIATEK_GE_SOC_PHY is not set
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
# CONFIG_MFD_AIROHA_AN8855 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_MTK=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_MEDIATEK=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MTK=y
CONFIG_MTD_NAND_MTK_BMT=y
CONFIG_MTD_PARSER_TRX=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_NVMEM=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_CPUX_TIMER=y
# CONFIG_MTK_CQDMA is not set
CONFIG_MTK_HSDMA=y
CONFIG_MTK_INFRACFG=y
# CONFIG_MTK_LVTS_THERMAL is not set
CONFIG_MTK_NET_PHYLIB=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_REGULATOR_COUPLER=y
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
# CONFIG_MTK_SOCINFO is not set
CONFIG_MTK_SOC_THERMAL=y
# CONFIG_MTK_SVS is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_NET_AIROHA is not set
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
# CONFIG_NET_DSA_MT7530_MMIO is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
CONFIG_NVMEM_BLOCK=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_LAYOUT_ADTRAN=y
CONFIG_NVMEM_MTK_EFUSE=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
CONFIG_PCIEASPM_PERFORMANCE=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PERF_EVENTS=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHY_MTK_DP is not set
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
# CONFIG_PHY_MTK_XSPHY is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_MT2712 is not set
# CONFIG_PINCTRL_MT6765 is not set
# CONFIG_PINCTRL_MT6795 is not set
# CONFIG_PINCTRL_MT6797 is not set
CONFIG_PINCTRL_MT7622=y
# CONFIG_PINCTRL_MT7981 is not set
# CONFIG_PINCTRL_MT7986 is not set
# CONFIG_PINCTRL_MT7987 is not set
# CONFIG_PINCTRL_MT7988 is not set
# CONFIG_PINCTRL_MT8173 is not set
# CONFIG_PINCTRL_MT8183 is not set
# CONFIG_PINCTRL_MT8186 is not set
# CONFIG_PINCTRL_MT8188 is not set
# CONFIG_PINCTRL_MT8516 is not set
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_OPP=y
CONFIG_POLYNOMIAL=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_SUPPLY=y
CONFIG_PRINTK_TIME=y
CONFIG_PSTORE=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_RAM=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
# CONFIG_RAVE_SP_CORE is not set
CONFIG_REALTEK_PHY=y
CONFIG_REALTEK_PHY_HWMON=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MT6380=y
CONFIG_RELOCATABLE=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MT7622=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTL8367S_GSW=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_MC=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
CONFIG_SPI_MTK_NOR=y
CONFIG_SPI_MTK_SNFI=y
CONFIG_SWCONFIG=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
# CONFIG_TEST_FPU is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_EMULATION=y
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UIMAGE_FIT_BLK=y
# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
CONFIG_USB_SUPPORT=y
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_VDSO_GETRANDOM=y
CONFIG_VMAP_STACK=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_SYSFS=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
target/linux/mediatek/mt7623/config-6.12
-525
View File
@@ -1,525 +0,0 @@
# CONFIG_AIO is not set
# CONFIG_AIROHA_EN8801SC_PHY is not set
# CONFIG_AIR_AN8855_PHY is not set
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
CONFIG_ARM_DMA_USE_IOMMU=y
CONFIG_ARM_GIC=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set
CONFIG_ARM_MEDIATEK_CPUFREQ=y
CONFIG_ARM_PAN=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LED=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BOUNCE=y
CONFIG_BUFFER_HEAD=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKSRC_MMIO=y
CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK_MEDIATEK=y
CONFIG_COMMON_CLK_MT2701=y
CONFIG_COMMON_CLK_MT2701_AUDSYS=y
CONFIG_COMMON_CLK_MT2701_BDPSYS=y
CONFIG_COMMON_CLK_MT2701_ETHSYS=y
CONFIG_COMMON_CLK_MT2701_G3DSYS=y
CONFIG_COMMON_CLK_MT2701_HIFSYS=y
CONFIG_COMMON_CLK_MT2701_IMGSYS=y
CONFIG_COMMON_CLK_MT2701_MMSYS=y
CONFIG_COMMON_CLK_MT2701_VDECSYS=y
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
# CONFIG_COMMON_CLK_MT7629 is not set
# CONFIG_COMMON_CLK_MT7981 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7987 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8135 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_COREDUMP=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_GENIV=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_ALIGN_RODATA=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_GPIO=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
CONFIG_DEBUG_MISC=y
CONFIG_DEBUG_MT6589_UART0=y
# CONFIG_DEBUG_MT8127_UART0 is not set
# CONFIG_DEBUG_MT8135_UART3 is not set
CONFIG_DEBUG_UART_8250=y
CONFIG_DEBUG_UART_8250_SHIFT=2
CONFIG_DEBUG_UART_PHYS=0x11004000
CONFIG_DEBUG_UART_VIRT=0xf1004000
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DRM=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_BRIDGE_CONNECTOR=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_LIMA=y
CONFIG_DRM_LVDS_CODEC=y
CONFIG_DRM_MEDIATEK=y
# CONFIG_DRM_MEDIATEK_DP is not set
CONFIG_DRM_MEDIATEK_HDMI=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
CONFIG_DRM_SCHED=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_EARLY_PRINTK=y
CONFIG_EINT_MTK=y
CONFIG_ELF_CORE=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FB=y
CONFIG_FB_CORE=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_DEVICE=y
CONFIG_FB_DMAMEM_HELPERS=y
CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y
CONFIG_FB_SYSMEM_FOPS=y
CONFIG_FB_SYSMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_IMAGEBLIT=y
CONFIG_FIXED_PHY=y
CONFIG_FONT_8x16=y
CONFIG_FONT_8x8=y
CONFIG_FONT_SUPPORT=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FREEZER=y
CONFIG_FS_MBCACHE=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_CACHE=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GRO_CELLS=y
# CONFIG_HARDEN_BRANCH_HISTORY is not set
# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
CONFIG_HAVE_SMP=y
CONFIG_HDMI=y
CONFIG_HID=y
CONFIG_HID_SUPPORT=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
CONFIG_IIO=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_IOMMUFD is not set
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_JBD2=y
CONFIG_KALLSYMS=y
CONFIG_KCMP=y
CONFIG_KEYBOARD_MTK_PMIC=y
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_LEDS_MT6323=y
# CONFIG_LEDS_QCOM_LPG is not set
# CONFIG_LEDS_SMARTRG_LED is not set
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_CLUT224=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MACH_MT2701 is not set
# CONFIG_MACH_MT6589 is not set
# CONFIG_MACH_MT6592 is not set
CONFIG_MACH_MT7623=y
# CONFIG_MACH_MT7629 is not set
# CONFIG_MACH_MT8127 is not set
# CONFIG_MACH_MT8135 is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MEDIATEK_GE_PHY=y
# CONFIG_MEDIATEK_MT6359_AUXADC is not set
CONFIG_MEDIATEK_MT6577_AUXADC=y
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MEMORY=y
# CONFIG_MFD_AIROHA_AN8855 is not set
CONFIG_MFD_CORE=y
# CONFIG_MFD_HI6421_SPMI is not set
CONFIG_MFD_MT6397=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_MTK_ADSP_MBOX is not set
CONFIG_MTK_CMDQ=y
CONFIG_MTK_CMDQ_MBOX=y
CONFIG_MTK_CPUX_TIMER=y
CONFIG_MTK_CQDMA=y
# CONFIG_MTK_HSDMA is not set
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_IOMMU=y
CONFIG_MTK_IOMMU_V1=y
# CONFIG_MTK_LVTS_THERMAL is not set
CONFIG_MTK_MMSYS=y
CONFIG_MTK_NET_PHYLIB=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_REGULATOR_COUPLER=y
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_SMI=y
# CONFIG_MTK_SOCINFO is not set
CONFIG_MTK_SOC_THERMAL=y
# CONFIG_MTK_SVS is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_SRCU_NMI_SAFE=y
CONFIG_NEON=y
# CONFIG_NET_AIROHA is not set
CONFIG_NET_DEVLINK=y
CONFIG_NET_DEVMEM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
# CONFIG_NET_DSA_MT7530_MMIO is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_VENDOR_MEDIATEK=y
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NLS=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
# CONFIG_NVMEM_LAYOUT_ADTRAN is not set
CONFIG_NVMEM_MTK_EFUSE=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_IOMMU=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MTK_DP is not set
CONFIG_PHY_MTK_HDMI=y
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
CONFIG_PHY_MTK_MIPI_DSI=y
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
# CONFIG_PHY_MTK_XSPHY is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MT2701=y
# CONFIG_PINCTRL_MT6397 is not set
CONFIG_PINCTRL_MT7623=y
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_DEVFREQ=y
# CONFIG_PM_DEVFREQ_EVENT is not set
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_OPP=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_MT6323 is not set
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_HWMON=y
CONFIG_PRINTK_TIME=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_RAS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MT6323=y
# CONFIG_REGULATOR_MT6331 is not set
# CONFIG_REGULATOR_MT6332 is not set
# CONFIG_REGULATOR_MT6357 is not set
# CONFIG_REGULATOR_MT6358 is not set
# CONFIG_REGULATOR_MT6380 is not set
# CONFIG_REGULATOR_MT6397 is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MT6397 is not set
# CONFIG_RTC_DRV_MT7622 is not set
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
# CONFIG_RTL8367S_GSW is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SERIAL_8250_DMA is not set
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
# CONFIG_SPI_MTK_NOR is not set
CONFIG_SPLIT_PTE_PTLOCKS=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_SPMI_MTK_PMIF is not set
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYNC_FILE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UIMAGE_FIT_BLK=y
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_G_MULTI=y
CONFIG_USB_G_MULTI_CDC=y
# CONFIG_USB_G_MULTI_RNDIS is not set
CONFIG_USB_HID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB_INVENTRA_DMA=y
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_MUSB_DUAL_ROLE=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_MEDIATEK=y
CONFIG_USB_OTG=y
CONFIG_USB_PHY=y
CONFIG_USB_ROLE_SWITCH=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_SERIAL=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_VIDEO=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
target/linux/mediatek/mt7629/config-6.12
-367
View File
@@ -1,367 +0,0 @@
# CONFIG_AIROHA_EN8801SC_PHY is not set
# CONFIG_AIR_AN8855_PHY is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_DEBUG_WX is not set
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_GROUP_RELOCS=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PAN=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_CACHE_L2X0=y
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CHR_DEV_SCH=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
CONFIG_CMDLINE_OVERRIDE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
# CONFIG_COMMON_CLK_MT2701 is not set
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
CONFIG_COMMON_CLK_MT7629=y
CONFIG_COMMON_CLK_MT7629_ETHSYS=y
CONFIG_COMMON_CLK_MT7629_HIFSYS=y
# CONFIG_COMMON_CLK_MT7981 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7987 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8135 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DEFAULT_HOSTNAME="(mt7629)"
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OPS_HELPERS=y
CONFIG_DTC=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y
CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIO_CDEV=y
CONFIG_GRO_CELLS=y
# CONFIG_HARDEN_BRANCH_HISTORY is not set
# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_HZ_FIXED=0
# CONFIG_IDPF is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQSTACKS=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
# CONFIG_LEDS_SMARTRG_LED is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MACH_MT2701 is not set
# CONFIG_MACH_MT6589 is not set
# CONFIG_MACH_MT6592 is not set
# CONFIG_MACH_MT7623 is not set
CONFIG_MACH_MT7629=y
# CONFIG_MACH_MT8127 is not set
# CONFIG_MACH_MT8135 is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MEDIATEK_WATCHDOG=y
# CONFIG_MFD_AIROHA_AN8855 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_MEDIATEK=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MTK_BMT=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_CPUX_TIMER=y
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_NET_PHYLIB=y
# CONFIG_MTK_PMIC_WRAP is not set
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_TIMER=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SRCU_NMI_SAFE=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_BPF_LINK=y
# CONFIG_NET_AIROHA is not set
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
# CONFIG_NET_DSA_MT7530_MMIO is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
# CONFIG_NVMEM_LAYOUT_ADTRAN is not set
CONFIG_NVMEM_LAYOUT_ASCII_ENV=y
# CONFIG_NVMEM_MTK_EFUSE is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MTK_DP is not set
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
# CONFIG_PHY_MTK_XSPHY is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MT7629=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
# CONFIG_RTL8367S_GSW is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
CONFIG_SPI_MTK_NOR=y
CONFIG_SPI_MTK_SNFI=y
CONFIG_STACKTRACE=y
# CONFIG_SWAP is not set
CONFIG_SWCONFIG=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MTK=y
# CONFIG_USB_XHCI_PLATFORM is not set
CONFIG_USE_OF=y
# CONFIG_VFP is not set
CONFIG_WATCHDOG_CORE=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch
-151
View File
@@ -1,151 +0,0 @@
From 1673d720b7e2862a5ff1994922558b7427f8a56b Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 17 Dec 2024 09:54:26 +0100
Subject: [PATCH 1/2] pinctrl: mediatek: add support for MTK_PULL_PD_TYPE
The MediaTek MT7988 SoC got some pins which only got configurable
pull-down but unlike previous designs there is no pull-up option.
Add new type MTK_PULL_PD_TYPE to support configuring such pins.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/20241217085435.9586-2-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 73 ++++++++++++++++---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 +
2 files changed, 63 insertions(+), 11 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -573,7 +573,7 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_r
*/
static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
- u32 pullup, u32 arg)
+ u32 pullup, u32 arg, bool pd_only)
{
int err, pu, pd;
@@ -587,18 +587,34 @@ static int mtk_pinconf_bias_set_pu_pd(st
pu = 0;
pd = 1;
} else {
- err = -EINVAL;
- goto out;
+ return -EINVAL;
}
- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
- if (err)
- goto out;
+ if (!pd_only) {
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
+ if (err)
+ return err;
+ }
- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
+}
+
+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 arg)
+{
+ int err, pd;
+
+ if (arg != MTK_DISABLE && arg != MTK_ENABLE)
+ return -EINVAL;
+
+ if (arg == MTK_DISABLE || pullup)
+ pd = 0;
+ else if (!pullup)
+ pd = 1;
+
+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
-out:
- return err;
}
static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
@@ -737,7 +753,7 @@ static int mtk_pinconf_bias_set_pu_pd_rs
return err;
}
- return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable);
+ return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false);
}
int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
@@ -758,8 +774,14 @@ int mtk_pinconf_bias_set_combo(struct mt
return 0;
}
+ if (try_all_type & MTK_PULL_PD_TYPE) {
+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true);
+ if (!err)
+ return err;
+ }
+
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false);
if (!err)
return 0;
}
@@ -878,6 +900,29 @@ out:
return err;
}
+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+{
+ int err, pd;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
+ if (err)
+ goto out;
+
+ if (pd == 0) {
+ *pullup = 0;
+ *enable = MTK_DISABLE;
+ } else if (pd == 1) {
+ *pullup = 0;
+ *enable = MTK_ENABLE;
+ } else
+ err = -EINVAL;
+
+out:
+ return err;
+}
+
static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 *pullup, u32 *enable)
@@ -947,6 +992,12 @@ int mtk_pinconf_bias_get_combo(struct mt
return 0;
}
+ if (try_all_type & MTK_PULL_PD_TYPE) {
+ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
+ if (!err)
+ return err;
+ }
+
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
if (!err)
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -24,6 +24,7 @@
* turned on/off itself. But it can't be selected pull up/down
*/
#define MTK_PULL_RSEL_TYPE BIT(3)
+#define MTK_PULL_PD_TYPE BIT(4)
/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
* MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
*/
target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch
-1610
View File
File diff suppressed because it is too large Load Diff
target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch
-41
View File
@@ -1,41 +0,0 @@
From 0e18b099672160698dfbd7c3c82e03e011c907e6 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Wed, 8 Jan 2025 22:52:44 +0100
Subject: [PATCH] pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd()
This function is unused and causing compile errors, delete it.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Link: https://lore.kernel.org/linux-next/20250106164630.4447cd0d@canb.auug.org.au/
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 18 ------------------
1 file changed, 18 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -599,24 +599,6 @@ static int mtk_pinconf_bias_set_pu_pd(st
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
}
-static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
- const struct mtk_pin_desc *desc,
- u32 pullup, u32 arg)
-{
- int err, pd;
-
- if (arg != MTK_DISABLE && arg != MTK_ENABLE)
- return -EINVAL;
-
- if (arg == MTK_DISABLE || pullup)
- pd = 0;
- else if (!pullup)
- pd = 1;
-
- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
-
-}
-
static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 arg)
target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch
-71
View File
@@ -1,71 +0,0 @@
From 52e2ca3be4b6d451fef0a2cd337157dd021b830f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Wed, 5 Jun 2024 10:54:33 +0200
Subject: [PATCH 01/32] arm64: dts: mediatek: mt7988: add UART controllers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
MT7988 has three on-SoC UART controllers that support M16C450 and
M16550A modes.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 35 ++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -86,7 +86,7 @@
#clock-cells = <1>;
};
- clock-controller@1001b000 {
+ topckgen: clock-controller@1001b000 {
compatible = "mediatek,mt7988-topckgen", "syscon";
reg = <0 0x1001b000 0 0x1000>;
#clock-cells = <1>;
@@ -124,6 +124,39 @@
status = "disabled";
};
+ serial@11000000 {
+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11000000 0 0x100>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uart", "wakeup";
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART0_CK>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ serial@11000100 {
+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11000100 0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uart", "wakeup";
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART1_CK>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ serial@11000200 {
+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11000200 0 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uart", "wakeup";
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART2_CK>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
i2c@11003000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11003000 0 0x1000>,
target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch
-35
View File
@@ -1,35 +0,0 @@
From 390529e00d5586eb6d7f4c33c23dee7f43ac14e7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Thu, 13 Jun 2024 21:59:33 +0200
Subject: [PATCH 02/32] arm64: dts: mediatek: mt7988: add efuse block
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
MT7988 (AKA MediaTek Filogic 880) uses efuse for storing calibration
data.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240613195933.31089-2-zajec5@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -234,6 +234,13 @@
#clock-cells = <1>;
};
+ efuse@11f50000 {
+ compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
+ reg = <0 0x11f50000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
clock-controller@15000000 {
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch
-85
View File
@@ -1,85 +0,0 @@
From a01cc71a8c55e7fc12cb37109953ad9c58a12d4f Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 09:54:29 +0100
Subject: [PATCH 03/32] arm64: dts: mediatek: mt7988: Add pinctrl support
Add mt7988a pinctrl node.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++
1 file changed, 54 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
/ {
compatible = "mediatek,mt7988a";
@@ -105,6 +106,59 @@
#clock-cells = <1>;
};
+ pio: pinctrl@1001f000 {
+ compatible = "mediatek,mt7988-pinctrl";
+ reg = <0 0x1001f000 0 0x1000>,
+ <0 0x11c10000 0 0x1000>,
+ <0 0x11d00000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11e00000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_tr",
+ "iocfg_br", "iocfg_rb",
+ "iocfg_lb", "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 84>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+
+ pcie0_pins: pcie0-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+ "pcie_wake_n0_0";
+ };
+ };
+
+ pcie1_pins: pcie1-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+ "pcie_wake_n1_0";
+ };
+ };
+
+ pcie2_pins: pcie2-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+ "pcie_wake_n2_0";
+ };
+ };
+
+ pcie3_pins: pcie3-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+ "pcie_wake_n3_0";
+ };
+ };
+ };
+
pwm@10048000 {
compatible = "mediatek,mt7988-pwm";
reg = <0 0x10048000 0 0x1000>;
target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch
-37
View File
@@ -1,37 +0,0 @@
From b3bb498ff23f5bcaa95614e0f8c9176690af8acb Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:15 +0100
Subject: [PATCH 04/32] arm64: dts: mediatek: mt7988: Add reserved memory
Add memory range handled by ATF to not be touched by linux kernel.
ATF is SoC specific and not board-specific so add it to mt7988.dtsi.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-2-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -62,6 +62,18 @@
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
+ secmon@43000000 {
+ reg = <0 0x43000000 0 0x50000>;
+ no-map;
+ };
+ };
+
soc {
compatible = "simple-bus";
ranges;
target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch
-52
View File
@@ -1,52 +0,0 @@
From de6ba1a3ef621762394e841888de3e0ed127e20a Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:16 +0100
Subject: [PATCH 05/32] arm64: dts: mediatek: mt7988: Add mmc support
Add devicetree node for MMC controller.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -112,7 +112,7 @@
#reset-cells = <1>;
};
- clock-controller@1001e000 {
+ apmixedsys: clock-controller@1001e000 {
compatible = "mediatek,mt7988-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
#clock-cells = <1>;
@@ -293,6 +293,25 @@
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
};
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7988-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11D60000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_MSDC400>,
+ <&infracfg CLK_INFRA_MSDC2_HCK>,
+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
+ <&apmixedsys CLK_APMIXED_MSDCPLL>;
+ clock-names = "source", "hclk", "axi_cg", "ahb_cg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch
-62
View File
@@ -1,62 +0,0 @@
From f07e0e093c42736df56f4830179c19f48f8b0725 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:17 +0100
Subject: [PATCH 06/32] arm64: dts: mediatek: mt7988: Add lvts node
Add Low Voltage Thermal Sensor (LVTS) node for mt7988 SoC.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-4-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
/ {
compatible = "mediatek,mt7988a";
@@ -97,6 +98,7 @@
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
topckgen: clock-controller@1001b000 {
@@ -265,6 +267,17 @@
status = "disabled";
};
+ lvts: lvts@1100a000 {
+ compatible = "mediatek,mt7988-lvts-ap";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x1100a000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_calibration>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ };
+
usb@11190000 {
compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
reg = <0 0x11190000 0 0x2e00>,
@@ -324,6 +337,10 @@
reg = <0 0x11f50000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ lvts_calibration: calib@918 {
+ reg = <0x918 0x28>;
+ };
};
clock-controller@15000000 {
target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch
-39
View File
@@ -1,39 +0,0 @@
From 122ed9fc41b948d79ac357f95f5438a4bd6786b8 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:18 +0100
Subject: [PATCH 07/32] arm64: dts: mediatek: mt7988: Add thermal-zone
Add basic thermal-zone node.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-5-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -358,6 +358,21 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&lvts 0>;
+ trips {
+ cpu_trip_crit: crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch
-31
View File
@@ -1,31 +0,0 @@
From 7fa08d530548ed57752703e9f011eeeb809ef9b0 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:20 +0100
Subject: [PATCH 08/32] arm64: dts: mediatek: mt7988: Add mcu-sys node for cpu
In preparation for adding support for CPU DVFS and clock tables for it,
add the MCUSYS clock controller node.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-7-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -192,6 +192,12 @@
status = "disabled";
};
+ mcusys: mcusys@100e0000 {
+ compatible = "mediatek,mt7988-mcusys", "syscon";
+ reg = <0 0x100e0000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
serial@11000000 {
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
reg = <0 0x11000000 0 0x100>;
target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch
-84
View File
@@ -1,84 +0,0 @@
From b10331c8faa1208c61fb98d9b65da2828e239113 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:21 +0100
Subject: [PATCH 09/32] arm64: dts: mediatek: mt7988: Add CPU OPP table for
clock scaling
Add operating points defining frequency/voltages of cpu cores.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -21,6 +21,10 @@
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu@1 {
@@ -28,6 +32,10 @@
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu@2 {
@@ -35,6 +43,10 @@
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu@3 {
@@ -42,6 +54,32 @@
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <900000>;
+ };
};
};
target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch
-34
View File
@@ -1,34 +0,0 @@
From 39bb12c26f556046e55f3638e2e4184bfbfd0564 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:22 +0100
Subject: [PATCH 10/32] arm64: dts: mediatek: mt7988: Disable usb controllers
by default
The controllers should be enabled at board level if used.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-9-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -334,6 +334,7 @@
<&infracfg CLK_INFRA_133M_USB_HCK>,
<&infracfg CLK_INFRA_USB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ status = "disabled";
};
usb@11200000 {
@@ -348,6 +349,7 @@
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ status = "disabled";
};
mmc0: mmc@11230000 {
target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch
-59
View File
@@ -1,59 +0,0 @@
From 46d056b6c2376d3ef866f9ab5212879c97588892 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:23 +0100
Subject: [PATCH 11/32] arm64: dts: mediatek: mt7988: Add t-phy for ssusb1
USB controller needs phys for working properly.
On mt7988 ssusb0 uses a xs-phy, ssusb uses t-phy.
For now add the t-phy for ssusb1. We can reuse the mt7986 compatible
here.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-10-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 25 +++++++++++++++++++++++
1 file changed, 25 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -349,6 +349,8 @@
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ phys = <&tphyu2port0 PHY_TYPE_USB2>,
+ <&tphyu3port0 PHY_TYPE_USB3>;
status = "disabled";
};
@@ -371,6 +373,29 @@
status = "disabled";
};
+ t-phy@11c50000 {
+ compatible = "mediatek,mt7986-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ tphyu2port0: usb-phy@11c50000 {
+ reg = <0 0x11c50000 0 0x700>;
+ clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ tphyu3port0: usb-phy@11c50700 {
+ reg = <0 0x11c50700 0 0x900>;
+ clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch
-176
View File
@@ -1,176 +0,0 @@
From aac2eb27ee500ca2828fe0fd1895ec6f9ef83787 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:24 +0100
Subject: [PATCH 12/32] arm64: dts: mediatek: mt7988: Add pcie nodes
Add pcie controllers for mt7988. Reuse mt7986 compatible.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-11-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 152 ++++++++++++++++++++++
1 file changed, 152 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -373,6 +373,158 @@
status = "disabled";
};
+ pcie@11280000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11280000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <3>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x20000000 0x00
+ 0x20000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x20200000 0x00
+ 0x20200000 0x00 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_pins>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+ <0 0 0 2 &pcie_intc2 1>,
+ <0 0 0 3 &pcie_intc2 2>,
+ <0 0 0 4 &pcie_intc2 3>;
+ pcie_intc2: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie@11290000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11290000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <2>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x28000000 0x00
+ 0x28000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x28200000 0x00
+ 0x28200000 0x00 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_pins>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+ <0 0 0 2 &pcie_intc3 1>,
+ <0 0 0 3 &pcie_intc3 2>,
+ <0 0 0 4 &pcie_intc3 3>;
+ pcie_intc3: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie@11300000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11300000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <0>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x30000000 0x00
+ 0x30000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x30200000 0x00
+ 0x30200000 0x00 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie@11310000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11310000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <1>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x38000000 0x00
+ 0x38000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x38200000 0x00
+ 0x38200000 0x00 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
t-phy@11c50000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
target/linux/mediatek/patches-6.12/032-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-pinctrl-subnod.patch
-211
View File
@@ -1,211 +0,0 @@
From 6b116c43782a153bcde18bd54d3220d81b476859 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 09:54:30 +0100
Subject: [PATCH 13/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl
subnodes for bpi-r4
Add board specific pinctrl configurations on Bananapi R4.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217085435.9586-6-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++
1 file changed, 189 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -9,3 +9,192 @@
model = "Banana Pi BPI-R4";
chassis-type = "embedded";
};
+
+&pio {
+ mdio0_pins: mdio0-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio0";
+ };
+
+ conf {
+ pins = "SMI_0_MDC", "SMI_0_MDIO";
+ drive-strength = <8>;
+ };
+ };
+
+ i2c0_pins: i2c0-g0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c0_1";
+ };
+ };
+
+ i2c1_pins: i2c1-g0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_0";
+ };
+ };
+
+ i2c1_sfp_pins: i2c1-sfp-g0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_sfp";
+ };
+ };
+
+ i2c2_0_pins: i2c2-g0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c2_0";
+ };
+ };
+
+ i2c2_1_pins: i2c2-g1-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c2_1";
+ };
+ };
+
+ gbe0_led0_pins: gbe0-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe0_led0";
+ };
+ };
+
+ gbe1_led0_pins: gbe1-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe1_led0";
+ };
+ };
+
+ gbe2_led0_pins: gbe2-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe2_led0";
+ };
+ };
+
+ gbe3_led0_pins: gbe3-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe3_led0";
+ };
+ };
+
+ gbe0_led1_pins: gbe0-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe0_led1";
+ };
+ };
+
+ gbe1_led1_pins: gbe1-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe1_led1";
+ };
+ };
+
+ gbe2_led1_pins: gbe2-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe2_led1";
+ };
+ };
+
+ gbe3_led1_pins: gbe3-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe3_led1";
+ };
+ };
+
+ i2p5gbe_led0_pins: 2p5gbe-led0-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
+ i2p5gbe_led1_pins: 2p5gbe-led1-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led1";
+ };
+ };
+
+ mmc0_pins_emmc_45: mmc0-emmc-45-pins {
+ mux {
+ function = "flash";
+ groups = "emmc_45";
+ };
+ };
+
+ mmc0_pins_emmc_51: mmc0-emmc-51-pins {
+ mux {
+ function = "flash";
+ groups = "emmc_51";
+ };
+ };
+
+ mmc0_pins_sdcard: mmc0-sdcard-pins {
+ mux {
+ function = "flash";
+ groups = "sdcard";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0";
+ };
+ };
+
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ spi0_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0";
+ };
+ };
+
+ spi0_flash_pins: spi0-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spi1_pins: spi1-pins {
+ mux {
+ function = "spi";
+ groups = "spi1";
+ };
+ };
+
+ spi2_pins: spi2-pins {
+ mux {
+ function = "spi";
+ groups = "spi2";
+ };
+ };
+
+ spi2_flash_pins: spi2-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi2", "spi2_wp_hold";
+ };
+ };
+};
target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch
-25
View File
@@ -1,25 +0,0 @@
From 6b6f2f1ee88b8b5763f4112babbc9fc45a94999a Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:25 +0100
Subject: [PATCH 14/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable watchdog
Enable the watchdog on Bananapi R4 board.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-12-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -198,3 +198,7 @@
};
};
};
+
+&watchdog {
+ status = "okay";
+};
target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch
-48
View File
@@ -1,48 +0,0 @@
From 72b0a6f181c5ca417405e594c80d724baee54813 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:26 +0100
Subject: [PATCH 15/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add fixed
regulators for 1v8 and 3v3
Add regulator nodes used for mmc to Bananapi R4 board.
This board has 1 MMC controller used for SDMMC and eMMC where only one can
be used at one time, selected by hardware switches. SD uses 3v3 for both
supplies and emmc uses both regulators.
So defining both regulators in board dts and referencing them in the dt
overlay.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-13-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -8,6 +8,24 @@
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
model = "Banana Pi BPI-R4";
chassis-type = "embedded";
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&pio {
target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch
-54
View File
@@ -1,54 +0,0 @@
From 67511ea667d3c4da827588fd460772562d7b054e Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:28 +0100
Subject: [PATCH 16/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add thermal
configuration
Add additional thermal trips to Bananapi R4 board.
SoC only contains the critical trip.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-15-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -28,6 +28,34 @@
};
};
+&cpu_thermal {
+ trips {
+ cpu_trip_hot: hot {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_trip_active_high: active-high {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_med: active-med {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_low: active-low {
+ temperature = <40000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
&pio {
mdio0_pins: mdio0-pins {
mux {
target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch
-41
View File
@@ -1,41 +0,0 @@
From a9df5ed2333b01546b4f906e2f6fd21dd5b146aa Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:29 +0100
Subject: [PATCH 17/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable serial0
debug uart
Enable the debug uart on Bananapi R4 board.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-16-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -245,6 +245,10 @@
};
};
+&serial0 {
+ status = "okay";
+};
+
&watchdog {
status = "okay";
};
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -236,7 +236,7 @@
#clock-cells = <1>;
};
- serial@11000000 {
+ serial0: serial@11000000 {
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
reg = <0 0x11000000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch
-29
View File
@@ -1,29 +0,0 @@
From 3dfb0dcb194e3f32ed931747131be08bfc429522 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:30 +0100
Subject: [PATCH 18/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add default UART
stdout
Add chosen node on Bananapi R4 board with stdout and default bootargs.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-17-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -9,6 +9,10 @@
model = "Banana Pi BPI-R4";
chassis-type = "embedded";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch
-72
View File
@@ -1,72 +0,0 @@
From 90d4eb65db14a3f2e776d2a8b1dc832e70198328 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:31 +0100
Subject: [PATCH 19/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable I2C
controllers
Enable the I2C0, I2C2 controllers found on the BananaPi R4 board.
Both controllers are not accessible from user and having fixed spare
devices. I2C0 have a pmic connected, I2C2 is used with I2C-multiplexer
for e.g. SFP cages.
The missing I2C1 is connected to GPIO header which can have either GPIO
mode or I2C mode.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-18-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 12 ++++++++++++
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 +++---
2 files changed, 15 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -60,6 +60,18 @@
};
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_1_pins>;
+ status = "okay";
+};
+
&pio {
mdio0_pins: mdio0-pins {
mux {
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -269,7 +269,7 @@
status = "disabled";
};
- i2c@11003000 {
+ i2c0: i2c@11003000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11003000 0 0x1000>,
<0 0x10217080 0 0x80>;
@@ -283,7 +283,7 @@
status = "disabled";
};
- i2c@11004000 {
+ i2c1: i2c@11004000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11004000 0 0x1000>,
<0 0x10217100 0 0x80>;
@@ -297,7 +297,7 @@
status = "disabled";
};
- i2c@11005000 {
+ i2c2: i2c@11005000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11005000 0 0x1000>,
<0 0x10217180 0 0x80>;
target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch
-74
View File
@@ -1,74 +0,0 @@
From dde7d741329616025e4cfa350eb3935b495ae140 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:32 +0100
Subject: [PATCH 20/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add PCA9545 I2C
Mux
Bananapi R4 uses an i2c multiplexer for SFP slots, rtc and eeprom.
Add its node to the right i2c controller.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-19-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -2,6 +2,8 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+
#include "mt7988a.dtsi"
/ {
@@ -70,6 +72,45 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c2_1_pins>;
status = "okay";
+
+ pca9545: i2c-mux@70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ size = <256>;
+ };
+
+ };
+
+ i2c_sfp1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_sfp2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ };
};
&pio {
target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch
-41
View File
@@ -1,41 +0,0 @@
From dfe00be85da20d9823d39775c92139c569a7960d Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:33 +0100
Subject: [PATCH 21/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable t-phy for
ssusb1
Bananapi R4 uses t-phy for usb. Enable its node at board level.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-20-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -306,6 +306,10 @@
status = "okay";
};
+&tphy {
+ status = "okay";
+};
+
&watchdog {
status = "okay";
};
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -525,7 +525,7 @@
};
};
- t-phy@11c50000 {
+ tphy: t-phy@11c50000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
#address-cells = <2>;

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