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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
2026-04-02 09:24:56 +08:00
parent 7220e63fda eba6fa859e
commit 24c36866be
94 changed files with 1889 additions and 2134 deletions
Download Patch File Download Diff File Expand all files Collapse all files
package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic
+6 -3
View File
@@ -59,9 +59,7 @@ tplink,tl-xdr6088|\
tplink,tl-xtr8488|\
xiaomi,mi-router-ax3000t-ubootmod|\
xiaomi,mi-router-wr30u-ubootmod|\
xiaomi,redmi-router-ax6000-ubootmod|\
zyxel,ex5601-t0-ubootmod|\
zyxel,wx5600-t0-ubootmod)
xiaomi,redmi-router-ax6000-ubootmod)
ubootenv_add_ubi_default
;;
acer,predator-w6|\
@@ -166,6 +164,11 @@ xiaomi,redmi-router-ax6000-stock)
zyxel,ex5601-t0)
ubootenv_add_mtd "u-boot-env" "0x0" "0x20000" "0x40000" "2"
;;
zyxel,ex5601-t0-ubootmod|\
zyxel,wx5600-t0-ubootmod)
ubootenv_add_ubi_default
ubootenv_add_sys_mtd "u-boot-env" "0x0" "0x20000" "0x40000" "2"
;;
zyxel,ex5700-telenor)
ubootenv_add_uci_config "/dev/ubootenv" "0x0" "0x4000" "0x4000" "1"
;;
package/libs/libunwind/Makefile
+1 -1
View File
@@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=libunwind
PKG_VERSION:=1.8.3
PKG_RELEASE:=2
PKG_RELEASE:=3
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/libunwind/libunwind/releases/download/v$(PKG_VERSION)/
package/libs/libunwind/patches/001-coredump-use-glibc-or-musl-register-names-as-appropr.patch
+97
View File
@@ -0,0 +1,97 @@
From df0807c1c2302c364c281d3d1109ddc10c9c7b19 Mon Sep 17 00:00:00 2001
From: Ross Burton <ross.burton@arm.com>
Date: Tue, 16 Jan 2024 18:21:26 +0000
Subject: [PATCH] coredump: use glibc or musl register names as appropriate on
MIPS
glibc has register macros of the form EF_REGx, but musl uses EF_Rx.
Handle this by using a macro to use the correct names.
Closes #708.
Signed-off-by: Ross Burton <ross.burton@arm.com>
---
src/coredump/_UCD_access_reg_linux.c | 69 ++++++++++++++++------------
1 file changed, 39 insertions(+), 30 deletions(-)
--- a/src/coredump/_UCD_access_reg_linux.c
+++ b/src/coredump/_UCD_access_reg_linux.c
@@ -100,38 +100,47 @@ _UCD_access_reg (unw_addr_space_t as UN
};
#else
#if defined(UNW_TARGET_MIPS)
+
+/* glibc and musl use different names */
+#ifdef __GLIBC__
+#define EF_REG(x) EF_REG ## x
+#else
+#include <sys/reg.h>
+#define EF_REG(x) EF_R ## x
+#endif
+
static const uint8_t remap_regs[] =
{
- [UNW_MIPS_R0] = EF_REG0,
- [UNW_MIPS_R1] = EF_REG1,
- [UNW_MIPS_R2] = EF_REG2,
- [UNW_MIPS_R3] = EF_REG3,
- [UNW_MIPS_R4] = EF_REG4,
- [UNW_MIPS_R5] = EF_REG5,
- [UNW_MIPS_R6] = EF_REG6,
- [UNW_MIPS_R7] = EF_REG7,
- [UNW_MIPS_R8] = EF_REG8,
- [UNW_MIPS_R9] = EF_REG9,
- [UNW_MIPS_R10] = EF_REG10,
- [UNW_MIPS_R11] = EF_REG11,
- [UNW_MIPS_R12] = EF_REG12,
- [UNW_MIPS_R13] = EF_REG13,
- [UNW_MIPS_R14] = EF_REG14,
- [UNW_MIPS_R15] = EF_REG15,
- [UNW_MIPS_R16] = EF_REG16,
- [UNW_MIPS_R17] = EF_REG17,
- [UNW_MIPS_R18] = EF_REG18,
- [UNW_MIPS_R19] = EF_REG19,
- [UNW_MIPS_R20] = EF_REG20,
- [UNW_MIPS_R21] = EF_REG21,
- [UNW_MIPS_R22] = EF_REG22,
- [UNW_MIPS_R23] = EF_REG23,
- [UNW_MIPS_R24] = EF_REG24,
- [UNW_MIPS_R25] = EF_REG25,
- [UNW_MIPS_R28] = EF_REG28,
- [UNW_MIPS_R29] = EF_REG29,
- [UNW_MIPS_R30] = EF_REG30,
- [UNW_MIPS_R31] = EF_REG31,
+ [UNW_MIPS_R0] = EF_REG(0),
+ [UNW_MIPS_R1] = EF_REG(1),
+ [UNW_MIPS_R2] = EF_REG(2),
+ [UNW_MIPS_R3] = EF_REG(3),
+ [UNW_MIPS_R4] = EF_REG(4),
+ [UNW_MIPS_R5] = EF_REG(5),
+ [UNW_MIPS_R6] = EF_REG(6),
+ [UNW_MIPS_R7] = EF_REG(7),
+ [UNW_MIPS_R8] = EF_REG(8),
+ [UNW_MIPS_R9] = EF_REG(9),
+ [UNW_MIPS_R10] = EF_REG(10),
+ [UNW_MIPS_R11] = EF_REG(11),
+ [UNW_MIPS_R12] = EF_REG(12),
+ [UNW_MIPS_R13] = EF_REG(13),
+ [UNW_MIPS_R14] = EF_REG(14),
+ [UNW_MIPS_R15] = EF_REG(15),
+ [UNW_MIPS_R16] = EF_REG(16),
+ [UNW_MIPS_R17] = EF_REG(17),
+ [UNW_MIPS_R18] = EF_REG(18),
+ [UNW_MIPS_R19] = EF_REG(19),
+ [UNW_MIPS_R20] = EF_REG(20),
+ [UNW_MIPS_R21] = EF_REG(21),
+ [UNW_MIPS_R22] = EF_REG(22),
+ [UNW_MIPS_R23] = EF_REG(23),
+ [UNW_MIPS_R24] = EF_REG(24),
+ [UNW_MIPS_R25] = EF_REG(25),
+ [UNW_MIPS_R28] = EF_REG(28),
+ [UNW_MIPS_R29] = EF_REG(29),
+ [UNW_MIPS_R30] = EF_REG(30),
+ [UNW_MIPS_R31] = EF_REG(31),
[UNW_MIPS_PC] = EF_CP0_EPC,
};
#elif defined(UNW_TARGET_S390X)
package/libs/libunwind/patches/002-fix-building-getcontext_S.patch
+13
View File
@@ -1,3 +1,16 @@
From b2d2e81e5fe53b01a0dd39e2e634f963ebeaab43 Mon Sep 17 00:00:00 2001
From: Ross Burton <ross.burton@arm.com>
Date: Tue, 16 Jan 2024 18:22:38 +0000
Subject: [PATCH] mips/getcontext.S: use assembler-friendly byte order symbols
endian.h on musl/mips can't be included in __ASSEMBLER__ mode,
so use the __BYTE_ORDER__ symbol instead.
Signed-off-by: Ross Burton <ross.burton@arm.com>
---
src/mips/getcontext.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/src/mips/getcontext.S
+++ b/src/mips/getcontext.S
@@ -24,12 +24,12 @@ OF CONTRACT, TORT OR OTHERWISE, ARISING
package/libs/libunwind/patches/003-fix-missing-ef_reg-defs-with-musl.patch
-45
View File
@@ -1,45 +0,0 @@
--- a/include/libunwind-mips.h
+++ b/include/libunwind-mips.h
@@ -121,6 +121,42 @@ typedef enum
}
mips_regnum_t;
+#ifndef __GLIBC__
+#include <sys/reg.h>
+
+/* musl as of 1.1.14 does not export these */
+#define EF_REG0 6
+#define EF_REG1 7
+#define EF_REG2 8
+#define EF_REG3 9
+#define EF_REG4 10
+#define EF_REG5 11
+#define EF_REG6 12
+#define EF_REG7 13
+#define EF_REG8 14
+#define EF_REG9 15
+#define EF_REG10 16
+#define EF_REG11 17
+#define EF_REG12 18
+#define EF_REG13 19
+#define EF_REG14 20
+#define EF_REG15 21
+#define EF_REG16 22
+#define EF_REG17 23
+#define EF_REG18 24
+#define EF_REG19 25
+#define EF_REG20 26
+#define EF_REG21 27
+#define EF_REG22 28
+#define EF_REG23 29
+#define EF_REG24 30
+#define EF_REG25 31
+#define EF_REG28 34
+#define EF_REG29 35
+#define EF_REG30 36
+#define EF_REG31 37
+#endif
+
typedef enum
{
UNW_MIPS_ABI_O32,
package/libs/libunwind/patches/004-ppc-musl.patch
+45 -212
View File
@@ -1,241 +1,74 @@
From 7f86abad3fec8c501c512283e5aa2512f91f7fbb Mon Sep 17 00:00:00 2001
From: Ross Burton <ross.burton@arm.com>
Date: Wed, 17 Jan 2024 16:28:39 +0000
Subject: [PATCH] Handle musl on PPC32
On Linux, glibc and musl disagree over the layout of the ucontext_t
structure. For more details, see the musl mailing list:
https://www.openwall.com/lists/musl/2018/02/22/1
Add conditionals to handle both the glibc and musl layout of the
structures.
Closes #709.
Signed-off-by: Ross Burton <ross.burton@arm.com>
---
src/ppc32/Ginit.c | 13 ++++++++++---
src/ppc32/ucontext_i.h | 5 +++++
2 files changed, 15 insertions(+), 3 deletions(-)
--- a/include/libunwind-ppc32.h
+++ b/include/libunwind-ppc32.h
@@ -40,6 +40,10 @@ extern "C" {
@@ -38,6 +38,7 @@ extern "C" {
#include <inttypes.h>
#include <stdint.h>
+#include <sys/reg.h>
#include <ucontext.h>
+#ifndef __GLIBC__
+#include <bits/reg.h>
+#endif
+
#ifndef UNW_EMPTY_STRUCT
# define UNW_EMPTY_STRUCT uint8_t unused;
#endif
@@ -81,6 +85,88 @@ typedef int64_t unw_sword_t;
typedef long double unw_tdep_fpreg_t;
+#ifndef __GLIBC__
+
+/* We can't include asm/ptrace.h here, as it conflicts with musl's definitions */
+
+#define PT_R0 0
+#define PT_R1 1
+#define PT_R2 2
+#define PT_R3 3
+#define PT_R4 4
+#define PT_R5 5
+#define PT_R6 6
+#define PT_R7 7
+#define PT_R8 8
+#define PT_R9 9
+#define PT_R10 10
+#define PT_R11 11
+#define PT_R12 12
+#define PT_R13 13
+#define PT_R14 14
+#define PT_R15 15
+#define PT_R16 16
+#define PT_R17 17
+#define PT_R18 18
+#define PT_R19 19
+#define PT_R20 20
+#define PT_R21 21
+#define PT_R22 22
+#define PT_R23 23
+#define PT_R24 24
+#define PT_R25 25
+#define PT_R26 26
+#define PT_R27 27
+#define PT_R28 28
+#define PT_R29 29
+#define PT_R30 30
+#define PT_R31 31
+
+#define PT_NIP 32
+#define PT_MSR 33
+#define PT_ORIG_R3 34
+#define PT_CTR 35
+#define PT_LNK 36
+#define PT_XER 37
+#define PT_CCR 38
+#ifndef __powerpc64__
+#define PT_MQ 39
+#else
+#define PT_SOFTE 39
+#endif
+#define PT_TRAP 40
+#define PT_DAR 41
+#define PT_DSISR 42
+#define PT_RESULT 43
+#define PT_DSCR 44
+#define PT_REGS_COUNT 44
+
+#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
+
+#ifndef __powerpc64__
+
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#else /* __powerpc64__ */
+
+#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
+
+
+#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
+#define PT_VSCR (PT_VR0 + 32*2 + 1)
+#define PT_VRSAVE (PT_VR0 + 33*2)
+
+
+/*
+ * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
+ */
+#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
+#define PT_VSR31 (PT_VSR0 + 2*31)
+#endif /* __powerpc64__ */
+
+#endif /* !__GLIBC__ */
+
typedef enum
{
UNW_PPC32_R0,
--- a/include/libunwind-ppc64.h
+++ b/include/libunwind-ppc64.h
@@ -40,6 +40,10 @@ extern "C" {
#include <stdint.h>
#include <ucontext.h>
+#ifndef __GLIBC__
+#include <bits/reg.h>
+#endif
+
#ifndef UNW_EMPTY_STRUCT
# define UNW_EMPTY_STRUCT uint8_t unused;
#endif
@@ -88,6 +92,88 @@ typedef struct {
uint64_t halves[2];
} unw_tdep_vreg_t;
+#ifndef __GLIBC__
+
+/* We can't include asm/ptrace.h here, as it conflicts with musl's definitions */
+
+#define PT_R0 0
+#define PT_R1 1
+#define PT_R2 2
+#define PT_R3 3
+#define PT_R4 4
+#define PT_R5 5
+#define PT_R6 6
+#define PT_R7 7
+#define PT_R8 8
+#define PT_R9 9
+#define PT_R10 10
+#define PT_R11 11
+#define PT_R12 12
+#define PT_R13 13
+#define PT_R14 14
+#define PT_R15 15
+#define PT_R16 16
+#define PT_R17 17
+#define PT_R18 18
+#define PT_R19 19
+#define PT_R20 20
+#define PT_R21 21
+#define PT_R22 22
+#define PT_R23 23
+#define PT_R24 24
+#define PT_R25 25
+#define PT_R26 26
+#define PT_R27 27
+#define PT_R28 28
+#define PT_R29 29
+#define PT_R30 30
+#define PT_R31 31
+
+#define PT_NIP 32
+#define PT_MSR 33
+#define PT_ORIG_R3 34
+#define PT_CTR 35
+#define PT_LNK 36
+#define PT_XER 37
+#define PT_CCR 38
+#ifndef __powerpc64__
+#define PT_MQ 39
+#else
+#define PT_SOFTE 39
+#endif
+#define PT_TRAP 40
+#define PT_DAR 41
+#define PT_DSISR 42
+#define PT_RESULT 43
+#define PT_DSCR 44
+#define PT_REGS_COUNT 44
+
+#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
+
+#ifndef __powerpc64__
+
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#else /* __powerpc64__ */
+
+#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
+
+
+#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
+#define PT_VSCR (PT_VR0 + 32*2 + 1)
+#define PT_VRSAVE (PT_VR0 + 33*2)
+
+
+/*
+ * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
+ */
+#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
+#define PT_VSR31 (PT_VSR0 + 2*31)
+#endif /* __powerpc64__ */
+
+#endif /* !__GLIBC__ */
+
typedef enum
{
UNW_PPC64_R0,
--- a/src/ppc32/Ginit.c
+++ b/src/ppc32/Ginit.c
@@ -46,10 +46,15 @@ static void *
@@ -42,6 +42,13 @@ static struct unw_addr_space local_addr_
unw_addr_space_t unw_local_addr_space = &local_addr_space;
+/* glibc and musl disagree over the layout of this struct */
+#ifdef __GLIBC__
+#define _UCONTEXT_UC_REGS(uc) uc->uc_mcontext.uc_regs
+#else
+#define _UCONTEXT_UC_REGS(uc) uc->uc_regs
+#endif
+
static void *
uc_addr (ucontext_t *uc, int reg)
{
void *addr;
+#ifdef __GLIBC__
+ mcontext_t *mc = uc->uc_mcontext.uc_regs;
+#else
+ mcontext_t *mc = &uc->uc_mcontext;
+#endif
@@ -49,7 +56,7 @@ uc_addr (ucontext_t *uc, int reg)
if ((unsigned) (reg - UNW_PPC32_R0) < 32)
#if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->gregs[reg - UNW_PPC32_R0];
+ addr = &mc->gregs[reg - UNW_PPC32_R0];
+ addr = &_UCONTEXT_UC_REGS(uc)->gregs[reg - UNW_PPC32_R0];
#elif defined(__FreeBSD__)
addr = &uc->uc_mcontext.mc_gpr[reg - UNW_PPC32_R0];
#endif
@@ -58,7 +63,7 @@ uc_addr (ucontext_t *uc, int reg)
@@ -58,7 +65,7 @@ uc_addr (ucontext_t *uc, int reg)
if ( ((unsigned) (reg - UNW_PPC32_F0) < 32) &&
((unsigned) (reg - UNW_PPC32_F0) >= 0) )
#if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->fpregs.fpregs[reg - UNW_PPC32_F0];
+ addr = &mc->fpregs.fpregs[reg - UNW_PPC32_F0];
+ addr = &_UCONTEXT_UC_REGS(uc)->fpregs.fpregs[reg - UNW_PPC32_F0];
#elif defined(__FreeBSD__)
addr = &uc->uc_mcontext.mc_fpreg[reg - UNW_PPC32_F0];
#endif
@@ -85,7 +90,7 @@ uc_addr (ucontext_t *uc, int reg)
@@ -85,7 +92,7 @@ uc_addr (ucontext_t *uc, int reg)
return NULL;
}
#if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->gregs[gregs_idx];
+ addr = &mc->gregs[gregs_idx];
+ addr = &_UCONTEXT_UC_REGS(uc)->gregs[gregs_idx];
#elif defined(__FreeBSD__)
addr = &uc->uc_mcontext.mc_gpr[gregs_idx];
#endif
@@ -249,8 +82,8 @@
#define _UC_MCONTEXT_GPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[x] - (void *)&dmy_ctxt) )
#define _UC_MCONTEXT_FPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[x] - (void *)&dmy_ctxt) )
+#else
+#define _UC_MCONTEXT_GPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.gregs[x] - (void *)&dmy_ctxt) )
+#define _UC_MCONTEXT_FPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.fpregs.fpregs[x] - (void *)&dmy_ctxt) )
+#define _UC_MCONTEXT_GPR(x) ( ((void *)&dmy_ctxt.uc_regs->gregs[x] - (void *)&dmy_ctxt) )
+#define _UC_MCONTEXT_FPR(x) ( ((void *)&dmy_ctxt.uc_regs->fpregs.fpregs[x] - (void *)&dmy_ctxt) )
+#endif
/* These are dummy structures used only for obtaining the offsets of the
package/libs/libunwind/patches/005-loongarch64-musl.patch
+12 -4
View File
@@ -1,12 +1,20 @@
From 05afdabf38d3fa461b7a9de80c64a6513a564d81 Mon Sep 17 00:00:00 2001
From: Jingyun Hua <huajingyun@loongson.cn>
Date: Mon, 8 Apr 2024 15:57:15 +0800
Subject: [PATCH] Remove the useless endina.h in getcontext.S for loongarch64
Fix issue #740
---
src/loongarch64/getcontext.S | 1 -
1 file changed, 1 deletion(-)
--- a/src/loongarch64/getcontext.S
+++ b/src/loongarch64/getcontext.S
@@ -25,7 +25,9 @@ OF CONTRACT, TORT OR OTHERWISE, ARISING
@@ -25,7 +25,6 @@ OF CONTRACT, TORT OR OTHERWISE, ARISING
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#include "offsets.h"
+#ifdef __GLIBC__
#include <endian.h>
+#endif
-#include <endian.h>
.text
#define SREG(X) st.d $r##X, $r4, (LINUX_UC_MCONTEXT_GREGS + 8 * X)
package/libs/wolfssl/Makefile
+4 -2
View File
@@ -88,7 +88,7 @@ define Package/libwolfsslcpu-crypto
$(call Package/libwolfssl/Default)
TITLE:=wolfSSL library with AES CPU instructions
PROVIDES:=libwolfssl libcyassl
DEPENDS:=@((aarch64||x86_64)&&(m||!TARGET_bcm27xx))
DEPENDS:=@((aarch64||x86_64||riscv64)&&(m||!TARGET_bcm27xx))
ABI_VERSION:=$(PKG_ABI_VERSION)
VARIANT:=cpu-crypto
endef
@@ -101,7 +101,7 @@ endef
define Package/libwolfsslcpu-crypto/description
$(call Package/libwolfssl/description)
This variant uses AES CPU instructions (Intel AESNI or ARMv8 Crypto Extension)
This variant uses AES CPU instructions (Intel AESNI, ARMv8 Crypto Extension or RISC-V ASM)
endef
define Package/libwolfsslcpu-crypto/config
@@ -192,6 +192,8 @@ else ifdef CONFIG_aarch64
Package/libwolfsslcpu-crypto/preinst=$(Package/libwolfsslcpu-crypto/preinst-aarch64)
else ifdef CONFIG_TARGET_x86_64
CONFIGURE_ARGS += --enable-intelasm
else ifdef CONFIG_riscv64
CONFIGURE_ARGS += --enable-riscv-asm
endif
ifeq ($(CONFIG_WOLFSSL_HAS_OCSP),y)
package/network/utils/wireguard-tools/Makefile
+2 -2
View File
@@ -35,8 +35,8 @@ define Package/wireguard-tools
MAINTAINER:=Jason A. Donenfeld <Jason@zx2c4.com>
TITLE:=WireGuard userspace control program (wg)
DEPENDS:= \
+!BUSYBOX_CONFIG_IP:ip \
+!BUSYBOX_CONFIG_FEATURE_IP_LINK:ip \
+@BUSYBOX_CONFIG_IP \
+@BUSYBOX_CONFIG_FEATURE_IP_LINK \
+kmod-wireguard
endef
target/linux/airoha/patches-6.12/134-v7.1-net-airoha-Delay-offloading-until-all-net_devices-ar.patch
+63
View File
@@ -0,0 +1,63 @@
From cedc1bf327de62ec30af9743bd1f601c2de30553 Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Sun, 29 Mar 2026 12:32:27 +0200
Subject: [PATCH] net: airoha: Delay offloading until all net_devices are fully
registered
Netfilter flowtable can theoretically try to offload flower rules as soon
as a net_device is registered while all the other ones are not
registered or initialized, triggering a possible NULL pointer dereferencing
of qdma pointer in airoha_ppe_set_cpu_port routine. Moreover, if
register_netdev() fails for a particular net_device, there is a small
race if Netfilter tries to offload flowtable rules before all the
net_devices are properly unregistered in airoha_probe() error patch,
triggering a NULL pointer dereferencing in airoha_ppe_set_cpu_port
routine. In order to avoid any possible race, delay offloading until
all net_devices are registered in the networking subsystem.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20260329-airoha-regiser-race-fix-v2-1-f4ebb139277b@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/ethernet/airoha/airoha_eth.c | 2 ++
drivers/net/ethernet/airoha/airoha_eth.h | 1 +
drivers/net/ethernet/airoha/airoha_ppe.c | 7 +++++++
3 files changed, 10 insertions(+)
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2957,6 +2957,8 @@ static int airoha_register_gdm_devices(s
return err;
}
+ set_bit(DEV_STATE_REGISTERED, &eth->state);
+
return 0;
}
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -88,6 +88,7 @@ enum {
enum {
DEV_STATE_INITIALIZED,
+ DEV_STATE_REGISTERED,
};
enum {
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -1387,6 +1387,13 @@ int airoha_ppe_setup_tc_block_cb(struct
struct airoha_eth *eth = ppe->eth;
int err = 0;
+ /* Netfilter flowtable can try to offload flower rules while not all
+ * the net_devices are registered or initialized. Delay offloading
+ * until all net_devices are registered in the system.
+ */
+ if (!test_bit(DEV_STATE_REGISTERED, &eth->state))
+ return -EBUSY;
+
mutex_lock(&flow_offload_mutex);
if (!eth->npu)
target/linux/airoha/patches-6.12/135-v7.1-net-airoha-Add-missing-cleanup-bits-in-airoha_qdma_c.patch
+57
View File
@@ -0,0 +1,57 @@
From 514aac3599879a7ed48b7dc19e31145beb6958ac Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Fri, 27 Mar 2026 10:48:21 +0100
Subject: [PATCH] net: airoha: Add missing cleanup bits in
airoha_qdma_cleanup_rx_queue()
In order to properly cleanup hw rx QDMA queues and bring the device to
the initial state, reset rx DMA queue head/tail index. Moreover, reset
queued DMA descriptor fields.
Fixes: 23020f049327 ("net: airoha: Introduce ethernet support for EN7581 SoC")
Tested-by: Madhur Agrawal <Madhur.Agrawal@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20260327-airoha_qdma_cleanup_rx_queue-fix-v1-1-369d6ab1511a@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/ethernet/airoha/airoha_eth.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -794,18 +794,34 @@ static int airoha_qdma_init_rx_queue(str
static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q)
{
- struct airoha_eth *eth = q->qdma->eth;
+ struct airoha_qdma *qdma = q->qdma;
+ struct airoha_eth *eth = qdma->eth;
+ int qid = q - &qdma->q_rx[0];
while (q->queued) {
struct airoha_queue_entry *e = &q->entry[q->tail];
+ struct airoha_qdma_desc *desc = &q->desc[q->tail];
struct page *page = virt_to_head_page(e->buf);
dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len,
page_pool_get_dma_dir(q->page_pool));
page_pool_put_full_page(q->page_pool, page, false);
+ /* Reset DMA descriptor */
+ WRITE_ONCE(desc->ctrl, 0);
+ WRITE_ONCE(desc->addr, 0);
+ WRITE_ONCE(desc->data, 0);
+ WRITE_ONCE(desc->msg0, 0);
+ WRITE_ONCE(desc->msg1, 0);
+ WRITE_ONCE(desc->msg2, 0);
+ WRITE_ONCE(desc->msg3, 0);
+
q->tail = (q->tail + 1) % q->ndesc;
q->queued--;
}
+
+ q->head = q->tail;
+ airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK,
+ FIELD_PREP(RX_RING_DMA_IDX_MASK, q->tail));
}
static int airoha_qdma_init_rx(struct airoha_qdma *qdma)
target/linux/airoha/patches-6.12/310-02-net-airoha-deassert-XSI-line-on-hw-init.patch
+1 -1
View File
@@ -13,7 +13,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1409,6 +1409,10 @@ static int airoha_hw_init(struct platfor
@@ -1425,6 +1425,10 @@ static int airoha_hw_init(struct platfor
if (err)
return err;
target/linux/airoha/patches-6.12/310-06-net-airoha-add-initial-fixup-for-GDM3-4-port-support.patch
+1 -1
View File
@@ -28,7 +28,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
airoha_fe_crsn_qsel_init(eth);
@@ -1641,7 +1643,8 @@ static int airoha_dev_open(struct net_de
@@ -1657,7 +1659,8 @@ static int airoha_dev_open(struct net_de
if (err)
return err;
target/linux/airoha/patches-6.12/310-07-airoha-ethernet-drop-xsi-mac-reset.patch
+2 -2
View File
@@ -15,7 +15,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -3109,7 +3109,6 @@ static void airoha_remove(struct platfor
@@ -3127,7 +3127,6 @@ static void airoha_remove(struct platfor
}
static const char * const en7581_xsi_rsts_names[] = {
@@ -23,7 +23,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
"hsi0-mac",
"hsi1-mac",
"hsi-mac",
@@ -3141,7 +3140,6 @@ static int airoha_en7581_get_src_port_id
@@ -3159,7 +3158,6 @@ static int airoha_en7581_get_src_port_id
}
static const char * const an7583_xsi_rsts_names[] = {
target/linux/airoha/patches-6.12/310-10-net-airoha-add-phylink-support-for-GDM2-4.patch
+8 -8
View File
@@ -35,7 +35,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
{
struct airoha_eth *eth = port->qdma->eth;
@@ -1638,6 +1644,17 @@ static int airoha_dev_open(struct net_de
@@ -1654,6 +1660,17 @@ static int airoha_dev_open(struct net_de
struct airoha_qdma *qdma = port->qdma;
u32 pse_port = FE_PSE_PORT_PPE1;
@@ -53,7 +53,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
netif_tx_start_all_queues(dev);
err = airoha_set_vip_for_gdm_port(port, true);
if (err)
@@ -1702,6 +1719,11 @@ static int airoha_dev_stop(struct net_de
@@ -1718,6 +1735,11 @@ static int airoha_dev_stop(struct net_de
}
}
@@ -65,7 +65,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
return 0;
}
@@ -2833,6 +2855,20 @@ static const struct ethtool_ops airoha_e
@@ -2849,6 +2871,20 @@ static const struct ethtool_ops airoha_e
.get_link = ethtool_op_get_link,
};
@@ -86,7 +86,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port)
{
int i;
@@ -2877,6 +2913,99 @@ bool airoha_is_valid_gdm_port(struct air
@@ -2893,6 +2929,99 @@ bool airoha_is_valid_gdm_port(struct air
return false;
}
@@ -186,7 +186,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
static int airoha_alloc_gdm_port(struct airoha_eth *eth,
struct device_node *np)
{
@@ -2948,6 +3077,12 @@ static int airoha_alloc_gdm_port(struct
@@ -2964,6 +3093,12 @@ static int airoha_alloc_gdm_port(struct
port->id = id;
eth->ports[p] = port;
@@ -199,7 +199,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
return airoha_metadata_dst_alloc(port);
}
@@ -3075,6 +3210,10 @@ error_napi_stop:
@@ -3093,6 +3228,10 @@ error_napi_stop:
if (port->dev->reg_state == NETREG_REGISTERED)
unregister_netdev(port->dev);
@@ -210,7 +210,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
airoha_metadata_dst_free(port);
}
airoha_hw_cleanup(eth);
@@ -3101,6 +3240,10 @@ static void airoha_remove(struct platfor
@@ -3119,6 +3258,10 @@ static void airoha_remove(struct platfor
unregister_netdev(port->dev);
airoha_metadata_dst_free(port);
@@ -223,7 +223,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -537,6 +537,10 @@ struct airoha_gdm_port {
@@ -538,6 +538,10 @@ struct airoha_gdm_port {
struct net_device *dev;
int id;
target/linux/airoha/patches-6.12/606-net-airoha-disable-external-phy-code-if-PCS_AIROHA-i.patch
+11 -11
View File
@@ -28,7 +28,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
{
@@ -1647,6 +1649,7 @@ static int airoha_dev_open(struct net_de
@@ -1663,6 +1665,7 @@ static int airoha_dev_open(struct net_de
struct airoha_qdma *qdma = port->qdma;
u32 pse_port = FE_PSE_PORT_PPE1;
@@ -36,7 +36,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
if (airhoa_is_phy_external(port)) {
err = phylink_of_phy_connect(port->phylink, dev->dev.of_node, 0);
if (err) {
@@ -1657,6 +1660,7 @@ static int airoha_dev_open(struct net_de
@@ -1673,6 +1676,7 @@ static int airoha_dev_open(struct net_de
phylink_start(port->phylink);
}
@@ -44,7 +44,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
netif_tx_start_all_queues(dev);
err = airoha_set_vip_for_gdm_port(port, true);
@@ -1722,10 +1726,12 @@ static int airoha_dev_stop(struct net_de
@@ -1738,10 +1742,12 @@ static int airoha_dev_stop(struct net_de
}
}
@@ -57,7 +57,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
return 0;
}
@@ -2858,6 +2864,7 @@ static const struct ethtool_ops airoha_e
@@ -2874,6 +2880,7 @@ static const struct ethtool_ops airoha_e
.get_link = ethtool_op_get_link,
};
@@ -65,7 +65,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
static struct phylink_pcs *airoha_phylink_mac_select_pcs(struct phylink_config *config,
phy_interface_t interface)
{
@@ -2871,6 +2878,7 @@ static void airoha_mac_config(struct phy
@@ -2887,6 +2894,7 @@ static void airoha_mac_config(struct phy
const struct phylink_link_state *state)
{
}
@@ -73,7 +73,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port)
{
@@ -2916,6 +2924,7 @@ bool airoha_is_valid_gdm_port(struct air
@@ -2932,6 +2940,7 @@ bool airoha_is_valid_gdm_port(struct air
return false;
}
@@ -81,7 +81,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
unsigned int mode, phy_interface_t interface,
int speed, int duplex, bool tx_pause, bool rx_pause)
@@ -3008,6 +3017,7 @@ static int airoha_setup_phylink(struct n
@@ -3024,6 +3033,7 @@ static int airoha_setup_phylink(struct n
return 0;
}
@@ -89,7 +89,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
static int airoha_alloc_gdm_port(struct airoha_eth *eth,
struct device_node *np)
@@ -3080,11 +3090,13 @@ static int airoha_alloc_gdm_port(struct
@@ -3096,11 +3106,13 @@ static int airoha_alloc_gdm_port(struct
port->id = id;
eth->ports[p] = port;
@@ -103,7 +103,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
return airoha_metadata_dst_alloc(port);
}
@@ -3213,10 +3225,12 @@ error_napi_stop:
@@ -3231,10 +3243,12 @@ error_napi_stop:
if (port->dev->reg_state == NETREG_REGISTERED)
unregister_netdev(port->dev);
@@ -116,7 +116,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
airoha_metadata_dst_free(port);
}
airoha_hw_cleanup(eth);
@@ -3243,10 +3257,12 @@ static void airoha_remove(struct platfor
@@ -3261,10 +3275,12 @@ static void airoha_remove(struct platfor
unregister_netdev(port->dev);
airoha_metadata_dst_free(port);
@@ -131,7 +131,7 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -537,9 +537,11 @@ struct airoha_gdm_port {
@@ -538,9 +538,11 @@ struct airoha_gdm_port {
struct net_device *dev;
int id;
target/linux/ath79/patches-6.12/730-ar8216-make-reg-access-atomic.patch
+3 -3
View File
@@ -14,7 +14,7 @@ with interrupts used.
---
--- a/drivers/net/phy/ar8216.c
+++ b/drivers/net/phy/ar8216.c
@@ -251,6 +251,7 @@ ar8xxx_mii_write32(struct ar8xxx_priv *p
@@ -250,6 +250,7 @@ ar8xxx_mii_write32(struct ar8xxx_priv *p
u32
ar8xxx_read(struct ar8xxx_priv *priv, int reg)
{
@@ -22,7 +22,7 @@ with interrupts used.
struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
u32 val;
@@ -258,11 +259,13 @@ ar8xxx_read(struct ar8xxx_priv *priv, in
@@ -257,11 +258,13 @@ ar8xxx_read(struct ar8xxx_priv *priv, in
split_addr((u32) reg, &r1, &r2, &page);
mutex_lock(&bus->mdio_lock);
@@ -36,7 +36,7 @@ with interrupts used.
mutex_unlock(&bus->mdio_lock);
return val;
@@ -271,17 +274,20 @@ ar8xxx_read(struct ar8xxx_priv *priv, in
@@ -270,17 +273,20 @@ ar8xxx_read(struct ar8xxx_priv *priv, in
void
ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
{
target/linux/generic/files/drivers/net/phy/ar8216.c
-1
View File
@@ -33,7 +33,6 @@
#include <linux/phy.h>
#include <linux/etherdevice.h>
#include <linux/lockdep.h>
#include <linux/ar8216_platform.h>
#include <linux/workqueue.h>
#include "ar8216.h"
target/linux/generic/files/drivers/net/phy/ar8327.c
+2 -221
View File
@@ -21,7 +21,6 @@
#include <linux/delay.h>
#include <linux/phy.h>
#include <linux/lockdep.h>
#include <linux/ar8216_platform.h>
#include <linux/workqueue.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -34,100 +33,6 @@
extern const struct ar8xxx_mib_desc ar8236_mibs[39];
extern const struct switch_attr ar8xxx_sw_attr_vlan[1];
static u32
ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
{
u32 t;
if (!cfg)
return 0;
t = 0;
switch (cfg->mode) {
case AR8327_PAD_NC:
break;
case AR8327_PAD_MAC2MAC_MII:
t = AR8327_PAD_MAC_MII_EN;
if (cfg->rxclk_sel)
t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
if (cfg->txclk_sel)
t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
break;
case AR8327_PAD_MAC2MAC_GMII:
t = AR8327_PAD_MAC_GMII_EN;
if (cfg->rxclk_sel)
t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
if (cfg->txclk_sel)
t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
break;
case AR8327_PAD_MAC_SGMII:
t = AR8327_PAD_SGMII_EN;
/*
* WAR for the QUalcomm Atheros AP136 board.
* It seems that RGMII TX/RX delay settings needs to be
* applied for SGMII mode as well, The ethernet is not
* reliable without this.
*/
t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
if (cfg->rxclk_delay_en)
t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
if (cfg->txclk_delay_en)
t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
if (cfg->sgmii_delay_en)
t |= AR8327_PAD_SGMII_DELAY_EN;
break;
case AR8327_PAD_MAC2PHY_MII:
t = AR8327_PAD_PHY_MII_EN;
if (cfg->rxclk_sel)
t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
if (cfg->txclk_sel)
t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
break;
case AR8327_PAD_MAC2PHY_GMII:
t = AR8327_PAD_PHY_GMII_EN;
if (cfg->pipe_rxclk_sel)
t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
if (cfg->rxclk_sel)
t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
if (cfg->txclk_sel)
t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
break;
case AR8327_PAD_MAC_RGMII:
t = AR8327_PAD_RGMII_EN;
t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
if (cfg->rxclk_delay_en)
t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
if (cfg->txclk_delay_en)
t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
break;
case AR8327_PAD_PHY_GMII:
t = AR8327_PAD_PHYX_GMII_EN;
break;
case AR8327_PAD_PHY_RGMII:
t = AR8327_PAD_PHYX_RGMII_EN;
break;
case AR8327_PAD_PHY_MII:
t = AR8327_PAD_PHYX_MII_EN;
break;
}
return t;
}
static void
ar8327_phy_rgmii_set(struct ar8xxx_priv *priv, struct phy_device *phydev)
{
@@ -194,34 +99,6 @@ ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
}
}
static u32
ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
{
u32 t;
if (!cfg->force_link)
return AR8216_PORT_STATUS_LINK_AUTO;
t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
switch (cfg->speed) {
case AR8327_PORT_SPEED_10:
t |= AR8216_PORT_SPEED_10M;
break;
case AR8327_PORT_SPEED_100:
t |= AR8216_PORT_SPEED_100M;
break;
case AR8327_PORT_SPEED_1000:
t |= AR8216_PORT_SPEED_1000M;
break;
}
return t;
}
#define AR8327_LED_ENTRY(_num, _reg, _shift) \
[_num] = { .reg = (_reg), .shift = (_shift) }
@@ -442,7 +319,7 @@ ar8327_led_create(struct ar8xxx_priv *priv,
if (led_info->led_num >= AR8327_NUM_LEDS)
return -EINVAL;
aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
aled = kzalloc(struct_size(aled, name, strlen(led_info->name) + 1),
GFP_KERNEL);
if (!aled)
return -ENOMEM;
@@ -456,7 +333,6 @@ ar8327_led_create(struct ar8xxx_priv *priv,
if (aled->mode == AR8327_LED_MODE_HW)
aled->enable_hw_mode = true;
aled->name = (char *)(aled + 1);
strcpy(aled->name, led_info->name);
aled->cdev.name = aled->name;
@@ -531,89 +407,6 @@ ar8327_leds_cleanup(struct ar8xxx_priv *priv)
kfree(data->leds);
}
static int
ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
struct ar8327_platform_data *pdata)
{
struct ar8327_led_cfg *led_cfg;
struct ar8327_data *data = priv->chip_data;
u32 pos, new_pos;
u32 t;
if (!pdata)
return -EINVAL;
priv->get_port_link = pdata->get_port_link;
data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
t = ar8327_get_pad_cfg(pdata->pad0_cfg);
if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
t |= AR8337_PAD_MAC06_EXCHANGE_EN;
ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
t = ar8327_get_pad_cfg(pdata->pad5_cfg);
ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
t = ar8327_get_pad_cfg(pdata->pad6_cfg);
ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRAP);
new_pos = pos;
led_cfg = pdata->led_cfg;
if (led_cfg) {
if (led_cfg->open_drain)
new_pos |= AR8327_POWER_ON_STRAP_LED_OPEN_EN;
else
new_pos &= ~AR8327_POWER_ON_STRAP_LED_OPEN_EN;
ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
if (new_pos != pos)
new_pos |= AR8327_POWER_ON_STRAP_POWER_ON_SEL;
}
if (pdata->sgmii_cfg) {
t = pdata->sgmii_cfg->sgmii_ctrl;
if (priv->chip_rev == 1)
t |= AR8327_SGMII_CTRL_EN_PLL |
AR8327_SGMII_CTRL_EN_RX |
AR8327_SGMII_CTRL_EN_TX;
else
t &= ~(AR8327_SGMII_CTRL_EN_PLL |
AR8327_SGMII_CTRL_EN_RX |
AR8327_SGMII_CTRL_EN_TX);
ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
if (pdata->sgmii_cfg->serdes_aen)
new_pos &= ~AR8327_POWER_ON_STRAP_SERDES_AEN;
else
new_pos |= AR8327_POWER_ON_STRAP_SERDES_AEN;
}
ar8xxx_write(priv, AR8327_REG_POWER_ON_STRAP, new_pos);
if (pdata->leds && pdata->num_leds) {
int i;
data->leds = kzalloc(pdata->num_leds * sizeof(void *),
GFP_KERNEL);
if (!data->leds)
return -ENOMEM;
for (i = 0; i < pdata->num_leds; i++)
ar8327_led_create(priv, &pdata->leds[i]);
}
return 0;
}
#ifdef CONFIG_OF
static int
ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
{
@@ -684,13 +477,6 @@ ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
of_node_put(leds);
return 0;
}
#else
static inline int
ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
{
return -EINVAL;
}
#endif
static int
ar8327_hw_init(struct ar8xxx_priv *priv)
@@ -701,12 +487,7 @@ ar8327_hw_init(struct ar8xxx_priv *priv)
if (!priv->chip_data)
return -ENOMEM;
if (priv->pdev->of_node)
ret = ar8327_hw_config_of(priv, priv->pdev->of_node);
else
ret = ar8327_hw_config_pdata(priv,
priv->phy->mdio.dev.platform_data);
ret = ar8327_hw_config_of(priv, priv->pdev->of_node);
if (ret)
return ret;
target/linux/generic/files/drivers/net/phy/ar8327.h
+33 -1
View File
@@ -303,11 +303,42 @@ struct ar8327_led_entry {
unsigned shift;
};
enum ar8327_led_num {
AR8327_LED_PHY0_0 = 0,
AR8327_LED_PHY0_1,
AR8327_LED_PHY0_2,
AR8327_LED_PHY1_0,
AR8327_LED_PHY1_1,
AR8327_LED_PHY1_2,
AR8327_LED_PHY2_0,
AR8327_LED_PHY2_1,
AR8327_LED_PHY2_2,
AR8327_LED_PHY3_0,
AR8327_LED_PHY3_1,
AR8327_LED_PHY3_2,
AR8327_LED_PHY4_0,
AR8327_LED_PHY4_1,
AR8327_LED_PHY4_2,
};
enum ar8327_led_mode {
AR8327_LED_MODE_HW = 0,
AR8327_LED_MODE_SW,
};
struct ar8327_led_info {
const char *name;
const char *default_trigger;
bool active_low;
enum ar8327_led_num led_num;
enum ar8327_led_mode mode;
struct fwnode_handle *fwnode;
};
struct ar8327_led {
struct led_classdev cdev;
struct ar8xxx_priv *sw_priv;
char *name;
bool active_low;
u8 led_num;
enum ar8327_led_mode mode;
@@ -318,6 +349,7 @@ struct ar8327_led {
bool enable_hw_mode;
enum ar8327_led_pattern pattern;
struct fwnode_handle *fwnode;
char name[];
};
struct ar8327_data {
target/linux/generic/files/include/linux/ar8216_platform.h
-134
View File
@@ -1,134 +0,0 @@
/*
* AR8216 switch driver platform data
*
* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef AR8216_PLATFORM_H
#define AR8216_PLATFORM_H
enum ar8327_pad_mode {
AR8327_PAD_NC = 0,
AR8327_PAD_MAC2MAC_MII,
AR8327_PAD_MAC2MAC_GMII,
AR8327_PAD_MAC_SGMII,
AR8327_PAD_MAC2PHY_MII,
AR8327_PAD_MAC2PHY_GMII,
AR8327_PAD_MAC_RGMII,
AR8327_PAD_PHY_GMII,
AR8327_PAD_PHY_RGMII,
AR8327_PAD_PHY_MII,
};
enum ar8327_clk_delay_sel {
AR8327_CLK_DELAY_SEL0 = 0,
AR8327_CLK_DELAY_SEL1,
AR8327_CLK_DELAY_SEL2,
AR8327_CLK_DELAY_SEL3,
};
struct ar8327_pad_cfg {
enum ar8327_pad_mode mode;
bool rxclk_sel;
bool txclk_sel;
bool pipe_rxclk_sel;
bool txclk_delay_en;
bool rxclk_delay_en;
bool sgmii_delay_en;
enum ar8327_clk_delay_sel txclk_delay_sel;
enum ar8327_clk_delay_sel rxclk_delay_sel;
bool mac06_exchange_dis;
};
enum ar8327_port_speed {
AR8327_PORT_SPEED_10 = 0,
AR8327_PORT_SPEED_100,
AR8327_PORT_SPEED_1000,
};
struct ar8327_port_cfg {
int force_link:1;
enum ar8327_port_speed speed;
int txpause:1;
int rxpause:1;
int duplex:1;
};
struct ar8327_sgmii_cfg {
u32 sgmii_ctrl;
bool serdes_aen;
};
struct ar8327_led_cfg {
u32 led_ctrl0;
u32 led_ctrl1;
u32 led_ctrl2;
u32 led_ctrl3;
bool open_drain;
};
enum ar8327_led_num {
AR8327_LED_PHY0_0 = 0,
AR8327_LED_PHY0_1,
AR8327_LED_PHY0_2,
AR8327_LED_PHY1_0,
AR8327_LED_PHY1_1,
AR8327_LED_PHY1_2,
AR8327_LED_PHY2_0,
AR8327_LED_PHY2_1,
AR8327_LED_PHY2_2,
AR8327_LED_PHY3_0,
AR8327_LED_PHY3_1,
AR8327_LED_PHY3_2,
AR8327_LED_PHY4_0,
AR8327_LED_PHY4_1,
AR8327_LED_PHY4_2,
};
enum ar8327_led_mode {
AR8327_LED_MODE_HW = 0,
AR8327_LED_MODE_SW,
};
struct ar8327_led_info {
const char *name;
const char *default_trigger;
bool active_low;
enum ar8327_led_num led_num;
enum ar8327_led_mode mode;
struct fwnode_handle *fwnode;
};
#define AR8327_LED_INFO(_led, _mode, _name) { \
.name = (_name), \
.led_num = AR8327_LED_ ## _led, \
.mode = AR8327_LED_MODE_ ## _mode \
}
struct ar8327_platform_data {
struct ar8327_pad_cfg *pad0_cfg;
struct ar8327_pad_cfg *pad5_cfg;
struct ar8327_pad_cfg *pad6_cfg;
struct ar8327_sgmii_cfg *sgmii_cfg;
struct ar8327_port_cfg port0_cfg;
struct ar8327_port_cfg port6_cfg;
struct ar8327_led_cfg *led_cfg;
int (*get_port_link)(unsigned port);
unsigned num_leds;
const struct ar8327_led_info *leds;
};
#endif /* AR8216_PLATFORM_H */
target/linux/generic/hack-6.18/905-io_uring-zcrx-Use-IS_REACHABLE-instead-of-IS_ENABLED.patch
+49
View File
@@ -0,0 +1,49 @@
From 6f6357583c491b451fb510071e39b6c56a521f95 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Tue, 31 Mar 2026 18:37:02 +0200
Subject: [PATCH] io_uring: zcrx: Use IS_REACHABLE() instead of IS_ENABLED()
We patch DMA_BUF to make it tristate, so once ALL_KMODS is selected it will
be built as a module even if previously disabled in the config.
So, since IO_URING_ZCRX does not depend on DMA_BUF linking will fail with:
aarch64-openwrt-linux-musl-ld: Unexpected GOT/PLT entries detected!
aarch64-openwrt-linux-musl-ld: Unexpected run-time procedure linkages detected!
aarch64-openwrt-linux-musl-ld: io_uring/zcrx.o: in function `io_release_dmabuf':
io_uring/zcrx.c:94:(.text+0x20): undefined reference to `dma_buf_unmap_attachment_unlocked'
aarch64-openwrt-linux-musl-ld: io_uring/zcrx.c:97:(.text+0x30): undefined reference to `dma_buf_detach'
aarch64-openwrt-linux-musl-ld: io_uring/zcrx.c:99:(.text+0x3c): undefined reference to `dma_buf_put'
aarch64-openwrt-linux-musl-ld: io_uring/zcrx.o: in function `io_import_dmabuf':
io_uring/zcrx.c:125:(.text+0x1b20): undefined reference to `dma_buf_get'
aarch64-openwrt-linux-musl-ld: io_uring/zcrx.c:132:(.text+0x1b34): undefined reference to `dma_buf_attach'
aarch64-openwrt-linux-musl-ld: io_uring/zcrx.c:139:(.text+0x1b48): undefined reference to `dma_buf_map_attachment_unlocked'
make[6]: *** [scripts/Makefile.vmlinux:72: vmlinux.unstripped] Error 1
So, lets use IS_REACHABLE() to check for CONFIG_DMA_SHARED_BUFFER instead
to avoid adding a dependency to CONFIG_DMA_SHARED_BUFFER.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
io_uring/zcrx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/io_uring/zcrx.c
+++ b/io_uring/zcrx.c
@@ -87,7 +87,7 @@ static int io_populate_area_dma(struct i
static void io_release_dmabuf(struct io_zcrx_mem *mem)
{
- if (!IS_ENABLED(CONFIG_DMA_SHARED_BUFFER))
+ if (!IS_REACHABLE(CONFIG_DMA_SHARED_BUFFER))
return;
if (mem->sgt)
@@ -118,7 +118,7 @@ static int io_import_dmabuf(struct io_zc
return -EINVAL;
if (WARN_ON_ONCE(!ifq->dev))
return -EFAULT;
- if (!IS_ENABLED(CONFIG_DMA_SHARED_BUFFER))
+ if (!IS_REACHABLE(CONFIG_DMA_SHARED_BUFFER))
return -EINVAL;
mem->is_dmabuf = true;
target/linux/generic/pending-6.12/308-mips32r2_tune.patch
+2 -2
View File
@@ -1,5 +1,5 @@
From: Felix Fietkau <nbd@nbd.name>
Subject: kernel: add -mtune=34kc to MIPS CFLAGS when building for mips32r2
Subject: kernel: add -mtune=24kc to MIPS CFLAGS when building for mips32r2
This provides a good tradeoff across at least 24Kc-74Kc, while also
producing smaller code.
@@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
-cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap
+cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=34kc -Wa,--trap
+cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=24kc -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap
target/linux/generic/pending-6.18/308-mips32r2_tune.patch
+2 -2
View File
@@ -1,5 +1,5 @@
From: Felix Fietkau <nbd@nbd.name>
Subject: kernel: add -mtune=34kc to MIPS CFLAGS when building for mips32r2
Subject: kernel: add -mtune=24kc to MIPS CFLAGS when building for mips32r2
This provides a good tradeoff across at least 24Kc-74Kc, while also
producing smaller code.
@@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
-cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap
+cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=34kc -Wa,--trap
+cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=24kc -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap
target/linux/ipq40xx/patches-6.12/701-net-dsa-add-out-of-band-tagging-protocol.patch
+2 -2
View File
@@ -111,9 +111,9 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
#define DSA_TAG_PROTO_MXL862_8021Q_VALUE 31
+#define DSA_TAG_PROTO_OOB_VALUE 32
enum dsa_tag_protocol {
@@ -92,6 +93,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -91,6 +92,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_VSC73XX_8021Q = DSA_TAG_PROTO_VSC73XX_8021Q_VALUE,
DSA_TAG_PROTO_MXL862 = DSA_TAG_PROTO_MXL862_VALUE,
DSA_TAG_PROTO_MXL862_8021Q = DSA_TAG_PROTO_MXL862_8021Q_VALUE,
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi
+1
View File
@@ -177,6 +177,7 @@
nvmem-layout {
compatible = "u-boot,env";
env-size = <0x1000>;
macaddr_uboot_ethaddr: ethaddr {
#nvmem-cell-cells = <1>;
target/linux/malta/Makefile
+1
View File
@@ -11,6 +11,7 @@ INITRAMFS_EXTRA_FILES:=
FEATURES:=cpiogz ext4 ramdisk squashfs targz
KERNEL_PATCHVER:=6.12
KERNEL_TESTING_PATCHVER:=6.18
include $(INCLUDE_DIR)/target.mk
target/linux/malta/config-6.18
+272
View File
@@ -0,0 +1,272 @@
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ATA=y
CONFIG_ATA_PIIX=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_BSG_COMMON=y
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOARD_SCACHE=y
CONFIG_BOOT_ELF32=y
CONFIG_BUFFER_HEAD=y
CONFIG_BUILTIN_DTB=y
CONFIG_CEVT_R4K=y
CONFIG_CLKBLD_I8253=y
CONFIG_CLKEVT_I8253=y
CONFIG_CLKSRC_I8253=y
CONFIG_CLKSRC_MIPS_GIC=y
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_PREFETCH=y
# CONFIG_CPU_HAS_SMARTMIPS is not set
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_MICROMIPS is not set
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS32_3_5_FEATURES is not set
# CONFIG_CPU_MIPS32_R1 is not set
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS32_R5 is not set
# CONFIG_CPU_MIPS32_R5_FEATURES is not set
# CONFIG_CPU_MIPS32_R6 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
# CONFIG_CPU_MIPS64_R6 is not set
# CONFIG_CPU_MIPSR1 is not set
# CONFIG_CPU_MIPSR2 is not set
# CONFIG_CPU_MIPSR2_IRQ_EI is not set
# CONFIG_CPU_MIPSR2_IRQ_VI is not set
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
# CONFIG_CPU_NEVADA is not set
CONFIG_CPU_R4K_CACHE_TLB=y
# CONFIG_CPU_RM7000 is not set
CONFIG_CPU_RMAP=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CRC16=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DNOTIFY=y
CONFIG_DTC=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GENERIC_LIB_CMPDI2=y
CONFIG_GENERIC_LIB_LSHRDI3=y
CONFIG_GENERIC_LIB_UCMPDI2=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIO_CDEV=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_I8259=y
CONFIG_INPUT=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
CONFIG_ISA_DMA_API=y
CONFIG_JBD2=y
CONFIG_KALLSYMS=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_XZ is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_MD=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_MIPS_ASID_SHIFT=0
CONFIG_MIPS_BONITO64=y
CONFIG_MIPS_CLOCK_VSYSCALL=y
CONFIG_MIPS_CM=y
CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
CONFIG_MIPS_CPC=y
CONFIG_MIPS_CPU_SCACHE=y
CONFIG_MIPS_EXTERNAL_TIMER=y
CONFIG_MIPS_GIC=y
CONFIG_MIPS_L1_CACHE_SHIFT=6
CONFIG_MIPS_L1_CACHE_SHIFT_6=y
CONFIG_MIPS_MALTA=y
CONFIG_MIPS_MSC=y
CONFIG_MIPS_MT=y
CONFIG_MIPS_MT_FPAFF=y
CONFIG_MIPS_MT_SMP=y
CONFIG_MIPS_NO_APPENDED_DTB=y
CONFIG_MIPS_NR_CPU_NR_MAP=2
CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MTD_CFI_STAA=y
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SRCU_NMI_SAFE=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PATA_LEGACY=y
CONFIG_PATA_TIMINGS=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PCI_GT64XXX_PCI0=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_QFMT_V2=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_QUOTA=y
CONFIG_QUOTACTL=y
CONFIG_QUOTA_TREE=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RELAY=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_SATA_HOST=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SMP_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SYNC_R4K=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y
CONFIG_SYS_HAS_CPU_MIPS32_R5=y
CONFIG_SYS_HAS_CPU_MIPS32_R6=y
CONFIG_SYS_HAS_CPU_MIPS64_R1=y
CONFIG_SYS_HAS_CPU_MIPS64_R2=y
CONFIG_SYS_HAS_CPU_MIPS64_R6=y
CONFIG_SYS_HAS_CPU_NEVADA=y
CONFIG_SYS_HAS_CPU_RM7000=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_HIGHMEM=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
CONFIG_SYS_SUPPORTS_MICROMIPS=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_MIPS_CPS=y
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
CONFIG_SYS_SUPPORTS_RELOCATABLE=y
CONFIG_SYS_SUPPORTS_SMARTMIPS=y
CONFIG_SYS_SUPPORTS_SMP=y
CONFIG_SYS_SUPPORTS_VPE_LOADER=y
CONFIG_SYS_SUPPORTS_ZBOOT=y
CONFIG_TARGET_ISA_REV=1
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_VXFS_FS=y
CONFIG_WAR_ICACHE_REFILLS=y
CONFIG_XPS=y
CONFIG_ZBOOT_LOAD_ADDRESS=0x0
target/linux/mediatek/image/filogic.mk
+2
View File
@@ -399,6 +399,8 @@ TARGET_DEVICES += arcadyan_mozart
define Device/asus_rt-ax52
DEVICE_VENDOR := ASUS
DEVICE_MODEL := RT-AX52
DEVICE_ALT0_VENDOR := ASUS
DEVICE_ALT0_MODEL := RT-AX52 PRO
DEVICE_DTS := mt7981b-asus-rt-ax52
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
target/linux/mediatek/patches-6.12/062-v6.18-arm64-dts-mediatek-add-thermal-sensor-support-on-mt7.patch
+69
View File
@@ -0,0 +1,69 @@
From 0da6f7a0ab5322eb6d091a9c89d799adfeae078d Mon Sep 17 00:00:00 2001
From: Aleksander Jan Bajkowski <olek2@wp.pl>
Date: Sun, 7 Sep 2025 13:15:09 +0200
Subject: [PATCH] arm64: dts: mediatek: add thermal sensor support on mt7981
The temperature sensor in the MT7981 is same as in the MT7986.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250907111742.23195-2-olek2@wp.pl
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 31 ++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
@@ -76,7 +76,7 @@
#reset-cells = <1>;
};
- clock-controller@1001e000 {
+ apmixedsys: clock-controller@1001e000 {
compatible = "mediatek,mt7981-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
#clock-cells = <1>;
@@ -184,6 +184,31 @@
status = "disabled";
};
+ thermal@1100c800 {
+ compatible = "mediatek,mt7981-thermal",
+ "mediatek,mt7986-thermal";
+ reg = <0 0x1100c800 0 0x800>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_THERM_CK>,
+ <&infracfg CLK_INFRA_ADC_26M_CK>;
+ clock-names = "therm", "auxadc";
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
+
+ auxadc: adc@1100d000 {
+ compatible = "mediatek,mt7981-auxadc",
+ "mediatek,mt7986-auxadc";
+ reg = <0 0x1100d000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
@@ -211,6 +236,10 @@
reg = <0 0x11f20000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ thermal_calibration: thermal-calib@274 {
+ reg = <0x274 0xc>;
+ };
};
clock-controller@15000000 {
target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch
+37 -49
View File
@@ -88,13 +88,11 @@ working:
soc {
compatible = "simple-bus";
ranges;
@@ -76,13 +134,13 @@
#reset-cells = <1>;
@@ -77,12 +135,12 @@
};
- clock-controller@1001e000 {
apmixedsys: clock-controller@1001e000 {
- compatible = "mediatek,mt7981-apmixedsys";
+ apmixedsys: clock-controller@1001e000 {
+ compatible = "mediatek,mt7981-apmixedsys", "syscon";
reg = <0 0x1001e000 0 0x1000>;
#clock-cells = <1>;
@@ -160,41 +158,16 @@ working:
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
<&infracfg CLK_INFRA_AP_DMA_CK>,
<&infracfg CLK_INFRA_I2C_MCK_CK>,
@@ -142,7 +215,32 @@
@@ -142,7 +215,7 @@
status = "disabled";
};
- spi@11009000 {
+ thermal: thermal@1100c800 {
+ #thermal-sensor-cells = <1>;
+ compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
+ reg = <0 0x1100c800 0 0x800>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_THERM_CK>,
+ <&infracfg CLK_INFRA_ADC_26M_CK>;
+ clock-names = "therm", "auxadc";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ };
+
+ auxadc: adc@1100d000 {
+ compatible = "mediatek,mt7981-auxadc",
+ "mediatek,mt7986-auxadc",
+ "mediatek,mt7622-auxadc";
+ reg = <0 0x1100d000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
+ <&infracfg CLK_INFRA_ADC_FRC_CK>;
+ clock-names = "main", "32k";
+ #io-channel-cells = <1>;
+ };
+
+ spi2: spi@11009000 {
compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x11009000 0 0x1000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
@@ -156,7 +254,7 @@
@@ -156,7 +229,7 @@
status = "disabled";
};
@@ -203,7 +176,7 @@ working:
compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
@@ -170,7 +268,7 @@
@@ -170,7 +243,7 @@
status = "disabled";
};
@@ -212,10 +185,31 @@ working:
compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
@@ -184,6 +282,41 @@
@@ -184,7 +257,7 @@
status = "disabled";
};
- thermal@1100c800 {
+ thermal: thermal@1100c800 {
compatible = "mediatek,mt7981-thermal",
"mediatek,mt7986-thermal";
reg = <0 0x1100c800 0 0x800>;
@@ -201,12 +274,48 @@
auxadc: adc@1100d000 {
compatible = "mediatek,mt7981-auxadc",
- "mediatek,mt7986-auxadc";
+ "mediatek,mt7986-auxadc",
+ "mediatek,mt7622-auxadc";
reg = <0 0x1100d000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
- clock-names = "main";
+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
+ <&infracfg CLK_INFRA_ADC_FRC_CK>;
+ clock-names = "main", "32k";
#io-channel-cells = <1>;
+ };
+
+ pcie: pcie@11280000 {
+ compatible = "mediatek,mt7981-pcie",
+ "mediatek,mt8192-pcie";
@@ -228,7 +222,7 @@ working:
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000
+ 0x0 0x20000000 0 0x10000000>;
+ status = "disabled";
status = "disabled";
+
+ clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
+ <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
@@ -249,12 +243,10 @@ working:
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
};
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
@@ -204,6 +337,35 @@
@@ -229,6 +338,35 @@
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
@@ -290,14 +282,10 @@ working:
};
efuse@11f20000 {
@@ -211,17 +373,297 @@
reg = <0 0x11f20000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ thermal_calibration: thermal-calib@274 {
+ reg = <0x274 0xc>;
+ };
@@ -240,17 +378,293 @@
thermal_calibration: thermal-calib@274 {
reg = <0x274 0xc>;
};
+
+ phy_calibration: phy-calib@8dc {
+ reg = <0x8dc 0x10>;
@@ -590,7 +578,7 @@ working:
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
@@ -234,6 +676,67 @@
@@ -263,6 +677,67 @@
clock-names = "mcu", "ap2conn";
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
@@ -658,7 +646,7 @@ working:
};
};
@@ -245,4 +748,8 @@
@@ -274,4 +749,8 @@
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch
+3 -3
View File
@@ -14,7 +14,7 @@ Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
@@ -248,6 +248,10 @@
@@ -223,6 +223,10 @@
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI2_CK>,
<&infracfg CLK_INFRA_SPI2_HCK_CK>;
@@ -25,7 +25,7 @@ Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
@@ -262,6 +266,10 @@
@@ -237,6 +241,10 @@
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0_CK>,
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
@@ -36,7 +36,7 @@ Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
@@ -273,9 +281,13 @@
@@ -248,9 +256,13 @@
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh
+40 -11
View File
@@ -116,6 +116,44 @@ tplink_do_upgrade() {
nand_do_upgrade "$1"
}
linksys_mr_pre_upgrade() {
local setenv_script="/tmp/fw_env_upgrade"
CI_UBIPART="rootfs"
boot_part="$(fw_printenv -n boot_part)"
if [ -n "$UPGRADE_OPT_USE_CURR_PART" ]; then
if [ "$boot_part" -eq "2" ]; then
CI_KERNPART="alt_kernel"
CI_UBIPART="alt_rootfs"
fi
else
if [ "$boot_part" -eq "1" ]; then
echo "boot_part 2" >> $setenv_script
CI_KERNPART="alt_kernel"
CI_UBIPART="alt_rootfs"
else
echo "boot_part 1" >> $setenv_script
fi
fi
boot_part_ready="$(fw_printenv -n boot_part_ready)"
if [ "$boot_part_ready" -ne "3" ]; then
echo "boot_part_ready 3" >> $setenv_script
fi
auto_recovery="$(fw_printenv -n auto_recovery)"
if [ "$auto_recovery" != "yes" ]; then
echo "auto_recovery yes" >> $setenv_script
fi
if [ -f "$setenv_script" ]; then
fw_setenv -s $setenv_script || {
echo "failed to update U-Boot environment"
return 1
}
fi
}
platform_check_image() {
return 0;
}
@@ -192,17 +230,8 @@ platform_do_upgrade() {
;;
linksys,mr7350|\
linksys,mr7500)
boot_part="$(fw_printenv -n boot_part)"
if [ "$boot_part" -eq "1" ]; then
fw_setenv boot_part 2
CI_KERNPART="alt_kernel"
CI_UBIPART="alt_rootfs"
else
fw_setenv boot_part 1
CI_UBIPART="rootfs"
fi
fw_setenv boot_part_ready 3
fw_setenv auto_recovery yes
linksys_mr_pre_upgrade "$1"
remove_oem_ubi_volume squashfs
nand_do_upgrade "$1"
;;
tplink,eap610-outdoor|\
target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4c.dts
+8 -1
View File
@@ -34,7 +34,7 @@
wan {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
};
@@ -59,6 +59,13 @@
};
};
&state_default {
gpio {
groups = "gpio", "wdt", "p1led_an", "wled_an";
function = "gpio";
};
};
&ehci {
status = "disabled";
};
target/linux/realtek/dts/macros.dtsi
+8 -2
View File
@@ -13,12 +13,18 @@
phy-is-integrated; \
};
#define EXTERNAL_PHY(n) \
phy##n: ethernet-phy@##n { \
#define PHY_C22(p, n) \
phy##p: ethernet-phy@n { \
reg = <##n>; \
compatible = "ethernet-phy-ieee802.3-c22"; \
};
#define PHY_C45(p, n) \
phy##p: ethernet-phy@n { \
reg = <##n>; \
compatible = "ethernet-phy-ieee802.3-c45"; \
};
#define EXTERNAL_SFP_PHY(n) \
phy##n: ethernet-phy@##n { \
compatible = "ethernet-phy-ieee802.3-c22"; \
target/linux/realtek/dts/rtl8380_netgear_gs110tpp-v1.dts
+2 -2
View File
@@ -55,8 +55,8 @@
};
&mdio_bus0 {
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
PHY_C22(16, 16)
PHY_C22(17, 17)
};
&switch0 {
target/linux/realtek/dts/rtl8380_netgear_gs110tup-v1.dts
+1 -1
View File
@@ -46,7 +46,7 @@
};
&mdio_bus0 {
EXTERNAL_PHY(16)
PHY_C22(16, 16)
};
&switch0 {
target/linux/realtek/dts/rtl8382_apresia_aplgs120gtss.dts
+8 -8
View File
@@ -200,14 +200,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
INTERNAL_PHY(8)
INTERNAL_PHY(9)
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-16.dts
+8 -8
View File
@@ -10,14 +10,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
INTERNAL_PHY(8)
INTERNAL_PHY(9)
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-20.dts
+8 -8
View File
@@ -10,14 +10,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
INTERNAL_PHY(8)
INTERNAL_PHY(9)
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-26.dts
+16 -16
View File
@@ -46,14 +46,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
INTERNAL_PHY(8)
INTERNAL_PHY(9)
@@ -64,14 +64,14 @@
INTERNAL_PHY(14)
INTERNAL_PHY(15)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-28_common.dtsi
+16 -16
View File
@@ -1,14 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
INTERNAL_PHY(8)
INTERNAL_PHY(9)
@@ -19,14 +19,14 @@
INTERNAL_PHY(14)
INTERNAL_PHY(15)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
/* External phy RTL8214FC */
EXTERNAL_SFP_PHY_FULL(24, 0)
target/linux/realtek/dts/rtl8382_hpe_1920-24g.dtsi
+8 -8
View File
@@ -8,14 +8,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
};
&switch0 {
target/linux/realtek/dts/rtl8382_hpe_1920.dtsi
+8 -8
View File
@@ -106,14 +106,14 @@
INTERNAL_PHY(14)
INTERNAL_PHY(15)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
EXTERNAL_SFP_PHY_FULL(24, 0)
EXTERNAL_SFP_PHY_FULL(25, 1)
target/linux/realtek/dts/rtl8382_inaba_aml2-17gp.dts
+9 -9
View File
@@ -95,16 +95,16 @@
INTERNAL_PHY(14)
INTERNAL_PHY(15)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
EXTERNAL_PHY(24)
PHY_C22(24, 24)
};
&switch0 {
target/linux/realtek/dts/rtl8382_iodata_bsh-g24mb.dts
+16 -16
View File
@@ -122,14 +122,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
INTERNAL_PHY(8)
INTERNAL_PHY(9)
@@ -140,14 +140,14 @@
INTERNAL_PHY(14)
INTERNAL_PHY(15)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_panasonic_m16eg-pn28160k.dts
+8 -8
View File
@@ -116,14 +116,14 @@
INTERNAL_PHY(15)
/* RTL8218FB */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_panasonic_m24eg-pn28240k.dts
+16 -16
View File
@@ -107,14 +107,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
INTERNAL_PHY(8)
INTERNAL_PHY(9)
@@ -126,14 +126,14 @@
INTERNAL_PHY(15)
/* RTL8218FB */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_tplink_t1600g-28ts-v3.dts
+16 -16
View File
@@ -95,14 +95,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
INTERNAL_PHY(8)
INTERNAL_PHY(9)
@@ -113,14 +113,14 @@
INTERNAL_PHY(14)
INTERNAL_PHY(15)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_zyxel_gs1900-16-a1.dts
+8 -8
View File
@@ -9,14 +9,14 @@
};
&mdio_bus0 {
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24.dtsi
+16 -16
View File
@@ -49,23 +49,23 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24e-a1.dts
+16 -16
View File
@@ -19,23 +19,23 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24ep-a1.dts
+16 -16
View File
@@ -13,23 +13,23 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24hp-a1.dts
+16 -16
View File
@@ -55,23 +55,23 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24hp-b1.dts
+16 -16
View File
@@ -51,23 +51,23 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts
+48 -48
View File
@@ -12,64 +12,64 @@
&mdio_bus0 {
/* External phy RTL8218B #1 */
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
/* External phy RTL8218B #2 */
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
/* External phy RTL8218B #3 */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
/* External phy RTL8218B #4 */
EXTERNAL_PHY(24)
EXTERNAL_PHY(25)
EXTERNAL_PHY(26)
EXTERNAL_PHY(27)
EXTERNAL_PHY(28)
EXTERNAL_PHY(29)
EXTERNAL_PHY(30)
EXTERNAL_PHY(31)
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
/* External phy RTL8218B #5 */
EXTERNAL_PHY(32)
EXTERNAL_PHY(33)
EXTERNAL_PHY(34)
EXTERNAL_PHY(35)
EXTERNAL_PHY(36)
EXTERNAL_PHY(37)
EXTERNAL_PHY(38)
EXTERNAL_PHY(39)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
/* External phy RTL8218B #6 */
EXTERNAL_PHY(40)
EXTERNAL_PHY(41)
EXTERNAL_PHY(42)
EXTERNAL_PHY(43)
EXTERNAL_PHY(44)
EXTERNAL_PHY(45)
EXTERNAL_PHY(46)
EXTERNAL_PHY(47)
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
/* External phy RTL8214FC */
EXTERNAL_SFP_PHY_FULL(48, 0)
target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts
+8 -8
View File
@@ -172,14 +172,14 @@
reset-post-delay-us = <140000>;
/* External phy RTL8218B */
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
/* External phy RTL8214FC */
EXTERNAL_SFP_PHY_FULL(48, 0)
target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
+48 -48
View File
@@ -25,59 +25,59 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
EXTERNAL_PHY(24)
EXTERNAL_PHY(25)
EXTERNAL_PHY(26)
EXTERNAL_PHY(27)
EXTERNAL_PHY(28)
EXTERNAL_PHY(29)
EXTERNAL_PHY(30)
EXTERNAL_PHY(31)
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
EXTERNAL_PHY(32)
EXTERNAL_PHY(33)
EXTERNAL_PHY(34)
EXTERNAL_PHY(35)
EXTERNAL_PHY(36)
EXTERNAL_PHY(37)
EXTERNAL_PHY(38)
EXTERNAL_PHY(39)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
EXTERNAL_PHY(40)
EXTERNAL_PHY(41)
EXTERNAL_PHY(42)
EXTERNAL_PHY(43)
EXTERNAL_PHY(44)
EXTERNAL_PHY(45)
EXTERNAL_PHY(46)
EXTERNAL_PHY(47)
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
};
&switch0 {
target/linux/realtek/dts/rtl8393_netgear_gs750e.dts
+48 -48
View File
@@ -107,64 +107,64 @@
// reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
/* External phy RTL8218B #1 */
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
/* External phy RTL8218B #2 */
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
/* External phy RTL8218B #3 */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
/* External phy RTL8218B #4 */
EXTERNAL_PHY(24)
EXTERNAL_PHY(25)
EXTERNAL_PHY(26)
EXTERNAL_PHY(27)
EXTERNAL_PHY(28)
EXTERNAL_PHY(29)
EXTERNAL_PHY(30)
EXTERNAL_PHY(31)
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
/* External phy RTL8218B #5 */
EXTERNAL_PHY(32)
EXTERNAL_PHY(33)
EXTERNAL_PHY(34)
EXTERNAL_PHY(35)
EXTERNAL_PHY(36)
EXTERNAL_PHY(37)
EXTERNAL_PHY(38)
EXTERNAL_PHY(39)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
/* External phy RTL8218B #6 */
EXTERNAL_PHY(40)
EXTERNAL_PHY(41)
EXTERNAL_PHY(42)
EXTERNAL_PHY(43)
EXTERNAL_PHY(44)
EXTERNAL_PHY(45)
EXTERNAL_PHY(46)
EXTERNAL_PHY(47)
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
};
&switch0 {
target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts
+48 -48
View File
@@ -243,60 +243,60 @@
};
&mdio_bus0 {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
EXTERNAL_PHY(24)
EXTERNAL_PHY(25)
EXTERNAL_PHY(26)
EXTERNAL_PHY(27)
EXTERNAL_PHY(28)
EXTERNAL_PHY(29)
EXTERNAL_PHY(30)
EXTERNAL_PHY(31)
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
EXTERNAL_PHY(32)
EXTERNAL_PHY(33)
EXTERNAL_PHY(34)
EXTERNAL_PHY(35)
EXTERNAL_PHY(36)
EXTERNAL_PHY(37)
EXTERNAL_PHY(38)
EXTERNAL_PHY(39)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
/* RTL8218FB */
EXTERNAL_PHY(40)
EXTERNAL_PHY(41)
EXTERNAL_PHY(42)
EXTERNAL_PHY(43)
EXTERNAL_PHY(44)
EXTERNAL_PHY(45)
EXTERNAL_PHY(46)
EXTERNAL_PHY(47)
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
};
&switch0 {
target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
+48 -48
View File
@@ -284,64 +284,64 @@
#size-cells = <0>;
/* External phy RTL8218B #1 */
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
/* External phy RTL8218B #2 */
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
/* External phy RTL8218B #3 */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
/* External phy RTL8218B #4 */
EXTERNAL_PHY(24)
EXTERNAL_PHY(25)
EXTERNAL_PHY(26)
EXTERNAL_PHY(27)
EXTERNAL_PHY(28)
EXTERNAL_PHY(29)
EXTERNAL_PHY(30)
EXTERNAL_PHY(31)
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
/* External phy RTL8218B #5 */
EXTERNAL_PHY(32)
EXTERNAL_PHY(33)
EXTERNAL_PHY(34)
EXTERNAL_PHY(35)
EXTERNAL_PHY(36)
EXTERNAL_PHY(37)
EXTERNAL_PHY(38)
EXTERNAL_PHY(39)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
/* External phy RTL8218B #6 */
EXTERNAL_PHY(40)
EXTERNAL_PHY(41)
EXTERNAL_PHY(42)
EXTERNAL_PHY(43)
EXTERNAL_PHY(44)
EXTERNAL_PHY(45)
EXTERNAL_PHY(46)
EXTERNAL_PHY(47)
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
};
};
target/linux/realtek/dts/rtl8393_zyxel_gs1900-48-a1.dts
+48 -48
View File
@@ -239,64 +239,64 @@
&mdio_bus0 {
/* External phy RTL8218B #1 */
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
/* External phy RTL8218B #2 */
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
/* External phy RTL8218B #3 */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
/* External phy RTL8218B #4 */
EXTERNAL_PHY(24)
EXTERNAL_PHY(25)
EXTERNAL_PHY(26)
EXTERNAL_PHY(27)
EXTERNAL_PHY(28)
EXTERNAL_PHY(29)
EXTERNAL_PHY(30)
EXTERNAL_PHY(31)
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
/* External phy RTL8218B #5 */
EXTERNAL_PHY(32)
EXTERNAL_PHY(33)
EXTERNAL_PHY(34)
EXTERNAL_PHY(35)
EXTERNAL_PHY(36)
EXTERNAL_PHY(37)
EXTERNAL_PHY(38)
EXTERNAL_PHY(39)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
/* External phy RTL8218B #6 */
EXTERNAL_PHY(40)
EXTERNAL_PHY(41)
EXTERNAL_PHY(42)
EXTERNAL_PHY(43)
EXTERNAL_PHY(44)
EXTERNAL_PHY(45)
EXTERNAL_PHY(46)
EXTERNAL_PHY(47)
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
};
&switch0 {
target/linux/realtek/dts/rtl839x_zyxel_gs1920-24hp-common.dtsi
+24 -24
View File
@@ -153,34 +153,34 @@
&mdio_bus0 {
/* External phy RTL8218B #1 */
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
/* External phy RTL8218B #2 */
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
/* External phy RTL8218B #3 */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl9301_linksys_lgs328c.dts
+24 -96
View File
@@ -66,108 +66,36 @@
};
&mdio_bus0 {
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy2: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy3: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy4: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy6: ethernet-phy@6 {
reg = <6>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy7: ethernet-phy@7 {
reg = <7>;
compatible = "ethernet-phy-ieee802.3-c22";
};
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
};
&mdio_bus1 {
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy9: ethernet-phy@9 {
reg = <9>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy10: ethernet-phy@10 {
reg = <10>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <11>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy12: ethernet-phy@12 {
reg = <12>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy14: ethernet-phy@14 {
reg = <14>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy15: ethernet-phy@15 {
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c22";
};
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
};
&mdio_bus2 {
phy16: ethernet-phy@16 {
reg = <16>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy17: ethernet-phy@17 {
reg = <17>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy18: ethernet-phy@18 {
reg = <18>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy19: ethernet-phy@19 {
reg = <19>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy20: ethernet-phy@20 {
reg = <20>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy21: ethernet-phy@21 {
reg = <21>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy22: ethernet-phy@22 {
reg = <22>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy23: ethernet-phy@23 {
reg = <23>;
compatible = "ethernet-phy-ieee802.3-c22";
};
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&switch0 {
target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi
+8 -40
View File
@@ -134,46 +134,14 @@
};
&mdio_bus0 {
/* External RTL8224 PHY */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy2: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy3: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy8: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy9: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy10: ethernet-phy@6 {
reg = <6>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy11: ethernet-phy@7 {
reg = <7>;
compatible = "ethernet-phy-ieee802.3-c45";
};
PHY_C45(0, 0)
PHY_C45(1, 1)
PHY_C45(2, 2)
PHY_C45(3, 3)
PHY_C45(8, 4)
PHY_C45(9, 5)
PHY_C45(10, 6)
PHY_C45(11, 7)
};
&switch0 {
target/linux/realtek/dts/rtl9302_plasmacloud_mcx3.dts
+2 -10
View File
@@ -151,16 +151,8 @@
};
&mdio_bus0 {
/* External RTL8224 PHY */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
PHY_C45(0, 0)
PHY_C45(1, 1)
};
&switch0 {
target/linux/realtek/dts/rtl9302_xikestor_sks8300-12e2t2x.dts
+14 -56
View File
@@ -147,71 +147,29 @@
};
&mdio_bus0 {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
};
phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <3>;
};
PHY_C45(0, 0)
PHY_C45(1, 1)
PHY_C45(2, 2)
PHY_C45(3, 3)
};
&mdio_bus1 {
phy8: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy9: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
};
phy10: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
phy11: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <3>;
};
PHY_C45(8, 0)
PHY_C45(9, 1)
PHY_C45(10, 2)
PHY_C45(11, 3)
};
&mdio_bus2 {
phy16: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy17: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
};
phy18: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
phy19: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <3>;
};
PHY_C45(16, 0)
PHY_C45(17, 1)
PHY_C45(18, 2)
PHY_C45(19, 3)
};
&mdio_bus3 {
phy24: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy25: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
};
PHY_C45(24, 0)
PHY_C45(25, 1)
};
&switch0 {
target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-a1.dts
+12
View File
@@ -38,3 +38,15 @@
#thermal-sensor-cells = <0>;
};
};
&port24 {
managed = "in-band-status";
};
&port25 {
managed = "in-band-status";
};
&port26 {
managed = "in-band-status";
};
target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-common.dtsi
+13 -90
View File
@@ -260,97 +260,20 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
pcs-handle = <&serdes2>;
phy-handle = <&phy0>;
phy-mode = "usxgmii";
led-set = <0>;
};
port@1 {
reg = <1>;
label = "lan2";
pcs-handle = <&serdes2>;
phy-handle = <&phy1>;
phy-mode = "usxgmii";
led-set = <0>;
};
port@2 {
reg = <2>;
label = "lan3";
pcs-handle = <&serdes2>;
phy-handle = <&phy2>;
phy-mode = "usxgmii";
led-set = <0>;
};
port@3 {
reg = <3>;
label = "lan4";
pcs-handle = <&serdes2>;
phy-handle = <&phy3>;
phy-mode = "usxgmii";
led-set = <0>;
};
port@4 {
reg = <4>;
label = "lan5";
pcs-handle = <&serdes2>;
phy-handle = <&phy4>;
phy-mode = "usxgmii";
led-set = <0>;
};
port@5 {
reg = <5>;
label = "lan6";
pcs-handle = <&serdes2>;
phy-handle = <&phy5>;
phy-mode = "usxgmii";
led-set = <0>;
};
port@6 {
reg = <6>;
label = "lan7";
pcs-handle = <&serdes2>;
phy-handle = <&phy6>;
phy-mode = "usxgmii";
led-set = <0>;
};
port@7 {
reg = <7>;
label = "lan8";
pcs-handle = <&serdes2>;
phy-handle = <&phy7>;
phy-mode = "usxgmii";
led-set = <0>;
};
SWITCH_PORT_LED(0, 1, 2, 0, usxgmii)
SWITCH_PORT_LED(1, 2, 2, 0, usxgmii)
SWITCH_PORT_LED(2, 3, 2, 0, usxgmii)
SWITCH_PORT_LED(3, 4, 2, 0, usxgmii)
SWITCH_PORT_LED(4, 5, 2, 0, usxgmii)
SWITCH_PORT_LED(5, 6, 2, 0, usxgmii)
SWITCH_PORT_LED(6, 7, 2, 0, usxgmii)
SWITCH_PORT_LED(7, 8, 2, 0, usxgmii)
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes6>;
phy-handle = <&phy24>;
phy-mode = "usxgmii";
led-set = <1>;
};
port@25 {
reg = <25>;
label = "lan10";
pcs-handle = <&serdes7>;
phy-handle = <&phy25>;
phy-mode = "usxgmii";
led-set = <1>;
};
port@26 {
reg = <26>;
label = "lan11";
pcs-handle = <&serdes8>;
phy-handle = <&phy26>;
phy-mode = "usxgmii";
led-set = <1>;
};
port@27 {
SWITCH_PORT_LED(24, 9, 6, 1, usxgmii)
SWITCH_PORT_LED(25, 10, 7, 1, usxgmii)
SWITCH_PORT_LED(26, 11, 8, 1, usxgmii)
port27: port@27 {
reg = <27>;
label = "lan12";
pcs-handle = <&serdes9>;
target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se.dts
+8 -38
View File
@@ -127,47 +127,17 @@
};
&mdio_bus0 {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy8: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
};
phy16: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
phy20: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <3>;
};
PHY_C45(0, 0)
PHY_C45(8, 1)
PHY_C45(16, 2)
PHY_C45(20, 3)
};
&mdio_bus3 {
phy24: ethernet-phy@16 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <16>;
};
phy25: ethernet-phy@17 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <17>;
};
phy26: ethernet-phy@18 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <18>;
};
phy27: ethernet-phy@19 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <19>;
};
PHY_C45(24, 16)
PHY_C45(25, 17)
PHY_C45(26, 18)
PHY_C45(27, 19)
};
&switch0 {
target/linux/realtek/dts/rtl9303_hasivo_s1100wp-8gt-se.dts
+8 -46
View File
@@ -175,55 +175,17 @@
};
&mdio_bus0 {
/* External RTL8221B PHY */
phy0: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
/* External RTL8221B PHY */
phy8: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
/* External RTL8221B PHY */
phy16: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
/* External RTL8221B PHY */
phy20: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c45";
};
PHY_C45(0, 1)
PHY_C45(8, 2)
PHY_C45(16, 3)
PHY_C45(20, 4)
};
&mdio_bus1 {
/* External RTL8221B PHY */
phy24: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
/* External RTL8221B PHY */
phy25: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
/* External RTL8221B PHY */
phy26: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
/* External RTL8221B PHY */
phy27: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c45";
};
PHY_C45(24, 1)
PHY_C45(25, 2)
PHY_C45(26, 3)
PHY_C45(27, 4)
};
&switch0 {
target/linux/realtek/dts/rtl9303_xikestor_sks8300-8t.dts
+8 -38
View File
@@ -130,47 +130,17 @@
};
&mdio_bus0 {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy8: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
};
phy16: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
phy20: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <3>;
};
PHY_C45(0, 0)
PHY_C45(8, 1)
PHY_C45(16, 2)
PHY_C45(20, 3)
};
&mdio_bus1 {
phy24: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy25: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
};
phy26: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
phy27: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <3>;
};
PHY_C45(24, 0)
PHY_C45(25, 1)
PHY_C45(26, 2)
PHY_C45(27, 3)
};
&ethernet0 {
target/linux/realtek/dts/rtl9311_linksys_lgs352c.dts
+48 -192
View File
@@ -80,201 +80,57 @@
};
&mdio_bus0 {
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy2: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy3: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy4: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy6: ethernet-phy@6 {
reg = <6>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy7: ethernet-phy@7 {
reg = <7>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy9: ethernet-phy@9 {
reg = <9>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy10: ethernet-phy@10 {
reg = <10>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <11>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy12: ethernet-phy@12 {
reg = <12>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy14: ethernet-phy@14 {
reg = <14>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy15: ethernet-phy@15 {
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy16: ethernet-phy@16 {
reg = <16>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy17: ethernet-phy@17 {
reg = <17>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy18: ethernet-phy@18 {
reg = <18>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy19: ethernet-phy@19 {
reg = <19>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy20: ethernet-phy@20 {
reg = <20>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy21: ethernet-phy@21 {
reg = <21>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy22: ethernet-phy@22 {
reg = <22>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy23: ethernet-phy@23 {
reg = <23>;
compatible = "ethernet-phy-ieee802.3-c22";
};
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
phy24: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy25: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy26: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy27: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy28: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy29: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy30: ethernet-phy@6 {
reg = <6>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy31: ethernet-phy@7 {
reg = <7>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy32: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy33: ethernet-phy@9 {
reg = <9>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy34: ethernet-phy@10 {
reg = <10>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy35: ethernet-phy@11 {
reg = <11>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy36: ethernet-phy@12 {
reg = <12>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy37: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy38: ethernet-phy@14 {
reg = <14>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy39: ethernet-phy@15 {
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy40: ethernet-phy@16 {
reg = <16>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy41: ethernet-phy@17 {
reg = <17>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy42: ethernet-phy@18 {
reg = <18>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy43: ethernet-phy@19 {
reg = <19>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy44: ethernet-phy@20 {
reg = <20>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy45: ethernet-phy@21 {
reg = <21>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy46: ethernet-phy@22 {
reg = <22>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy47: ethernet-phy@23 {
reg = <23>;
compatible = "ethernet-phy-ieee802.3-c22";
};
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl9312_plasmacloud_common.dtsi
+24 -119
View File
@@ -239,128 +239,33 @@
};
&mdio_bus0 {
/* External RTL8224 PHY */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy4: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy5: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy8: ethernet-phy@4 {
reg = <4>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy9: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy12: ethernet-phy@6 {
reg = <6>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy13: ethernet-phy@7 {
reg = <7>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy16: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy17: ethernet-phy@9 {
reg = <9>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy20: ethernet-phy@10 {
reg = <10>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy21: ethernet-phy@11 {
reg = <11>;
compatible = "ethernet-phy-ieee802.3-c45";
};
PHY_C45(0, 0)
PHY_C45(1, 1)
PHY_C45(4, 2)
PHY_C45(5, 3)
PHY_C45(8, 4)
PHY_C45(9, 5)
PHY_C45(12, 6)
PHY_C45(13, 7)
PHY_C45(16, 8)
PHY_C45(17, 9)
PHY_C45(20, 10)
PHY_C45(21, 11)
};
&mdio_bus1 {
phy24: ethernet-phy@12 {
reg = <12>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy25: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy28: ethernet-phy@14 {
reg = <14>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy29: ethernet-phy@15 {
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy32: ethernet-phy@16 {
reg = <16>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy33: ethernet-phy@17 {
reg = <17>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy36: ethernet-phy@18 {
reg = <18>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy37: ethernet-phy@19 {
reg = <19>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy40: ethernet-phy@20 {
reg = <20>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy41: ethernet-phy@21 {
reg = <21>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy44: ethernet-phy@22 {
reg = <22>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy45: ethernet-phy@23 {
reg = <23>;
compatible = "ethernet-phy-ieee802.3-c45";
};
PHY_C45(24, 12)
PHY_C45(25, 13)
PHY_C45(28, 14)
PHY_C45(29, 15)
PHY_C45(32, 16)
PHY_C45(33, 17)
PHY_C45(36, 18)
PHY_C45(37, 19)
PHY_C45(40, 20)
PHY_C45(41, 21)
PHY_C45(44, 22)
PHY_C45(45, 23)
};
&switch0 {
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c
+8 -47
View File
@@ -24,7 +24,7 @@ int rtldsa_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
u32 msti = 0;
int state;
if (port >= priv->cpu_port)
if (port >= priv->r->cpu_port)
return -EINVAL;
mutex_lock(&priv->reg_mutex);
@@ -298,7 +298,7 @@ static int rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
pcs_node = of_parse_phandle(dn, "pcs-handle", 0);
phy_node = of_parse_phandle(dn, "phy-handle", 0);
if (pn != priv->cpu_port && !phy_node && !pcs_node) {
if (pn != priv->r->cpu_port && !phy_node && !pcs_node) {
dev_err(priv->dev, "Port node %d has neither pcs-handle nor phy-handle\n", pn);
continue;
}
@@ -327,30 +327,7 @@ static int rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
}
}
if (!phy_node) {
if (priv->ports[pn].pcs)
priv->ports[pn].phy_is_integrated = true;
continue;
}
if (of_property_read_bool(phy_node, "phy-is-integrated") &&
!of_property_read_bool(phy_node, "sfp")) {
priv->ports[pn].phy = PHY_RTL8218B_INT;
continue;
}
if (!of_property_read_bool(phy_node, "phy-is-integrated") &&
of_property_read_bool(phy_node, "sfp")) {
priv->ports[pn].phy = PHY_RTL8214FC;
continue;
}
if (!of_property_read_bool(phy_node, "phy-is-integrated") &&
!of_property_read_bool(phy_node, "sfp")) {
priv->ports[pn].phy = PHY_RTL8218B_EXT;
continue;
}
priv->ports[pn].phy = !!phy_node;
}
/* Disable MAC polling the PHY so that we can start configuration */
@@ -836,7 +813,7 @@ int rtl83xx_port_is_under(const struct net_device *dev, struct rtl838x_switch_pr
* }
*/
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
if (!priv->ports[i].dp)
continue;
if (priv->ports[i].dp->user == dev)
@@ -1543,7 +1520,7 @@ static irqreturn_t rtldsa_switch_irq(int irq, void *dev_id)
link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
for (int port = 0; port < priv->cpu_port; port++)
for (int port = 0; port < priv->r->cpu_port; port++)
if (ports & BIT_ULL(port))
dsa_port_phylink_mac_change(ds, port, link & BIT_ULL(port));
@@ -1633,10 +1610,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
case RTL8380_FAMILY_ID:
priv->ds->ops = &rtldsa_83xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
priv->cpu_port = RTL838X_CPU_PORT;
priv->port_mask = 0x1f;
priv->port_width = 1;
priv->fib_entries = 8192;
priv->ds->num_lag_ids = 8;
priv->l2_bucket_size = 4;
priv->n_mst = 64;
@@ -1644,10 +1617,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
case RTL8390_FAMILY_ID:
priv->ds->ops = &rtldsa_83xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
priv->cpu_port = RTL839X_CPU_PORT;
priv->port_mask = 0x3f;
priv->port_width = 2;
priv->fib_entries = 16384;
priv->ds->num_lag_ids = 16;
priv->l2_bucket_size = 4;
priv->n_mst = 256;
@@ -1655,10 +1624,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
case RTL9300_FAMILY_ID:
priv->ds->ops = &rtldsa_93xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
priv->cpu_port = RTL930X_CPU_PORT;
priv->port_mask = 0x1f;
priv->port_width = 1;
priv->fib_entries = 16384;
priv->ds->num_lag_ids = 16;
sw_w32(0, RTL930X_ST_CTRL);
priv->l2_bucket_size = 8;
@@ -1667,18 +1632,14 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
case RTL9310_FAMILY_ID:
priv->ds->ops = &rtldsa_93xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
priv->cpu_port = RTL931X_CPU_PORT;
priv->port_mask = 0x3f;
priv->port_width = 2;
priv->fib_entries = 16384;
priv->ds->num_lag_ids = 16;
sw_w32(0, RTL931x_ST_CTRL);
priv->l2_bucket_size = 8;
priv->n_mst = 128;
break;
}
priv->ds->num_ports = priv->cpu_port + 1;
priv->irq_mask = GENMASK_ULL(priv->cpu_port - 1, 0);
priv->ds->num_ports = priv->r->cpu_port + 1;
priv->irq_mask = GENMASK_ULL(priv->r->cpu_port - 1, 0);
err = rtl83xx_mdio_probe(priv);
if (err) {
@@ -1710,7 +1671,7 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
* dsa_switch_tree, the tree is built when the switch
* is registered by dsa_register_switch
*/
for (int i = 0; i <= priv->cpu_port; i++)
for (int i = 0; i <= priv->r->cpu_port; i++)
priv->ports[i].dp = dsa_to_port(priv->ds, i);
/* Enable link and media change interrupts. Are the SERDES masks needed? */
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/debugfs.c
+4 -4
View File
@@ -324,7 +324,7 @@ static int l2_table_show(struct seq_file *m, void *v)
mutex_lock(&priv->reg_mutex);
for (int i = 0; i < priv->fib_entries; i++) {
for (int i = 0; i < priv->r->fib_entries; i++) {
bucket = i >> 2;
index = i & 0x3;
priv->r->read_l2_entry_using_hash(bucket, index, &e);
@@ -827,7 +827,7 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
(u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));
/* Create one directory per port */
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
if (priv->ports[i].phy) {
ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);
if (ret)
@@ -845,9 +845,9 @@ void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
port_ctrl_regset->regs = port_ctrl_regs;
port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->cpu_port << 2));
port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->r->cpu_port << 2));
debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port);
debugfs_create_u8("id", 0444, port_dir, (u8 *)&priv->r->cpu_port);
/* Create entries for LAGs */
for (int i = 0; i < priv->ds->num_lag_ids; i++) {
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c
+40 -39
View File
@@ -49,7 +49,7 @@ static void rtldsa_enable_phy_polling(struct rtl838x_switch_priv *priv)
msleep(1000);
/* Enable all ports with a PHY, including the SFP-ports */
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
if (priv->ports[i].phy || priv->ports[i].pcs)
v |= BIT_ULL(i);
}
@@ -130,26 +130,26 @@ static void rtldsa_vlan_setup(struct rtl838x_switch_priv *priv)
* egress VLAN(s) must therefore be a member of VLAN 0 to support
* CPU port as ingress when VLAN filtering is enabled.
*/
for (int i = 0; i <= priv->cpu_port; i++) {
for (int i = 0; i <= priv->r->cpu_port; i++) {
rtldsa_vlan_set_pvid(priv, i, 0);
info.member_ports |= BIT_ULL(i);
}
priv->r->vlan_set_tagged(0, &info);
/* Set forwarding action based on inner VLAN tag */
for (int i = 0; i < priv->cpu_port; i++)
for (int i = 0; i < priv->r->cpu_port; i++)
priv->r->vlan_fwd_on_inner(i, true);
}
static void rtldsa_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
{
for (int i = 0; i < priv->cpu_port; i++)
for (int i = 0; i < priv->r->cpu_port; i++)
priv->r->set_receive_management_action(i, BPDU, TRAP2CPU);
}
static void rtldsa_setup_lldp_traps(struct rtl838x_switch_priv *priv)
{
for (int i = 0; i < priv->cpu_port; i++)
for (int i = 0; i < priv->r->cpu_port; i++)
priv->r->set_receive_management_action(i, LLDP, TRAP2CPU);
}
@@ -174,24 +174,24 @@ static int rtldsa_83xx_setup(struct dsa_switch *ds)
for (int i = 0; i < ds->num_ports; i++)
priv->ports[i].enable = false;
priv->ports[priv->cpu_port].enable = true;
priv->ports[priv->r->cpu_port].enable = true;
/* Configure ports so they are disabled by default, but once enabled
* they will work in isolated mode (only traffic between port and CPU).
*/
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
if (priv->ports[i].phy || priv->ports[i].pcs) {
priv->ports[i].pm = BIT_ULL(priv->cpu_port);
priv->ports[i].pm = BIT_ULL(priv->r->cpu_port);
priv->r->traffic_set(i, BIT_ULL(i));
}
}
priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
priv->r->traffic_set(priv->r->cpu_port, BIT_ULL(priv->r->cpu_port));
/* For standalone ports, forward packets even if a static fdb
* entry for the source address exists on another port.
*/
if (priv->r->set_static_move_action) {
for (int i = 0; i <= priv->cpu_port; i++)
for (int i = 0; i <= priv->r->cpu_port; i++)
priv->r->set_static_move_action(i, true);
}
@@ -209,7 +209,7 @@ static int rtldsa_83xx_setup(struct dsa_switch *ds)
priv->r->l2_learning_setup();
rtldsa_port_set_salrn(priv, priv->cpu_port, false);
rtldsa_port_set_salrn(priv, priv->r->cpu_port, false);
ds->assisted_learning_on_cpu_port = true;
/* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
@@ -247,18 +247,18 @@ static int rtldsa_93xx_setup(struct dsa_switch *ds)
/* Disable all ports except CPU port */
for (int i = 0; i < ds->num_ports; i++)
priv->ports[i].enable = false;
priv->ports[priv->cpu_port].enable = true;
priv->ports[priv->r->cpu_port].enable = true;
/* Configure ports so they are disabled by default, but once enabled
* they will work in isolated mode (only traffic between port and CPU).
*/
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
if (priv->ports[i].phy || priv->ports[i].pcs) {
priv->ports[i].pm = BIT_ULL(priv->cpu_port);
priv->ports[i].pm = BIT_ULL(priv->r->cpu_port);
priv->r->traffic_set(i, BIT_ULL(i));
}
}
priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
priv->r->traffic_set(priv->r->cpu_port, BIT_ULL(priv->r->cpu_port));
priv->r->print_matrix();
/* TODO: Initialize statistics */
@@ -273,7 +273,7 @@ static int rtldsa_93xx_setup(struct dsa_switch *ds)
priv->r->l2_learning_setup();
rtldsa_port_set_salrn(priv, priv->cpu_port, false);
rtldsa_port_set_salrn(priv, priv->r->cpu_port, false);
ds->assisted_learning_on_cpu_port = true;
rtldsa_enable_phy_polling(priv);
@@ -377,7 +377,7 @@ static void rtldsa_93xx_phylink_mac_config(struct phylink_config *config,
int port = dp->index;
/* Nothing to be done for the CPU-port */
if (port == priv->cpu_port)
if (port == priv->r->cpu_port)
return;
/* Disable MAC completely */
@@ -526,7 +526,7 @@ static void rtldsa_93xx_phylink_mac_link_up(struct phylink_config *config,
mcr |= RTL930X_RX_PAUSE_EN;
if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port))
mcr |= RTL930X_DUPLEX_MODE;
if (dsa_port_is_cpu(dp) || !priv->ports[port].phy_is_integrated)
if (dsa_port_is_cpu(dp) || priv->ports[port].phy)
mcr |= RTL930X_FORCE_EN;
}
@@ -775,7 +775,7 @@ static void rtldsa_poll_counters(struct work_struct *work)
struct rtl838x_switch_priv,
counters_work);
for (int port = 0; port < priv->cpu_port; port++) {
for (int port = 0; port < priv->r->cpu_port; port++) {
if (!priv->ports[port].phy && !priv->ports[port].pcs)
continue;
@@ -792,7 +792,7 @@ static void rtldsa_init_counters(struct rtl838x_switch_priv *priv)
{
struct rtldsa_counter_state *counters;
for (int port = 0; port < priv->cpu_port; port++) {
for (int port = 0; port < priv->r->cpu_port; port++) {
if (!priv->ports[port].phy && !priv->ports[port].pcs)
continue;
@@ -817,7 +817,7 @@ static void rtldsa_get_strings(struct dsa_switch *ds,
if (stringset != ETH_SS_STATS)
return;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return;
mib_desc = priv->r->mib_desc;
@@ -833,7 +833,7 @@ static void rtldsa_get_ethtool_stats(struct dsa_switch *ds, int port,
const struct rtldsa_mib_desc *mib_desc;
const struct rtldsa_mib_item *mib_item;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return;
mib_desc = priv->r->mib_desc;
@@ -850,7 +850,7 @@ static int rtldsa_get_sset_count(struct dsa_switch *ds, int port, int sset)
if (sset != ETH_SS_STATS)
return 0;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return 0;
return priv->r->mib_desc->list_count;
@@ -862,7 +862,7 @@ static void rtldsa_get_eth_phy_stats(struct dsa_switch *ds, int port,
struct rtl838x_switch_priv *priv = ds->priv;
struct rtldsa_counter_state *counters = &priv->ports[port].counters;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return;
rtldsa_counters_lock(priv, port);
@@ -880,7 +880,7 @@ static void rtldsa_get_eth_mac_stats(struct dsa_switch *ds, int port,
struct rtl838x_switch_priv *priv = ds->priv;
struct rtldsa_counter_state *counters = &priv->ports[port].counters;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return;
rtldsa_counters_lock(priv, port);
@@ -926,7 +926,7 @@ static void rtldsa_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
struct rtl838x_switch_priv *priv = ds->priv;
struct rtldsa_counter_state *counters = &priv->ports[port].counters;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return;
rtldsa_counters_lock(priv, port);
@@ -946,7 +946,7 @@ static void rtldsa_get_rmon_stats(struct dsa_switch *ds, int port,
const struct rtldsa_mib_desc *mib_desc;
struct rtldsa_counter_state *counters = &priv->ports[port].counters;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return;
mib_desc = priv->r->mib_desc;
@@ -992,7 +992,7 @@ static void rtldsa_get_stats64(struct dsa_switch *ds, int port,
struct rtl838x_switch_priv *priv = ds->priv;
struct rtldsa_counter_state *counters = &priv->ports[port].counters;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return;
if (priv->r->stat_update_counters_atomically)
@@ -1010,7 +1010,7 @@ static void rtldsa_get_pause_stats(struct dsa_switch *ds, int port,
struct rtl838x_switch_priv *priv = ds->priv;
struct rtldsa_counter_state *counters = &priv->ports[port].counters;
if (port < 0 || port >= priv->cpu_port)
if (port < 0 || port >= priv->r->cpu_port)
return;
rtldsa_counters_lock(priv, port);
@@ -1078,7 +1078,7 @@ static int rtldsa_port_enable(struct dsa_switch *ds, int port, struct phy_device
return 0;
/* add port to switch mask of CPU_PORT */
priv->r->traffic_enable(priv->cpu_port, port);
priv->r->traffic_enable(priv->r->cpu_port, port);
/* add all other ports in the same bridge to switch mask of port */
priv->r->traffic_set(port, priv->ports[port].pm);
@@ -1103,7 +1103,7 @@ static void rtldsa_port_disable(struct dsa_switch *ds, int port)
/* BUG: This does not work on RTL931X */
/* remove port from switch mask of CPU_PORT */
priv->r->traffic_disable(priv->cpu_port, port);
priv->r->traffic_disable(priv->r->cpu_port, port);
/* remove all other ports from switch mask of port */
priv->r->traffic_set(port, 0);
@@ -1452,13 +1452,14 @@ static void rtldsa_port_xstp_state_set(struct rtl838x_switch_priv *priv, int por
u8 state, u16 mst_slot)
__must_hold(&priv->reg_mutex)
{
/* 838x/930x have 28 ports and 2 bit fields other devices 4 bit fields. */
int n = priv->r->cpu_port == RTL838X_CPU_PORT ? 2 : 4;
u32 port_state[4];
int index, bit;
int pos = port;
int n = priv->port_width << 1;
/* Ports above or equal CPU port can never be configured */
if (port >= priv->cpu_port)
if (port >= priv->r->cpu_port)
return;
/* For the RTL839x and following, the bits are left-aligned, 838x and 930x
@@ -1557,7 +1558,7 @@ static int rtldsa_vlan_filtering(struct dsa_switch *ds, int port,
* 2: Trap packet to CPU port
* The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
*/
if (port != priv->cpu_port) {
if (port != priv->r->cpu_port) {
priv->r->set_vlan_igr_filter(port, IGR_DROP);
priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
} else {
@@ -1567,7 +1568,7 @@ static int rtldsa_vlan_filtering(struct dsa_switch *ds, int port,
} else {
/* Disable ingress and egress filtering */
if (port != priv->cpu_port)
if (port != priv->r->cpu_port)
priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
@@ -1638,7 +1639,7 @@ static int rtldsa_vlan_add(struct dsa_switch *ds, int port,
* of now no such logic is in place. So for the CPU port keep the fixed
* PVID=0 from initial setup in place and ignore all subsequent settings.
*/
if (port != priv->cpu_port) {
if (port != priv->r->cpu_port) {
if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
rtldsa_vlan_set_pvid(priv, port, vlan->vid);
else if (priv->ports[port].pvid == vlan->vid)
@@ -2001,7 +2002,7 @@ static int rtldsa_port_fdb_dump(struct dsa_switch *ds, int port,
mutex_lock(&priv->reg_mutex);
for (int i = 0; i < priv->fib_entries; i++) {
for (int i = 0; i < priv->r->fib_entries; i++) {
priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
if (!e.valid)
@@ -2421,7 +2422,7 @@ static int rtldsa_port_lag_join(struct dsa_switch *ds,
mutex_lock(&priv->reg_mutex);
if (port >= priv->cpu_port) {
if (port >= priv->r->cpu_port) {
err = -EINVAL;
goto out;
}
@@ -2465,7 +2466,7 @@ static int rtldsa_port_lag_leave(struct dsa_switch *ds, int port,
goto out;
}
if (port >= priv->cpu_port) {
if (port >= priv->r->cpu_port) {
err = -EINVAL;
goto out;
}
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/qos.c
+6 -6
View File
@@ -44,7 +44,7 @@ static void rtl839x_read_out_q_table(int port)
u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)
{
if (port > priv->cpu_port)
if (port > priv->r->cpu_port)
return 0;
return sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff;
@@ -55,7 +55,7 @@ int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate
{
u32 old_rate;
if (port > priv->cpu_port)
if (port > priv->r->cpu_port)
return -1;
old_rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port));
@@ -70,7 +70,7 @@ u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)
u32 rate;
pr_debug("%s: Getting egress rate on port %d to %d\n", __func__, port, rate);
if (port >= priv->cpu_port)
if (port >= priv->r->cpu_port)
return 0;
mutex_lock(&priv->reg_mutex);
@@ -92,7 +92,7 @@ int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate
u32 old_rate;
pr_debug("%s: Setting egress rate on port %d to %d\n", __func__, port, rate);
if (port >= priv->cpu_port)
if (port >= priv->r->cpu_port)
return -1;
mutex_lock(&priv->reg_mutex);
@@ -197,7 +197,7 @@ static void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, i
mutex_lock(&priv->reg_mutex);
/* Check whether we need to empty the egress queue of that port due to Errata E0014503 */
if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) {
if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->r->cpu_port) {
/* Read Operations, Adminstatrion and Management control register */
oam_state = sw_r32(RTL839X_OAM_CTRL);
@@ -231,7 +231,7 @@ static void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, i
sw_w32_mask(BIT(19), sched ? BIT(19) : 0, RTL839X_TBL_ACCESS_DATA_2(8));
rtl839x_write_scheduling_table(port);
if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) {
if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->r->cpu_port) {
/* Restore OAM state to control register */
sw_w32(oam_state, RTL839X_OAM_CTRL);
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c
+4 -2
View File
@@ -737,7 +737,7 @@ static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
/* Enable EEE MAC support on ports */
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
if (priv->ports[i].phy)
priv->r->set_mac_eee(priv, i, enable);
}
@@ -1576,7 +1576,7 @@ static void rtl838x_pie_init(struct rtl838x_switch_priv *priv)
mutex_init(&priv->pie_mutex);
/* Enable ACL lookup on all ports, including CPU_PORT */
for (int i = 0; i <= priv->cpu_port; i++)
for (int i = 0; i <= priv->r->cpu_port; i++)
sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));
/* Power on all PIE blocks */
@@ -1807,6 +1807,8 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
struct netdev_lag_upper_info *info);
const struct rtldsa_config rtldsa_838x_cfg = {
.cpu_port = RTL838X_CPU_PORT,
.fib_entries = 8192,
.mask_port_reg_be = rtl838x_mask_port_reg,
.set_port_reg_be = rtl838x_set_port_reg,
.get_port_reg_be = rtl838x_get_port_reg,
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.h
+3 -15
View File
@@ -896,15 +896,6 @@ typedef enum {
*/
#define RTLDSA_COUNTERS_FAST_POLL_INTERVAL (3 * HZ)
enum phy_type {
PHY_NONE = 0,
PHY_RTL838X_SDS = 1,
PHY_RTL8218B_INT = 2,
PHY_RTL8218B_EXT = 3,
PHY_RTL8214FC = 4,
PHY_RTL839X_SDS = 5,
};
enum pbvlan_type {
PBVLAN_TYPE_INNER = 0,
PBVLAN_TYPE_OUTER,
@@ -1003,14 +994,13 @@ struct rtldsa_93xx_lag_entry {
struct rtldsa_port {
bool enable:1;
bool phy_is_integrated:1;
bool phy:1;
bool isolated:1;
bool rate_police_egress:1;
bool rate_police_ingress:1;
u64 pm;
u16 pvid;
bool eee_enabled;
enum phy_type phy;
struct phylink_pcs *pcs;
int led_set;
int leds_on_this_port;
@@ -1422,7 +1412,9 @@ struct rtldsa_config {
int imr_glb;
int n_counters;
int n_pie_blocks;
u8 cpu_port;
u8 port_ignore;
u32 fib_entries;
int trk_ctrl;
int trk_hash_ctrl;
void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
@@ -1525,11 +1517,7 @@ struct rtl838x_switch_priv {
int mirror_group_ports[4];
struct mii_bus *parent_bus;
const struct rtldsa_config *r;
u8 cpu_port;
u8 port_mask;
u8 port_width;
u64 irq_mask;
u32 fib_entries;
int l2_bucket_size;
u16 n_mst;
struct dentry *dbgfs_dir;
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c
+5 -3
View File
@@ -787,7 +787,7 @@ static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
/* Setup EEE on all ports */
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
if (priv->ports[i].phy)
priv->r->set_mac_eee(priv, i, enable);
}
@@ -1592,8 +1592,8 @@ static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv)
struct net_device *dev;
u64 mac;
pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->cpu_port].dp);
dev = priv->ports[priv->cpu_port].dp->user;
pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->r->cpu_port].dp);
dev = priv->ports[priv->r->cpu_port].dp->user;
mac = ether_addr_to_u64(dev->dev_addr);
for (int i = 0; i < 15; i++) {
@@ -1722,6 +1722,8 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
struct netdev_lag_upper_info *info);
const struct rtldsa_config rtldsa_839x_cfg = {
.cpu_port = RTL839X_CPU_PORT,
.fib_entries = 16384,
.mask_port_reg_be = rtl839x_mask_port_reg_be,
.set_port_reg_be = rtl839x_set_port_reg_be,
.get_port_reg_be = rtl839x_get_port_reg_be,
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c
+5 -3
View File
@@ -1187,7 +1187,7 @@ static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
pr_debug("Setting up EEE, state: %d\n", enable);
/* Setup EEE on all ports */
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
if (priv->ports[i].phy)
priv->r->set_mac_eee(priv, i, enable);
}
@@ -2245,7 +2245,7 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
pr_debug("%s\n", __func__);
/* Enable ACL lookup on all ports, including CPU_PORT */
for (int i = 0; i <= priv->cpu_port; i++)
for (int i = 0; i <= priv->r->cpu_port; i++)
sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
/* Include IPG in metering */
@@ -2679,7 +2679,7 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv)
rtldsa_930x_led_get_forced(node, leds_in_set, forced_leds_per_port);
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
int pos = (i << 1) % 32;
u32 set;
@@ -2793,6 +2793,8 @@ static void rtldsa_930x_qos_init(struct rtl838x_switch_priv *priv)
}
const struct rtldsa_config rtldsa_930x_cfg = {
.cpu_port = RTL930X_CPU_PORT,
.fib_entries = 16384,
.mask_port_reg_be = rtl838x_mask_port_reg,
.set_port_reg_be = rtl838x_set_port_reg,
.get_port_reg_be = rtl838x_get_port_reg,
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c
+7 -5
View File
@@ -1490,7 +1490,7 @@ static void rtl931x_pie_init(struct rtl838x_switch_priv *priv)
pr_debug("%s\n", __func__);
/* Enable ACL lookup on all ports, including CPU_PORT */
for (int i = 0; i <= priv->cpu_port; i++)
for (int i = 0; i <= priv->r->cpu_port; i++)
sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i));
/* Include IPG in metering */
@@ -1670,7 +1670,7 @@ static void rtldsa_931x_led_init(struct rtl838x_switch_priv *priv)
rtldsa_931x_led_get_forced(node, leds_in_set, forced_leds_per_port);
for (int i = 0; i < priv->cpu_port; i++) {
for (int i = 0; i < priv->r->cpu_port; i++) {
int pos = (i << 1) % 32;
u32 set;
@@ -1688,10 +1688,10 @@ static void rtldsa_931x_led_init(struct rtl838x_switch_priv *priv)
sw_w32_mask(0x3 << pos, (priv->ports[i].leds_on_this_port - 1) << pos,
RTL931X_LED_PORT_NUM_CTRL(i));
if (priv->ports[i].phy_is_integrated)
pm_fiber |= BIT_ULL(i);
else
if (priv->ports[i].phy)
pm_copper |= BIT_ULL(i);
else
pm_fiber |= BIT_ULL(i);
set = priv->ports[i].led_set;
sw_w32_mask(0, set << pos, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i));
@@ -1934,6 +1934,8 @@ static void rtldsa_931x_qos_init(struct rtl838x_switch_priv *priv)
}
const struct rtldsa_config rtldsa_931x_cfg = {
.cpu_port = RTL931X_CPU_PORT,
.fib_entries = 16384, /* TODO: has 32K but code cannot handle that */
.mask_port_reg_be = rtl839x_mask_port_reg_be,
.set_port_reg_be = rtl839x_set_port_reg_be,
.get_port_reg_be = rtl839x_get_port_reg_be,
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c
+1 -1
View File
@@ -159,7 +159,7 @@ static int rtl83xx_add_flow(struct rtl838x_switch_priv *priv, struct flow_cls_of
case FLOW_ACTION_TRAP:
pr_debug("%s: TRAP\n", __func__);
flow->rule.fwd_data = priv->cpu_port;
flow->rule.fwd_data = priv->r->cpu_port;
flow->rule.fwd_act = PIE_ACT_REDIRECT_TO_PORT;
rtl83xx_flow_bypass_all(flow);
break;
target/linux/realtek/patches-6.12/025-01-v7.0-i2c-rtl9300-remove-const-cast.patch
+54
View File
@@ -0,0 +1,54 @@
From fc31008d5f57e71afa124550ca01b4399434435e Mon Sep 17 00:00:00 2001
From: Rosen Penev <rosenp@gmail.com>
Date: Tue, 16 Dec 2025 22:30:26 -0800
Subject: i2c: rtl9300: remove const cast
These casts are used to remove const for no good reason. Fix the types
instead.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20251217063027.37987-2-rosenp@gmail.com
---
drivers/i2c/busses/i2c-rtl9300.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/i2c/busses/i2c-rtl9300.c
+++ b/drivers/i2c/busses/i2c-rtl9300.c
@@ -129,7 +129,7 @@ static int rtl9310_i2c_select_scl(struct
static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan)
{
- struct rtl9300_i2c_drv_data *drv_data;
+ const struct rtl9300_i2c_drv_data *drv_data;
int ret;
if (i2c->sda_num == chan->sda_num)
@@ -139,7 +139,7 @@ static int rtl9300_i2c_config_chan(struc
if (ret)
return ret;
- drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
+ drv_data = device_get_match_data(i2c->dev);
ret = drv_data->select_scl(i2c, i2c->scl_num);
if (ret)
return ret;
@@ -372,7 +372,7 @@ static int rtl9300_i2c_probe(struct plat
struct device *dev = &pdev->dev;
struct rtl9300_i2c *i2c;
struct fwnode_handle *child;
- struct rtl9300_i2c_drv_data *drv_data;
+ const struct rtl9300_i2c_drv_data *drv_data;
struct reg_field fields[F_NUM_FIELDS];
u32 clock_freq, scl_num, sda_num;
int ret, i = 0;
@@ -399,7 +399,7 @@ static int rtl9300_i2c_probe(struct plat
platform_set_drvdata(pdev, i2c);
- drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
+ drv_data = device_get_match_data(i2c->dev);
if (device_get_child_node_count(dev) > drv_data->max_nchan)
return dev_err_probe(dev, -EINVAL, "Too many channels\n");
target/linux/realtek/patches-6.12/025-02-v7.0-i2c-rtl9300-use-of-instead-of-fwnode.patch
+56
View File
@@ -0,0 +1,56 @@
From f6551f7861aca09cb2fdf675d6bb9ca2ffa9038a Mon Sep 17 00:00:00 2001
From: Rosen Penev <rosenp@gmail.com>
Date: Tue, 16 Dec 2025 22:30:27 -0800
Subject: i2c: rtl9300: use of instead of fwnode
Avoids having to use to_of_node and just assign directly. This is an OF
only driver anyway.
Use _scoped for the for each loop to avoid refcount leaks.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20251217063027.37987-3-rosenp@gmail.com
---
drivers/i2c/busses/i2c-rtl9300.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
--- a/drivers/i2c/busses/i2c-rtl9300.c
+++ b/drivers/i2c/busses/i2c-rtl9300.c
@@ -371,7 +371,6 @@ static int rtl9300_i2c_probe(struct plat
{
struct device *dev = &pdev->dev;
struct rtl9300_i2c *i2c;
- struct fwnode_handle *child;
const struct rtl9300_i2c_drv_data *drv_data;
struct reg_field fields[F_NUM_FIELDS];
u32 clock_freq, scl_num, sda_num;
@@ -415,15 +414,15 @@ static int rtl9300_i2c_probe(struct plat
return ret;
i = 0;
- device_for_each_child_node(dev, child) {
+ for_each_child_of_node_scoped(dev->of_node, child) {
struct rtl9300_i2c_chan *chan = &i2c->chans[i];
struct i2c_adapter *adap = &chan->adap;
- ret = fwnode_property_read_u32(child, "reg", &sda_num);
+ ret = of_property_read_u32(child, "reg", &sda_num);
if (ret)
return ret;
- ret = fwnode_property_read_u32(child, "clock-frequency", &clock_freq);
+ ret = of_property_read_u32(child, "clock-frequency", &clock_freq);
if (ret)
clock_freq = I2C_MAX_STANDARD_MODE_FREQ;
@@ -449,7 +448,7 @@ static int rtl9300_i2c_probe(struct plat
adap->retries = 3;
adap->dev.parent = dev;
i2c_set_adapdata(adap, chan);
- adap->dev.of_node = to_of_node(child);
+ adap->dev.of_node = child;
snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_num);
i++;
target/linux/realtek/patches-6.12/100-rtl9300-i2c-add-more-speeds.patch
+1 -1
View File
@@ -37,7 +37,7 @@ Signed-off-by: Jan Kantert <jan-kernel@kantert.net>
struct rtl9300_i2c;
struct rtl9300_i2c_chan {
@@ -434,6 +440,12 @@ static int rtl9300_i2c_probe(struct plat
@@ -433,6 +439,12 @@ static int rtl9300_i2c_probe(struct plat
case I2C_MAX_FAST_MODE_FREQ:
chan->bus_freq = RTL9300_I2C_FAST_FREQ;
break;
target/linux/realtek/patches-6.12/308-tune-switch-4kec.patch
+3 -3
View File
@@ -2,7 +2,7 @@ From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Fri, 13 Jun 2025 20:25:37 +0100
Subject: [PATCH] realtek: set mtune 4kec for RTL838x targets
Generic patches will always force the gcc kernel tuning to 34kc. With RTL838x
Generic patches will always force the gcc kernel tuning to 24kc. With RTL838x
being only 4kec this does not harm but is not right. Match the tuning properly.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
@@ -13,10 +13,10 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
@@ -164,6 +164,11 @@ cflags-$(CONFIG_CPU_R4X00) += $(call cc-
cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=34kc -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=24kc -Wa,--trap
+
+#ifdef CONFIG_RTL838X
+cflags-$(CONFIG_CPU_MIPS32_R2) := $(subst 34kc,4kec,$(cflags-$(CONFIG_CPU_MIPS32_R2)))
+cflags-$(CONFIG_CPU_MIPS32_R2) := $(subst 24kc,4kec,$(cflags-$(CONFIG_CPU_MIPS32_R2)))
+#endif
+
cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg
target/linux/realtek/patches-6.12/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch
+2 -2
View File
@@ -70,7 +70,7 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
struct dsa_chip_data {
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -481,7 +481,7 @@ struct dsa_switch {
@@ -480,7 +480,7 @@ struct dsa_switch {
/*
* User mii_bus and devices for the individual ports.
*/
@@ -79,7 +79,7 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
struct mii_bus *user_mii_bus;
/* Ageing Time limits in msecs */
@@ -617,24 +617,24 @@ static inline bool dsa_is_user_port(stru
@@ -616,24 +616,24 @@ static inline bool dsa_is_user_port(stru
dsa_switch_for_each_port_continue_reverse((_dp), (_ds)) \
if (dsa_port_is_cpu((_dp)))
target/linux/realtek/patches-6.12/721-net-dsa-add-support-for-tag-rtl-otto.patch
+2 -2
View File
@@ -39,9 +39,9 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
#define DSA_TAG_PROTO_MXL862_8021Q_VALUE 31
+#define DSA_TAG_PROTO_RTL_OTTO_VALUE 32
enum dsa_tag_protocol {
@@ -92,6 +93,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -91,6 +92,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_VSC73XX_8021Q = DSA_TAG_PROTO_VSC73XX_8021Q_VALUE,
DSA_TAG_PROTO_MXL862 = DSA_TAG_PROTO_MXL862_VALUE,
DSA_TAG_PROTO_MXL862_8021Q = DSA_TAG_PROTO_MXL862_8021Q_VALUE,
target/linux/realtek/patches-6.18/025-01-v7.0-i2c-rtl9300-remove-const-cast.patch
+54
View File
@@ -0,0 +1,54 @@
From fc31008d5f57e71afa124550ca01b4399434435e Mon Sep 17 00:00:00 2001
From: Rosen Penev <rosenp@gmail.com>
Date: Tue, 16 Dec 2025 22:30:26 -0800
Subject: i2c: rtl9300: remove const cast
These casts are used to remove const for no good reason. Fix the types
instead.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20251217063027.37987-2-rosenp@gmail.com
---
drivers/i2c/busses/i2c-rtl9300.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/i2c/busses/i2c-rtl9300.c
+++ b/drivers/i2c/busses/i2c-rtl9300.c
@@ -129,7 +129,7 @@ static int rtl9310_i2c_select_scl(struct
static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan)
{
- struct rtl9300_i2c_drv_data *drv_data;
+ const struct rtl9300_i2c_drv_data *drv_data;
int ret;
if (i2c->sda_num == chan->sda_num)
@@ -139,7 +139,7 @@ static int rtl9300_i2c_config_chan(struc
if (ret)
return ret;
- drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
+ drv_data = device_get_match_data(i2c->dev);
ret = drv_data->select_scl(i2c, i2c->scl_num);
if (ret)
return ret;
@@ -372,7 +372,7 @@ static int rtl9300_i2c_probe(struct plat
struct device *dev = &pdev->dev;
struct rtl9300_i2c *i2c;
struct fwnode_handle *child;
- struct rtl9300_i2c_drv_data *drv_data;
+ const struct rtl9300_i2c_drv_data *drv_data;
struct reg_field fields[F_NUM_FIELDS];
u32 clock_freq, scl_num, sda_num;
int ret, i = 0;
@@ -399,7 +399,7 @@ static int rtl9300_i2c_probe(struct plat
platform_set_drvdata(pdev, i2c);
- drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
+ drv_data = device_get_match_data(i2c->dev);
if (device_get_child_node_count(dev) > drv_data->max_nchan)
return dev_err_probe(dev, -EINVAL, "Too many channels\n");
target/linux/realtek/patches-6.18/025-02-v7.0-i2c-rtl9300-use-of-instead-of-fwnode.patch
+56
View File
@@ -0,0 +1,56 @@
From f6551f7861aca09cb2fdf675d6bb9ca2ffa9038a Mon Sep 17 00:00:00 2001
From: Rosen Penev <rosenp@gmail.com>
Date: Tue, 16 Dec 2025 22:30:27 -0800
Subject: i2c: rtl9300: use of instead of fwnode
Avoids having to use to_of_node and just assign directly. This is an OF
only driver anyway.
Use _scoped for the for each loop to avoid refcount leaks.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20251217063027.37987-3-rosenp@gmail.com
---
drivers/i2c/busses/i2c-rtl9300.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
--- a/drivers/i2c/busses/i2c-rtl9300.c
+++ b/drivers/i2c/busses/i2c-rtl9300.c
@@ -371,7 +371,6 @@ static int rtl9300_i2c_probe(struct plat
{
struct device *dev = &pdev->dev;
struct rtl9300_i2c *i2c;
- struct fwnode_handle *child;
const struct rtl9300_i2c_drv_data *drv_data;
struct reg_field fields[F_NUM_FIELDS];
u32 clock_freq, scl_num, sda_num;
@@ -415,15 +414,15 @@ static int rtl9300_i2c_probe(struct plat
return ret;
i = 0;
- device_for_each_child_node(dev, child) {
+ for_each_child_of_node_scoped(dev->of_node, child) {
struct rtl9300_i2c_chan *chan = &i2c->chans[i];
struct i2c_adapter *adap = &chan->adap;
- ret = fwnode_property_read_u32(child, "reg", &sda_num);
+ ret = of_property_read_u32(child, "reg", &sda_num);
if (ret)
return ret;
- ret = fwnode_property_read_u32(child, "clock-frequency", &clock_freq);
+ ret = of_property_read_u32(child, "clock-frequency", &clock_freq);
if (ret)
clock_freq = I2C_MAX_STANDARD_MODE_FREQ;
@@ -449,7 +448,7 @@ static int rtl9300_i2c_probe(struct plat
adap->retries = 3;
adap->dev.parent = dev;
i2c_set_adapdata(adap, chan);
- adap->dev.of_node = to_of_node(child);
+ adap->dev.of_node = child;
snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_num);
i++;
target/linux/realtek/patches-6.18/100-rtl9300-i2c-add-more-speeds.patch
+1 -1
View File
@@ -37,7 +37,7 @@ Signed-off-by: Jan Kantert <jan-kernel@kantert.net>
struct rtl9300_i2c;
struct rtl9300_i2c_chan {
@@ -434,6 +440,12 @@ static int rtl9300_i2c_probe(struct plat
@@ -433,6 +439,12 @@ static int rtl9300_i2c_probe(struct plat
case I2C_MAX_FAST_MODE_FREQ:
chan->bus_freq = RTL9300_I2C_FAST_FREQ;
break;
target/linux/realtek/patches-6.18/308-tune-switch-4kec.patch
+3 -3
View File
@@ -2,7 +2,7 @@ From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Fri, 13 Jun 2025 20:25:37 +0100
Subject: [PATCH] realtek: set mtune 4kec for RTL838x targets
Generic patches will always force the gcc kernel tuning to 34kc. With RTL838x
Generic patches will always force the gcc kernel tuning to 24kc. With RTL838x
being only 4kec this does not harm but is not right. Match the tuning properly.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
@@ -13,10 +13,10 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
@@ -160,6 +160,11 @@ cflags-$(CONFIG_CPU_R4X00) += $(call cc-
cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=34kc -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=24kc -Wa,--trap
+
+#ifdef CONFIG_RTL838X
+cflags-$(CONFIG_CPU_MIPS32_R2) := $(subst 34kc,4kec,$(cflags-$(CONFIG_CPU_MIPS32_R2)))
+cflags-$(CONFIG_CPU_MIPS32_R2) := $(subst 24kc,4kec,$(cflags-$(CONFIG_CPU_MIPS32_R2)))
+#endif
+
cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg